TEXAS INSTRUMENTS MSP430x22x2, MSP430x22x4 Technical data

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MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption

-- Active Mode: 270 μAat1MHz,2.2V

-- Standby Mode: 0.7 μA

-- Off Mode (RAM Retention): 0.1 μA

D Ultrafast Wake-Up From Standby Mode in

Less Than 1 μs

D 16-Bit RISC Architecture, 62.5-ns

Instruction Cycle Time

D Basic Clock Module Configurations:

-- Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1%

-- Internal Very-Low-Power Low-Frequency Oscillator

-- 32-kHz Crystal

-- High-Frequency Crystal up to 16 MHz

-- Resonator

-- External Digital Clock Source

-- External Resistor

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_B With Three

Capture/Compare Registers

D Universal Serial Communication Interface

-- Enhanced UART Supporting Auto-Baudrate Detection (LIN)

-- IrDA Encoder and Decoder

-- Synchronous SPI

C™

-- I

D 10-Bit, 200 -ksps A/D Converter With

Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller

D Two Configurable Operational Amplifiers

(MSP430x22x4 Only)

D Brownout Detector D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Bootstrap Loader D On Chip Emulation Module D Family Members Include:

MSP430F2232: 8KB + 256B Flash Memory

512B RAM

MSP430F2252: 16KB + 256B Flash Memory

512B RAM

MSP430F2272: 32KB + 256B Flash Memory

1KB RAM

MSP430F2234: 8KB + 256B Flash Memory

512B RAM

MSP430F2254: 16KB + 256B Flash Memory

512B RAM

MSP430F2274: 32KB + 256B Flash Memory

1KB RAM Available in a 38-Pin Thin Shrink Small-Outline Package (TSSOP) and 40-Pin QFN Package

D For Complete Module Descriptions, Refer

to the MSP430x2xx Family User’s Guide

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.

The MSP430x22xx series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general-purpose operational amplifiers in the MSP430x22x4 devices, and 32 I/O pins.

Typicalapplications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front ends are another area of application.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

-- 4 0 °Cto85°C

-- 4 0 °C to 105°C

†

Product Preview

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

38-PIN TSSOP

(DA)

MSP430F2232IDA MSP430F2252IDA MSP430F2272IDA MSP430F2234IDA MSP430F2254IDA MSP430F2274IDA

MSP430F2232TDA MSP430F2252TDA MSP430F2272TDA

MSP430F2234TDA MSP430F2254TDA MSP430F2274TDA

PLASTIC

40-PIN QFN

MSP430F2232IRHA MSP430F2252IRHA MSP430F2272IRHA MSP430F2234IRHA MSP430F2254IRHA MSP430F2274IRHA

†

MSP430F2232TRHA

†

MSP430F2252TRHA

†

MSP430F2272TRHA

MSP430F2234TRHA MSP430F2254TRHA MSP430F2274TRHA

(RHA)

†

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MSP430x22x2 device pinout, DA package

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

1TEST/SBWTCK

2DVCC

3P2.5/Rosc

DVSS

XOUT/P2 .7

XIN/P2 .6

RST /NMI /SBWTDIO

P2.0/ACLK /A0

P2 .1 /TAINCLK /SMCLK /A1

P2 .2 /TA 0/A2

P3 .0 /UCB 0STE /UCA 0CLK /A 5

P3 .1 /UCB 0SIMO /UCB 0SDA

P3 .2/UCB 0SOMI /UCB 0SCL

P3 .3 /UCB 0CLK /UCA 0STE

AVSS

P4.0/TB 0

P4.1/TB 1

P4.2/TB 2

18 P4.4 /TB 1/A 13

MSP430x22x4 device pinout, DA package

38 P1.7 /TA 2/TDO /TDI

37 P1.6 /TA 1/TDI

36 P1.5 /TA 0/TMS

35 P 1.4/SMCLK /TCK

34 P 1.3/TA 2

33 P 1.2/TA 1

32 P 1.1/TA 0

31 P 1.0/TACLK /ADC 10 CLK

30 P2.4 /TA 2/A 4 /VREF+/ VeREF +

29 P2.3 /TA 1/A 3 /VREF-- /VeREF --

28 P 3.7/A7

27 P 3.6/A6

26 P 3.5/UCA 0RXD /UCA0SOMI

25 P 3.4/UCA 0 TXD /UCA0SIMO

P4.7/TBCLK

P4.6/TBOUTH /A15

23AVC C

P4.5 /TB 2/A 14

P4.3 /TB 0/A 12

DVSS

XOUT/P 2.7

XIN /P2. 6

RST /NMI /SBWTDIO

P2 .0 / ACLK /A0/OA 0I0

P2 .1 /TAINCLK /SMCLK /A1 /OA 0O

P2 .2 /TA 0/A2 /OA 0I1

P3 .0 /UCB 0STE /UCA 0CLK /A 5

P3 .1 /UCB 0SIMO/UCB 0 SDA

P3.2/UCB 0SOMI/UCB 0 SCL

P3 .3 /UCB 0CLK /UCA 0STE

AVSS

P4 .0 /TB 0

P4 .1 /TB 1

P4 .2 /TB 2

1TEST/SBWTCK

2DVCC

3P2.5/Rosc

18 P 4.4/TB 1/A13 /OA1O

38 P1 .7/TA2/TDO /TDI

37 P 1.6/TA 1/TDI

36 P 1.5/TA 0 /TMS

35 P 1.4/SMCLK /TCK

34 P 1.3/TA 2

33 P 1.2/TA 1

32 P 1.1/TA 0

31 P 1.0/TACLK /ADC 10 CLK

30 P 2.4/TA 2 /A 4/VREF +/VeREF +/ OA 1I0

29 P 2.3/TA 1 /A 3/VREF --/ VeREF --/OA 1I1/OA 1O

28 P 3.7/A7/OA 1I2

27 P 3.6/A6/OA 0I2

26 P 3.5/UCA 0RXD /UCA0SOMI

25 P 3.4/UCA 0TXD /UCA0SIMO

P4.7/TBCLK

P4.6/TBOUTH/A15/OA1I3

23AVC C

P4.5/TB2/A14 /OA0I3

P4.3/TB0/A12 /OA0O

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MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

MSP430x22x2 device pinout, RHA package

XOUT /P2.7

XIN /P2. 6

DVSS

RST /NMI /SBWTDIO

P2.0/ACLK /A0

P2 .1 /TAINCLK /SMCLK /A 1

P2.2 /TA 0/A 2

P3 .0 /UCB 0STE /UCA 0CLK /A5

P3 .1 /UCB 0SIMO /UCB 0SDA

P2.5/Rosc

1DVSS

12 14 15 16 17 18 19

P3.2/UCB0SOMI/UCB0SCL

TEST/SBWTCK

DVCC

P1.7/T A2/TD O /T D I

3839 37 36 35 34 33 32

AVSS

AVCC

P4 .0 /TB0

P3.3/UCB0CLK/UCA0STE

P1 .5 /T A0 / T M S

P1 .6 /T A1 / T D I/T CLK

P4 .1 /TB1

P4 .2 /TB2

P1 .2 /T A1

P1 .3 /T A2

P1 .4 /SM CLK/TC K

P1.1/TA0

P1.0/TACLK /ADC 10CLK

P2 .4 / TA 2 /A4/VREF+/ VeREF+

P2 .3 / TA 1 /A3/VREF-- / V e R E F--

P3.7/A7

P3.6/A6

P3 .5 /UCA 0RXD/UCA0SOMI

P3 .4 /UCA 0TXD/UCA0SIMO

P4.7/TBCLK

P4.6/TBOUTH/A15

P4.3 /TB 0/A 1 2

P4.4 /TB 1/A 1 3

P4.5 /TB 2/A 1 4

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MSP430x22x4 device pinout, RHA package

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

XOUT /P2.7

XIN /P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK /A0/OA 0I0

P2 .1 /TAINCLK /SMCLK /A1/ OA 0O

P2 .2 /TA 0/A2 /OA 0I1

P3 .0 /UCB 0STE /UCA 0CLK /A5

P3 .1 /UCB 0SIMO /UCB 0SDA

P2.5/Rosc

1DVSS

12 14 15 16 17 18 19

P3.2/UCB0SOMI/UCB0SCL

TEST/SBWTCK

DVCC

P1.7/T A2/TD O /T D I

3839 37 36 35 34 33 32

AVSS

AVCC

P4 .0 /TB0

P3.3/UCB0CLK/UCA0STE

P1 .5 /T A0 / T M S

P1 .6 /T A1 / T D I/T CLK

P4 .1 /TB1

P4 .2 /TB2

P1 .2 /T A1

P1 .3 /T A2

P1 .4 /SM CLK/TC K

P1.1/TA0

P1.0/TACLK /ADC 10CLK

P2 .4/TA 2/A4 /VREF+/ VeREF+/ OA1I0

P2 .3/TA 1/A3 /VREF-- / V e R E F-- /OA 1 I1/OA1O

P3.7/A7/OA1I2

P3.6/A6/OA0I2

P3 .5 /UCA 0RXD /UCA 0 SOMI

P3 .4 /UCA 0TXD /UCA 0SIMO

P4.7/TBCLK

P4.6/TBOUTH/A15/OA 1I3

P4 .3 /T B0 / A12 /O A 0 O

P4 .4 /T B1 / A13 /O A 1 O

P4.5/TB2/A 14/OA0I3

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MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

MSP430x22x2 functional block diagram

VCC VSS

System+

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

JTAG

Interface

XOUT

MCLK

ACLK

SMCLK

MAB

MDB

Flash

32kB 16kB

8kB

Brownout

Protection

RST/NMI

XIN

Basic Clock

Spy--Bi Wire

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

VCC VSS

System+

16MHz

CPU

incl. 16

Registers

XOUT

MCLK

ACLK

SMCLK

MAB

MDB

Flash

32kB 16kB

8kB

XIN

Basic Clock

RAM

1kB 512B 512B

RAM

1kB 512B 512B

ADC10

1 0 --B i t

12 Channels, Autoscan,

DTC

Watchdog

WDT+

15/16--Bit

ADC10

1 0 --B i t

12 Channels, Autoscan,

DTC

Time r_A3

3CC

Registers

OA0, OA1

2OpAmps

P1.x/P2.x

2x8

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull--up/down

resistors

Time r_B3

3CC

Registers,

Shadow

Reg

P1.x/P2.x

2x8

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull--up/down

resistors

P3.x/P4.x

2x8

Ports P3/P4

2x8 I/O

pull--up/down

resistors

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

P3.x/P4.x

2x8

Ports P3/P4

2x8 I/O

pull--up/down

resistors

Emulation

(2BP)

JTAG

Interface

Spy--Bi Wire

Brownout

Protection

RST/NMI

Watchdog

WDT+

15/16--Bit

Time r_A3

3CC

Registers

Time r_B3

3CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

NOTE: See port schematics section for detailed I/O information.

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MSP430x22x2, MSP430x22x4

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Terminal Functions, MSP430x22x2

TERMINAL

NAME

P1.0/TACLK/ ADC10CLK

P1.1/TA0 32 30 I/O General-purpose digital I/O pin

P1.2/TA1 33 31 I/O General-purpose digital I/O pin

P1.3/TA2 34 32 I/O General-purpose digital I/O pin

P1.4/SMCLK/ TCK

P1.5/TA0/ TMS

P1.6/TA1/ TDI/TCLK

P1.7/TA2/ TDO/TDI

P2.0/ACLK/A0 8 6 I/O General-purpose digital I/O pin / ACLK output

P2.1/TAINCLK/SMCLK/A1 9 7 I/O General-purpose digital I/O pin

P2.2/TA0/A2 10 8 I/O General-purpose digital I/O pin

P2.3/TA1/ A3/V

P2.4/TA2/ A4/V

P2.5/ R

XIN/P2.6 6 3 I/O Input terminal of crystal oscillator

XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator

P3.0/ UCB0STE/UCA0CLK/ A5

P3.1/ UCB0SIMO/UCB0SDA

P3.2/ UCB0SOMI/UCB0SCL

P3.3/ UCB0CLK/UCA0STE

P3.4/ UCA0TXD/UCA0SIMO

†

REF--/VeREF--

REF+/VeREF+

OSC

DA RHA

NO. NO.

31 29 I/O General-purpose digital I/O pin

35 33 I/O General-purpose digital I/O pin / SMCLK signal output

36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output

37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output

38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output

29 27 I/O General-purpose digital I/O pin

30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output

3 40 I/O General-purpose digital I/O pin

11 9 I/O General-purpose digital I/O pin

12 10 I/O General-purpose digital I/O pin

13 11 I/O General-purpose digital I/O pin

14 12 I/O General-purpose digital I/O pin

25 23 I/O General-purpose digital I/O pin

I/O

Timer_A, clock signal TACLK input ADC10, conversion clock

Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit

Timer_A, capture: CCI1A input, compare: OUT1 output

Timer_A, capture: CCI2A input, compare: OUT2 output

Test Clock input for device programming and test

Test Mode Select input for device programming and test

Test Data Input or Test Clock Input for programming and test

Test Data Output or Test Data Input for programming and test

ADC10, analog input A0

Timer_A, clock signal at INCLK, SMCLK signal output ADC10, analog input A1

Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2

Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input

ADC10, analog input A4 / positive reference voltage output/input

Input for external DCO resistor to define DCO frequency

General-purpose digital I/O pin

USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5

USCI_B0 slave in/master out in SPI mode, SDA I

USCI_B0 slave out/master in in SPI mode, SCL I

USCI_B0 clock input/output / USCI_A0 slave transmit enable

USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode

DESCRIPTION

CdatainI2C mode

C clock in I2C mode

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MSP430x22x2, MSP430x22x4

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Terminal Functions, MSP430x22x2 (Continued)

TERMINAL

NAME

P3.5/ UCA0RXD/UCA0SOMI

P3.6/A6 27 25 I/O General-purpose digital I/O pin

P3.7/A7 28 26 I/O General-purpose digital I/O pin

P4.0/TB0 17 15 I/O General-purpose digital I/O pin

P4.1/TB1 18 16 I/O General-purpose digital I/O pin

P4.2/TB2 19 17 I/O General-purpose digital I/O pin

P4.3/TB0/ A12

P4.4/TB1 A13

P4.5/TB2 A14

P4.6/TBOUTH A15

P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin

RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input

TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is

QFN Pad NA Package

†

TDO or TDI is selected via JTAG instruction.

NOTE: IfXOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

DA RHA

NO. NO.

26 24 I/O General-purpose digital I/O pin

20 18 I/O General-purpose digital I/O pin

21 19 I/O General-purpose digital I/O pin

22 20 I/O General-purpose digital I/O pin

23 21 I/O General-purpose digital I/O pin

2 38, 39 Digital supply voltage

16 14 Analog supply voltage

4 1, 4 Digital ground reference

15 13 Analog ground reference

Pad

I/O

USCI_A0 receive data input in UART mode, slave out/master in in SPI mode

ADC10 analog input A6

ADC10 analog input A7

Timer_B, capture: CCI0A input, compare: OUT0 output

Timer_B, capture: CCI1A input, compare: OUT1 output

Timer_B, capture: CCI2A input, compare: OUT2 output

Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12

Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13

Timer_B, compare: OUT2 output ADC10 analog input A14

Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15

Timer_B, clock signal TBCLK input

Spy-Bi-Wire test data input/output during programming and test

connected to TEST. Spy-Bi-Wire test clock input during programming and test

NA QFN package pad; connection to DVSSrecommended.

DESCRIPTION

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MSP430x22x2, MSP430x22x4

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Terminal Functions, MSP430x22x4

TERMINAL

NAME

P1.0/TACLK/ ADC10CLK

P1.1/TA0 32 30 I/O General-purpose digital I/O pin

P1.2/TA1 33 31 I/O General-purpose digital I/O pin

P1.3/TA2 34 32 I/O General-purpose digital I/O pin

P1.4/SMCLK/ TCK

P1.5/TA0/ TMS

P1.6/TA1/ TDI/TCLK

P1.7/TA2/ TDO/TDI

P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output

P2.1/TAINCLK/SMCLK/ A1/OA0O

P2.2/TA0/ A2/OA0I1

P2.3/TA1/ A3/V /OA1I1/OA1O

P2.4/TA2/ A4/V /OA1I0

P2.5/ R

XIN/P2.6 6 3 I/O Input terminal of crystal oscillator

XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator

P3.0/ UCB0STE/UCA0CLK/ A5

P3.1/ UCB0SIMO/UCB0SDA

P3.2/ UCB01SOMI/UCB0SCL

P3.3/ UCB0CLK/UCA0STE

P3.4/ UCA0TXD/UCA0SIMO

†

REF--/VeREF--

REF+/VeREF+

OSC

DA RHA

NO. NO.

31 29 I/O General-purpose digital I/O pin

35 33 I/O General-purpose digital I/O pin / SMCLK signal output

36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output

37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output

38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output

9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK

10 8 I/O General-purpose digital I/O pin

29 27 I/O General-purpose digital I/O pin

30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output

3 40 I/O General-purpose digital I/O pin

11 9 I/O General-purpose digital I/O pin

12 10 I/O General-purpose digital I/O pin

13 11 I/O General-purpose digital I/O pin

14 12 I/O General-purpose digital I/O pin

25 23 I/O General-purpose digital I/O pin

I/O

Timer_A, clock signal TACLK input ADC10, conversion clock

Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit

Timer_A, capture: CCI1A input, compare: OUT1 output

Timer_A, capture: CCI2A input, compare: OUT2 output

Test Clock input for device programming and test

Test Mode Select input for device programming and test

Test Data Input or Test Clock Input for programming and test

Test Data Output or Test Data Input for programming and test

ADC10, analog input A0 / OA0, analog input I0

SMCLK signal output ADC10, analog input A1 / OA0, analog output

Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I1

Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output

ADC10, analog input A4 / positive reference voltage output/input OA1, analog input I0

Input for external DCO resistor to define DCO frequency

General-purpose digital I/O pin

USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5

USCI_B0 slave in/master out in SPI mode, SDA I

USCI_B0 slave out/master in in SPI mode, SCL I

USCI_B0 clock input/output / USCI_A0 slave transmit enable

USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode

DESCRIPTION

CdatainI2C mode

C clock in I2C mode

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Terminal Functions, MSP430x22x4 (Continued)

TERMINAL

NAME

P3.5/ UCA0RXD/UCA0SOMI

P3.6/A6/OA0I2 27 25 I/O General-purpose digital I/O pin

P3.7/A7/OA1I2 28 26 I/O General-purpose digital I/O pin

P4.0/TB0 17 15 I/O General-purpose digital I/O pin

P4.1/TB1 18 16 I/O General-purpose digital I/O pin

P4.2/TB2 19 17 I/O General-purpose digital I/O pin

P4.3/TB0/ A12/OA0O

P4.4/TB1 A13/OA1O

P4.5/TB2 A14/OA0I3

P4.6/TBOUTH A15/OA1I3

P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin

RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input

TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is

QFN Pad NA Package

†

TDO or TDI is selected via JTAG instruction.

NOTE: IfXOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

DA RHA

NO. NO.

26 24 I/O General-purpose digital I/O pin

20 18 I/O General-purpose digital I/O pin

21 19 I/O General-purpose digital I/O pin

22 20 I/O General-purpose digital I/O pin

23 21 I/O General-purpose digital I/O pin

2 38, 39 Digital supply voltage

16 14 Analog supply voltage

4 1, 4 Digital ground reference

15 13 Analog ground reference

Pad

I/O

USCI_A0 receive data input in UART mode, slave out/master in in SPI mode

ADC10 analog input A6 / OA0 analog input I2

ADC10 analog input A7 / OA1 analog input I2

Timer_B, capture: CCI0A input, compare: OUT0 output

Timer_B, capture: CCI1A input, compare: OUT1 output

Timer_B, capture: CCI2A input, compare: OUT2 output

Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 / OA0 analog output

Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 / OA1 analog output

Timer_B, compare: OUT2 output ADC10 analog input A14 / OA0 analog input I3

Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 / OA1 analog input I3

Timer_B, clock signal TBCLK input

Spy-Bi-Wire test data input/output during programming and test

connected to TEST. Spy-Bi-Wire test clock input during programming and test

NA QFN package pad connection to DVSSrecommended.

DESCRIPTION

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short-form description

CPU

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ----> (TOS), R8---- > PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)----> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) ----> M(TONI)

Absolute F F MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)

Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 ----> M(TONI)

NOTE: S = source D = destination

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 ----> R11

M(R10) -- --> R11 R10 + 2----> R10

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operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active

D Low-power mode 0 (LPM0)

-- CPU is disabled ACLK and SMCLK remain active MCLK is disabled

D Low-power mode 1 (LPM1)

-- CPU is disabled ACLK and SMCLK remain active MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode

D Low-power mode 2 (LPM2)

-- CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active

D Low-power mode 3 (LPM3)

-- CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active

D Low-power mode 4 (LPM4)

-- CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

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interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes into LPM4 immediately after power up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog

Flash key violation

PC out-of-range (see Note 1)

NMI

Oscillator fault

Flash memory access violation

Timer_B3 TBCCR0 CCIFG (see Note 3) maskable 0FFFAh 29

Timer_B3

Watchdog Timer WDTIFG maskable 0FFF4h 26

Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25

Timer_A3

USCI_A0/USCI_B0 Receive

USCI_A0/USCI_B0 Transmit

ADC10 ADC10IFG (see Note 3) maskable 0FFEAh 21

I/O Port P2

(eight flags)

I/O Port P1

(eight flags)

(see Note 5) 0FFDEh 15

(see Note 6) 0FFDCh ... 0FFC0h 14 ... 0, lowest

NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from

within unused address ranges.

2. Multiple source flags

3. Interrupt flags are located in the module.

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

5. This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied.

6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if necessary.

TAIFG (see Notes 2 and 3)

UCA0RXIFG, UCB0RXIFG

UCA0TXIFG, UCB0TXIFG

PORIFG RSTIFG WDTIFG

KEYV

(see Note 2)

NMIIFG

OFIFG

ACCVIFG

(see Notes 2 & 4)

TBCCR1 and TBCCR2

CCIFGs, TBIFG

(see Notes 2 and 3)

TACCR1 CCIFG.

TACCR2 CCIFG

(see Notes 2)

P2IFG.0toP2IFG.7 (see Notes 2 and 3)

P1IFG.0toP1IFG.7 (see Notes 2 and 3)

Reset 0FFFEh 31, highest

(non)-maskable, (non)-maskable,

(non)-maskable

maskable 0FFF8h 28

maskable 0FFF0h 24

maskable 0FFEEh 23

maskable 0FFECh 22

maskable 0FFE6h 19

maskable 0FFE4h 18

0FFFCh 30

0FFF6h 27

0FFE8h 20

0FFE2h 17

0FFE0h 16

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special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address76543210

00h

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw--0

WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured

OFIE Oscillator fault enable

NMIIE (Non)-maskable interrupt enable

ACCVIE Flash access violation i nterrupt enable

Address76543210

01h

UCA0RXIE USCI_A0 receive-interrupt enable

UCA0TXIE USCI_A0 transmit-interrupt enable

UCB0RXIE USCI_B0 receive-interrupt enable

UCB0TXIE USCI_B0 transmit-interrupt enable

in interval timer mode.

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw--0 rw--0 rw--0 rw--0

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interrupt flag register 1 and 2

Address76543210

02h

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw--0 rw--(0) rw--(1) rw--1 rw --(0)

WDTIFG Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

OFIFG Flag set on oscillator fault

RSTIFG External reset interrupt flag. Set on a reset condition at RST

PORIFG Power-On interrupt flag. Set on V

NMIIFG Set via RST

Address76543210

03h

UCA0RXIFG USCI_A0 receive-interrupt flag

UCA0TXIFG USCI_A0 transmit-interrupt flag

UCB0RXIFG USCI_B0 receive-interrupt flag

UCB0TXIFG USCI_B0 transmit-interrupt flag

Legend rw:

rw-0,1: rw-(0,1):

Reset on V

power up or a reset condition at RST/NMI pin in reset mode.

/NMI pin in reset mode. Reset on VCCpower up.

power up.

/NMI-pin

UCB0

TXIFG

rw--1 rw--0 rw--1 rw--0

Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

UCB0

RXIFG

UCA0

TXIFG

UCA0

RXIFG

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memory organization

MSP430F223x MSP430F225x MSP430F227x

Memory Main: interrupt vector Main: code memory

Information memory Size

Boot memory Size

RAM Size 512 Byte

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report, Features of the MSP430 Bootstrap Loader, TI literature number SLAA089.

Size Flash Flash

Flash

ROM

8-bit

8-bit SFR

8KB Flash

0FFFFh--0FFC0h

0FFFFh--0E000h

256 Byte

010FFh--01000h

1KB

0FFFh--0C00h

03FFh--0200h

01FFh--0100h

0FFh--010h

0Fh--00h

16KB Flash 0FFFFh--0FFC0h 0FFFFh--0C000h

256 Byte

010FFh--01000h

1KB

0FFFh--0C00h

512 Byte

03FFh--0200h

01FFh--0100h

0FFh--010h

0Fh--00h

32KB Flash

0FFFFh--0FFC0h

0FFFFh--08000h

256 Byte

010FFh--01000h

1KB

0FFFh--0C00h

1KB

05FFh--0200h

01FFh--0100h

0FFh--010h

0Fh--00h

BSL Function DA Package Pins RHA Package Pins

Data transmit 32 - P1.1 30 - P1.1

Data receive 10 - P2.2 8-P2.2

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0--n.

Segments A to D are also called information memory.

D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.

It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.

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MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

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peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very

low power LF oscillator.

D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

DCO Calibration Data (provided from factory in flash info memory segment A)

DCO Frequency Calibration Register Size Address

1MHz

8MHz

12 MHz

16 MHz

CALBC1_1MHZ byte

CALDCO_1MHZ byte

CALBC1_8MHZ byte

CALDCO_8MHZ byte

CALBC1_12MHZ byte

CALDCO_12MHZ byte

CALBC1_16MHZ byte

CALDCO_16MHZ byte

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of port P1 and P2. D Read/write access to port-control registers is supported by all instructions. D Each I/O has an individually programmable pullup/pulldown r esistor.

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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MSP430x22x2, MSP430x22x4

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timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer_A3 Signal Connections

Input

Pin Number

DA RHA DA RHA

31 - P1.0 29 - P1.0 TACLK TAC L K

9-P2.1 7-P2.1 TAINCLK INCLK

32 - P1.1 30 - P1.1 TA0 CCI0A

10 - P2.2 8-P2.2 TA 0 CCI0B

33 - P1.2 31 - P1.2 TA1 CCI1A

29 - P2.3 27 - P2.3 TA1 CCI1B

34 - P1.3 32 - P1.3 TA2 CCI2A

Device

Input Signal

ACLK ACLK

SMCLK SMCLK

ACLK (internal) CCI2B

Module

Input Name

GND

Module

Block

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

Module

Output Signal

Output

Pin Number

32 - P1.1 30 - P1.1

10 - P2.2 8-P2.2

36 - P1.5 34 - P1.5

33 - P1.2 31 - P1.2

29 - P2.3 27 - P2.3

37 - P1.6 35 - P1.6

34 - P1.3 32 - P1.3

30 - P2.4 28 - P2.4

38 - P1.7 36 - P1.7

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timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer_B3 Signal Connections

Input

Pin Number

DA RHA DA RHA

24 - P4.7 22 - P4.7 TBCLK TBCLK

24 - P4.7 22 - P4.7 TBCLK INCLK

17 - P4.0 15 - P4.0 TB0 CCI0A

20 - P4.3 18 - P4.3 TB0 CCI0B

18 - P4.1 16 - P4.1 TB1 CCI1A

21 - P4.4 19 - P4.4 TB1 CCI1B

19 - P4.2 17 - P4.2 TB2 CCI2A

Device

Input Signal

ACLK ACLK

SMCLK SMCLK

ACLK (internal) CCI2B

Module

Input Name

GND

Module

Block

Timer N

CCR0 TB0

CCR1 TB1

CCR2 TB2

Module

Output Signal

Output

Pin Number

17 - P4.0 15 - P4.0

20 - P4.3 18 - P4.3

18 - P4.1 16 - P4.1

21 - P4.4 19 - P4.4

19 - P4.2 17 - P4.2

22 - P4.5 20 - P4.5

universal serial communications interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I

C and asynchronous communication protocols such as UART,

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MSP430x22x2, MSP430x22x4

DeviceInputSignalModuleInputNam

MIXED SIGNAL MICROCONTROLLER

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ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention.

operational amplifier OA (MSP430x22x4 only)

The MSP430x22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

OA0 Signal Connections

Analog Input

Pin Number

DA RHA

8-A0 6-A0 OA0I0 OAxI0

10 - A2 8-A2 OA0I1 OA0I1

10 - A2 8-A2 OA0I1 OAxI1

27 - A6 25 - A6 OA0I2 OAxIA

22 - A14 20 - A14 OA0I3 OAxIB

Device Input Signal Module Input Name

OA1 Signal Connections

Analog Input

Pin Number

DA RHA

30 - A4 28 - A4 OA1I0 OAxI0

10 - A2 8-A2 OA0I1 OA0I1

29 - A3 27 - A3 OA1I1 OAxI1

28 - A7 26 - A7 OA1I2 OAxIA

23 - A15 21 - A15 OA1I3 OAxIB

Device Input Signal Module Input Name

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peripheral file map

ADCcontrolregister0

ADC10CTL0

1B0

ADC10 ADC data transfer start address

Timer_B Capture/compare register

Timer_A Capture/compare register

Flash Memory Flash control 3

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

OA1 (MSP430x22x4 only) Operational Amplifier 1 control register 1

OA0 (MSP430x22x4 only) Operational Amplifier 0 control register 1

USCI_B0 USCI_B0 transmit buffer

USCI_A0 USCI_A0 transmit buffer

PERIPHERALS WITH WORD ACCESS

ADC memory ADC control register 1 ADC control register 0 ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0

Capture/compare register Capture/compare register Timer_B register Capture/compare control Capture/compare control Capture/compare control Timer_B control Timer_B interrupt vector

Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector

Flash control 2 Flash control 1

PERIPHERALS WITH BYTE ACCESS

Operational Amplifier 1 control register 1

Operational Amplifier 0 control register 1

USCI_B0 receive buffer USCI_B0 status USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address

USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0

TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV

TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TAC T L TAI V

FCTL3 FCTL2 FCTL1

OA1CTL1 OA1CTL0

OA0CTL1 OA0CTL0

UCB0TXBUF UCB0RXBUF UCB0STAT UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA

UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL

1BCh 1B4h 1B2h 1B0h 04Ah 04Bh 049h 048h

0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh

0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh

012Ch 012Ah 0128h

0C3h 0C2h

0C1h 0C0h

06Fh 06Eh 06Dh 06Bh 06Ah 069h 068h 011Ah 0118h

067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh

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PERIPHERALS WITH BYTE ACCESS (continued)

Basic Clock System+ Basic clock system control 3

Basic clock system control 2 Basic clock system control 1 DCO clock frequency control

Port P4 Port P4 resistor enable

Port P4 selection Port P4 direction Port P4 output Port P4 input

Port P3 Port P3 resistor enable

Port P3 selection Port P3 direction Port P3 output Port P3 input

Port P2 Port P2 resistor enable

Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input

Port P1 Port P1 resistor enable

Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input

Special Function SFR interrupt flag 2

SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1

BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL

P4REN P4SEL P4DIR P4OUT P4IN

P3REN P3SEL P3DIR P3OUT P3IN

P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN

P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN

IFG2 IFG1 IE2 IE1

053h 058h 057h 056h

011h 01Fh 01Eh 01Dh 01Ch

010h 01Bh 01Ah 019h 018h

02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h

027h 026h 025h 024h 023h 022h 021h 020h

003h 002h 001h 000h

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absolute maximum ratings (see Note 1)

Voltage applied at VCCto V

Voltage applied to any pin (see Note 2) --0.3 V to V

Diode current at any device terminal ±2mA.......................................................

Storage temperature range, T Storage temperature range, T

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Expos ure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. All voltages referenced to V is applied to the TEST pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

(unprogrammed device, see Note 3) --55°C to 150°C..................

stg

(programmed device, see Note 3) --40°C to 105°C....................

stg

. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage during program execution, V

Supply voltage during program/erase flash memory, V

Supply voltage, V

Operatingfree-air temperature, T

Processor frequency f (see Notes 1, 2 and Figure 1)

NOTES: 1. The MSP430 CPU is clocked directly with MCLK.

(maximum MCLK frequency)

SYSTEM

Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.

2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

I version -- 4 0 85

T version -- 4 0 105

VCC=1.8V, Duty cycle = 50% ±10%

VCC=2.7V, Duty cycle = 50% ±10%

VCC≥ 3.3 V, Duty cycle = 50% ±10%

1.8 3.6 V

2.2 3.6 V

dc 4.15

dc 12

dc 16

--0.3 V to 4.1 V......................................................

+0.3 V........................................

0 V

MHz

°C

16 MHz

12 MHz

7.5 MHz

System Frequency -- MHz

4.15 MHz

1.8 V 2.2 V 2.7 V 3.3 V 3.6 V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCCof 2.2 V.

Supply Voltage -- V

Legend:

Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Figure 1. Operating Area

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

(

AM)

Activemode(AM

)

(

AM)

Activemode(AM

)

(

AM)

CLK

=32,768Hz/8=4,096Hz

Activemode(AM

)

Programexecutesinflas

ADIVMxDIVSxDIVAx11,

(

AM)

Activemode(AM

)

Programexecutesinflas

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

active mode supply current (into DVCC+AVCC) excluding external current (see Notes 1 and 2)

AM, 1MHz

AM, 4kHz

AM,100kHz

PARAMETER TEST CONDITIONS T

ctive mode

current (1 MHz)

DCO=fMCLK=fSMCLK

= 32,768 Hz,

ACLK

Program executes in flash, BCSCTL1 = C DCOCTL = CALDCO_1MHZ,

=1MHz,

LBC1_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

ctive mode

current (1 MHz)

DCO=fMCLK=fSMCLK

= 32,768 Hz,

ACLK

Program executes in RAM, BCSCTL1 = C DCOCTL = CALDCO_1MHZ,

=1MHz,

LBC1_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

ctive mode

current (4 kHz)

ctive mode

current (100 kHz)

MCLK=fSMCLK

=32,768 Hz/8=4,096 Hz

=0Hz,

DCO

Pro

ram executes inflash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0

MCLK=fSMCLK=fDCO(0, 0)

=0Hz,

ACLK

Program executes in RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1

-40--85°C 2.2 V 5 9

105°C 2.2 V 18

-40--85°C 3V 6 10

105°C 3V 20

lash,

≈ 100 kHz,

-40--85°C 2.2 V 60 85

105°C 2.2 V 95

-40--85°C 3V 72 95

105°C 3V 105

VCC MIN TYP MAX UNIT

2.2 V 270 390

3V 390 550

2.2 V 240

3V 340

NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.

2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

typical characteristics -- active mode supply current (into DVCC+AVCC)

8.0

=16MHz

7.0

6.0

5.0

4.0

3.0

Active Mode Current -- mA

2.0

1.0

0.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC-- Supply Voltage -- V

DCO

=12MHz

=8MHz

=1MHz

Figure 2. Active Mode Current vs VCC,TA=25°C

5.0

TA=85°C

4.0

3.0

VCC=3V

2.0

Active Mode Current -- mA

1.0

VCC=2.2V

0.0

0.0 4.0 8.0 12.0 16.0

-- DCO Frequency -- MHz

DCO

TA=85°C

TA=25°C

Figure 3. Active Mode Current vs DCO Frequency

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

CLK

ACL

=0H

1MH

(

0MH

3(LPM3)curren

ACL

=32,768Hz

(

)

0MH

(

VLO)

3curren

t,(LPM3

)

ACL

frominternalLFoscillator(VLO)

0MH

ACL

=0H

/3V

AseeNote5

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

low power mode supply currents (into DVCC+AVCC) excluding external current (see Notes 1 and 2)

LPM0, 1MHz

LPM0, 100kHz

LPM2

LPM3,LFXT1

LPM3,VLO

LPM4

PARAMETER TEST CONDITIONS T

=0MHz,

MCLK

Low-power mode 0 (LPM0) current, seeNote3

SMCLK=fDCO

= 32,768 Hz,

ACLK

BCSCTL1 = C DCOCTL = CALDCO_1MHZ,

=1MHz,

LBC1_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

=0MHz,

MCLK

Low-power mode 0 (LPM0) current, seeNote3

SMCLK=fDCO(0, 0)

=0Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0,

≈ 100 kHz,

OSCOFF = 1

Low-power mode 2 (LPM2) current, seeNote4

MCLK=fSMCLK

DCO

= 32,768 Hz,

ACLK

BCSCTL1 = C DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

=0MHz,

LBC1_1MHZ,

-40--85°C

105°C

-40--85°C

105°C

-40°C 0.7 1.4

25°C

ow-power mode

LPM3)current,

seeNote4

DCO

MCLK

= 32,768 Hz,

SMCLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0

85°C

105°C 5 10

-40°C 0.9 1.5

25°C

85°C

105°C 6 12

-40°C 0.4 1.0

25°C

ow-power mode

3 current,

LPM3

seeNote4

DCO

MCLK

SMCLK

rom internal LF oscillator CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0

85°C

105°C 4.5 9

-40°C 0.5 1.2

25°C

85°C

105°C 5.5 11

-40°C 0.1 0.5

25°C

85°C

105°C 4.5 9

Low-power mode 4 (LPM4) current, seeNote5

DCO

MCLK

=0Hz,

SMCLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1

VCC MIN TYP MAX UNIT

2.2 V 75 90

3V 90 120

2.2 V 37 48

3V 41 65

22 29

2.2 31

25 32

2.2

0.7 1.4

2.4 3.3

0.9 1.5

2.6 3.8

0.5 1.0

1.8 2.9

0.6 1.2

2.1 3.3

0.1 0.5

1.5 3.0

NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.

2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

3. Current for brownout and WDT clocked by SMCLK included.

4. Current for brownout and WDT clocked by ACLK included.

5. Current for brownout included.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

IT+

Positivegoinginputthresholdvoltag

Negativegoinginputthresholdvoltag

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs -- Ports P1, P2, P3, P4, and RST/NMI

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IT+

IT--

hys

Pull

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

Pullup/pulldown resistor

IT+

-- V

IT--

)

For pullup: VIN=VSS; For pulldown: V

Input capacitance VIN=VSSor V

IN=VCC

inputs -- Ports P1 and P2

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Port P1, P2: P1.x to P2.x, External

(int)

External interrupt timing

NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t

shorter than t

(int)

trigger pulse width to set interrupt flag (see Note 1)

0.45 0.75 V

2.2 V 1.00 1.65

3V 1.35 2.25

0.25 0.55 V

2.2 V 0.55 1.20

3V 0.75 1.65

2.2 V 0.2 1.0

3V 0.3 1.0

20 35 50 kΩ

5 pF

2.2 V/3 V 20 ns

is met. It may be set even with trigger signals

(int)

leakage current -- Ports P1, P2, P3 and P4

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

lkg(Px.x)

NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.

High-impedance leakage current See Notes 1 and 2 2.2 V/3 V ±50 nA

2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

Portoutputfrequency

VCC/

2.0/ACL

K,P

1.4/SMCLK,CL=20pF

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

outputs -- Ports P1, P2, P3 and P4

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

High-level output voltage

Low-level output voltage

NOTES: 1. The maximum total current, I

voltage drop specified.

2. The maximum total current, I voltage drop specified.

OHmax

= --1.5 mA (see Note 1) 2.2 V VCC--0.25 V

(OHmax)

= --6 mA (see Note 2) 2.2 V VCC-- 0 . 6 V

(OHmax)

= --1.5 mA (see Note 1) 3V VCC--0.25 V

(OHmax)

= --6 mA (see Note 2) 3V VCC-- 0 . 6 V

(OHmax)

= 1.5 mA (see Note 1) 2.2 V V

(OLmax)

= 6 mA (see Note 2) 2.2 V V

(OLmax)

= 1.5 mA (see Note 1) 3V V

(OLmax)

= 6 mA (see Note 2) 3V V

(OLmax)

and I

, for all outputs combined, should not exceed ±12 mA to hold the maximum

OLmax

, for all outputs combined, should not exceed ±48 mA to hold the maximum

OLmax

VSS+0.25

VSS+0.6

VSS+0.25

VSS+0.6

output frequency -- Ports P1, P2, P3 and P4

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

P1.4/SMCLK,

=20pF,RL=1kΩ against

(see Notes 1 and 2)

P2.0

CLK, P1.4/SMCLK, C

(see Note 2)

=20pF

Px.y

Port_CLK

Port outputfrequenc (with load)

Clock outputfrequency

NOTES: 1. Alternatively a resistive divider with 2 times 2 kΩ between VCCand VSSis used as load. The output is connected to the center tap

of the divider.

2. The output voltage reaches at least 10% and 90% V

at the specified toggle frequency.

2.2 V 10

3V 12

2.2 V 12

3V 16

MHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

typical characteristics -- outputs

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

25.0

VCC=2.2V P4.5

20.0

15.0

10.0

5.0

I -- Typical Low-Level Output Current -- m

0.0

0.0 0.5 1.0 1.5 2.0 2.5

VOL-- Low-Level Output Voltage -- V

TA=25°C

TA=85°C

Figure 4

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

50.0

VCC=3V P4.5

40.0

30.0

20.0

10.0

I -- Typical Low-Level Output Current -- mA

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOL-- Low-Level Output Voltage -- V

Figure 5

TA=25°C

TA=85°C

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0 VCC=2.2V P4.5

-- 5 . 0

--10.0

--15.0

I -- Typical High-Level Output Current -- m

--20.0

--25.0

TA=85°C

0.0 0.5 1.0 1.5 2.0 2.5

VOH-- High-Level Output Voltage -- V

Figure 6

NOTE: One output loaded at a time

TA=25°C

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0 VCC=3V P4.5

--10.0

--20.0

--30.0

TA=85°C

TA=25°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOH-- High-Level Output Voltage -- V

I -- Typical High-Level Output Current -- mA

--40.0

--50.0

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

POR/brownout reset (BOR) (see Notes 1 and 2)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

CC(start)

(B_IT--)

hys(B_IT--)

d(BOR)

(reset)

NOTES: 1. The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level

SeeFigure8 dVCC/dt ≤ 3V/s 0.7 × V

(B_IT--)

See Figure 8 through Figure 10 dVCC/dt ≤ 3V/s 1.71 V

SeeFigure8 dVCC/dt ≤ 3V/s 70 130 210 mV

SeeFigure8 2000 μs

Pulse length needed at RST/NMI pin

to accepted reset internally

(B_IT--)+Vhys(B_IT--)

is ≤ 1.8V.

2. During power up, the CPU begins code execution following a period of t DCO settings must not be changed until V

≥ V

CC(min)

, where V

CC(min)

d(BOR)

is the minimum supply voltage for the desired

2.2 V/3 V 2 μs

after VCC=V

(B_IT--)+Vhys(B_IT--)

operating frequency.

. The default

CC(start)

(B_IT--)

hys(B_IT--)

d(BOR)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

typical characteristics -- POR/brownout reset (BOR)

1.5

-- V

=3V

Typical Conditions

CC(drop)

0.5

0.001 1 1000

tpw-- Pulse Width -- μs

Figure 9. V

Typical Conditions

1.5

-- V

CC(drop)

0.5

0.001 1 1000

Figure 10. V

CC(drop)

=3V

CC(drop)

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

-- Pulse Width -- μs

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

CC(drop)

1ns 1ns

tpw-- Pulse Width -- μs

tf=t

tpw-- Pulse Width -- μs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

VccSupplyvoltagerange

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

main DCO characteristics

D All r anges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

D DCO control bits DCOx have a step size as defined by parameter S D Modulation control bits MODx select how often f

cycles. The frequency f to:

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal

DCO(RSEL,DCO+1)

is used within the period of 32 DCOCLK

DCO

avera ge

 ×

 × 

×



+−    × 

+



+

DCO frequency

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

RSELx < 14 1.8 3.6

Vcc Supply voltage range

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

RSEL

DCO

Duty Cycle Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 %

DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz

DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V/3 V 0.07 0.17 MHz

DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V/3 V 0.10 0.20 MHz

DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz

DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V/3 V 0.20 0.40 MHz

DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.28 0.54 MHz

DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V/3 V 0.39 0.77 MHz

DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V/3 V 0.54 1.06 MHz

DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V/3 V 0.80 1.50 MHz

DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V/3 V 1.10 2.10 MHz

DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V/3 V 1.60 3.00 MHz

DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V/3 V 2.50 4.30 MHz

DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V/3 V 3.00 5.50 MHz

DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V/3 V 4.30 7.30 MHz

DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V/3 V 6.00 9.60 MHz

DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V/3 V 8.60 13.9 MHz

DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz

DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz

Frequency step between range RSEL and RSEL+1

Frequency step between tap DCO and DCO+1

RSELx = 14

RSELx = 15 3.0 3.6

RSEL=fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

DCO=fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

2.2 V/3 V 1.55 ratio

2.2 V/3 V 1.05 1.08 1.12 ratio

2.2 3.6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

)

BCSCTL1=CALBC1_1MHZ

CAL(1MHz)

1MHzcalibrationvalueDCOCTLCALDCO_1MHZ

085

MHz

)

BCSCTL1=CALBC1_8MHZ

CAL(8MHz)

8MHzcalibrationvalueDCOCTLCALDCO_8MHZ

085

MHz

)

BCSCTL1=CALBC1_12MH

CAL(12MHz

)

12MHzcalibrationvalueDCOCTLCALDCO_12MHZ

085

MHz

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

calibrated DCO frequencies -- tolerance at calibration

PARAMETER TEST CONDITIONS T

Frequency tolerance at calibration 25°C 3V -- 1 ±0.2 +1 %

BCSCTL1= CALBC1_1MHZ,

CAL(1MHz)

1-MHz calibration value

DCOCTL = CALDCO_1MHZ,

25°C 3V 0.990 1 1.010 MHz

Gating time: 5 ms

BCSCTL1= CALBC1_8MHZ,

CAL(8MHz)

8-MHz calibration value

DCOCTL = CALDCO_8MHZ,

25°C 3V 7.920 8 8.080 MHz

Gating time: 5 ms

BCSCTL1= CALBC1_12MHZ,

CAL(12MHz)

12-MHz calibration value

DCOCTL = CALDCO_12MHZ,

25°C 3V 11. 88 12 12.12 MHz

Gating time: 5 ms

BCSCTL1= CALBC1_16MHZ,

CAL(16MHz)

16-MHz calibration value

DCOCTL = CALDCO_16MHZ,

25°C 3V 15.84 16 16.16 MHz

Gating time: 2 ms

calibrated DCO frequencies -- tolerance over temperature 0°Cto+85°C

PARAMETER TEST CONDITIONS T

1-MHz tolerance over temperature 0--85°C 3.0 V -- 2 . 5 ±0.5 +2.5 %

8-MHz tolerance over temperature 0--85°C 3.0 V -- 2 . 5 ±1.0 +2.5 %

12-MHz tolerance over temperature 0--85°C 3.0 V -- 2 . 5 ±1.0 +2.5 %

16-MHz tolerance over temperature 0--85°C 3.0 V -- 3 . 0 ±2.0 +3.0 %

CAL(1MHz

CAL(8MHz

CAL(12MHz

1-MHz calibration value

8-MHz calibration value

12-MHz calibration value

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

= DCOCTL = CALDCO_8MHZ, Gating time: 5 ms

= DCOCTL = CALDCO_12MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_16MHZ,

CAL(16MHz)

16-MHz calibration value

DCOCTL = CALDCO_16MHZ, Gating time: 2 ms

0--85°C

VCC MIN TYP MAX UNIT

2.2 V 0.970 1 1.030

3.0 V 0.975 1 1.025

MHz

3.6 V 0.970 1 1.030

2.2 V 7.760 8 8.400

3.0 V 7.800 8 8.200

MHz

3.6 V 7.600 8 8.240

2.2 V 11. 70 12 12.30

3.0 V 11. 70 12 12.30

MHz

3.6 V 11. 70 12 12.30

3.0 V 15.52 16 16.48

3.6 V 15.00 16 16.48

MHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

calibrated DCO frequencies -- tolerance over supply voltage V

PARAMETER

1-MHz tolerance over V

8-MHz tolerance over V

12-MHz tolerance over V

16 -Hz tolerance over V

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

1-MHz calibration value

8-MHz calibration value

12-MHz calibration value

16-MHz calibration value

TEST CONDITIONS T

BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms

calibrated DCO frequencies -- overall tolerance

PARAMETER TEST CONDITIONS T

1-MHz tolerance overall

8-MHz tolerance overall

12-MHz tolerance overall

16-MHz tolerance overall

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

1-MHz calibration value

8-MHz calibration value

12-MHz calibration value

16-MHz calibration value

BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms

BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

I: -40--85°C

T: -40--105°C

VCC MIN TYP MAX UNIT

25°C 1.8 V -- 3.6 V -- 3 ±2 +3 %

25°C 2.2 V -- 3.6 V -- 3 ±2 +3 %

25°C 3.0 V -- 3.6 V -- 6 ±2 +3 %

25°C 1.8 V -- 3.6 V 0.970 1 1.030 MHz

25°C 1.8 V -- 3.6 V 7.760 8 8.240 MHz

25°C 2.2 V -- 3.6 V 11. 64 12 12.36 MHz

25°C 3.0 V -- 3.6 V 15.00 16 16.48 MHz

VCC MIN TYP MAX UNIT

1.8 V to 3.6 V -- 5 ±2 +5 %

2.2 V to 3.6 V -- 5 ±2 +5 %

3.0 V to 3.6 V -- 6 ±3 +6 %

1.8 V to 3.6 V 0.950 1 1.050 MHz

1.8 V to 3.6 V 7.600 8 8.400 MHz

2.2 V to 3.6 V 11 . 40 12 12.60 MHz

3.0 V to 3.6 V 15.00 16 17.00 MHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

typical characteristics -- calibrated 1-MHz DCO frequency

1.03

1.02

VCC=1.8V

1.01

VCC=2.2V

1.00

0.99

Frequency -- MHz

VCC=3.6V

0.98

0.97

--50.0 --25.0 0.0 25.0 50.0 75.0 100.0

TA-- Temperature -- °C

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

VCC=3.0V

Figure 11. Calibrated 1-MHz Frequency vs Temperature

1.03

1.02

1.01

1.00

Frequency -- MHz

0.99

0.98

0.97

1.5 2.0 2.5 3.0 3.5 4.0

-- Supply Voltage -- V

Figure 12. Calibrated 1-MHz Frequency vs V

TA= 105 °C

TA=85°C

TA=25°C

TA=--40°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

DCOclockwakeuptimefromLPM3/

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

wake-up from lower power modes (LPM3/4)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ

BCSCTL1= CALBC1_8MHZ,

DCO,LPM3/4

CPU,LPM3/4

NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge

DCO clock wake-uptimefrom LPM3/4 (see Note 1)

CPU wake-up time from LPM3/4 (see Note 2)

observable externally on a clock pin (MCLK or SMCLK).

2. Parameter applicable only if DCOCLK is used for MCLK.

DCOCTL = CALDCO_8MHZ

BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ

BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ

2.2 V/3 V 2

2.2 V/3 V 1.5

2.2 V/3 V 1

3V 1

1/f

MCLK

Clock,LPM3/4

μs

typical characteristics -- DCO clock wake-up time from LPM3/4

10.00

RSELx = 0...11

1.00

DCO Wake-Up Time -- μs

0.10

0.10 1.00 10.00

DCO Frequency -- MHz

Figure 13. Clock Wake-Up Time From LPM3 vs DCO Frequency

RSELx = 12...15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

DCOoutputfrequenc

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

DCO with external resistor R

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

DCO,ROSC

NOTES: 1. R

DCO outputfrequenc with R

OSC

Temperature drift

Drift with V

OSC

= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK= ±50ppm/°C.

(see Note 1)

OSC

DCOR = 1, RSELx = 4, DCOx=3,MODx=0, T

=25°C

DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0

typical characteristics -- DCO with external resistor R

10.00

1.00

0.10

DCO Frequency -- MHz

RSELx = 4

OSC

DCO Frequency -- MHz

10.00

1.00

0.10

2.2 V 1.8

3V 1.95

2.2 V/3 V ±0.1 %/°C

2.2 V/3 V 10 %/V

RSELx = 4

MHz

0.01

10.00 100.00 1000.00 10000.00

-- External Resistor -- kΩ

OSC

Figure 14. DCO Frequency vs R

=2.2V,TA=25°C

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

DCO Frequency -- MHz

0.25

0.00

--50.0 --25.0 0.0 25.0 50.0 75.0 100.0

TA-- Temperature -- °C

OSC

= 100k

OSC

= 270k

OSC

=1M

OSC

Figure 16. DCO Frequency vs Temperature,

=3.0V

0.01

10.00 100.00 1000.00 10000.00

-- External Resistor -- kΩ

OSC

DCO Frequency -- MHz

Figure 15. DCO Frequency vs R

=3.0V,TA=25°C

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

2.0 2.5 3.0 3.5 4.0

VCC-- Supply Voltage -- V

OSC

= 100k

= 270k

=1M

Figure 17. DCO Frequency vs VCC,

=25°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

OscillationallowanceforLF

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1, low frequency modes (see Note 4)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

LFXT1,LF

LFXT1,LF,logic

L,eff

Duty Cycle LF mode

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).

LFXT1 oscillator crystal frequency, LF mode 0, 1

LFXT1 oscillator l ogic level square wave input frequency, LF mode

Oscillation allowancefor LF crystals

Integrated effective l oad capacitance, LF mode

Oscillator fault frequency, LF mode (see Note 3)

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

XTS = 0, LFXT1Sx = 0 or 1 1.8 V -- 3.6 V 32,768 Hz

XTS = 0, LFXT1Sx = 3 1.8 V -- 3.6 V 10,000 32,768 50,000 Hz

XTS = 0, LFXT1Sx = 0; f

LFXT1,LF

XTS = 0, LFXT1Sx = 0; f

LFXT1,LF

XTS = 0, XCAPx = 0 1

XTS = 0, XCAPx = 1 5.5

XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 11

XTS = 0, Measured at P1.4/ACLK, f

LFXT1,LF

XTS = 0, LFXT1Sx = 3 (see Note 2)

L,eff

= 32,768 kHz,

=6pF

= 32,768 kHz,

=12pF

= 32,768 Hz

500

kΩ

200

2.2 V/3 V 30 50 70 %

2.2 V/3 V 10 10,000 Hz

-- Keep as short a trace as possible between the device and the crystal.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

internal very low power, low frequency oscillator (VLO)

PARAMETER TEST CONDITIONS T

VLO

/dT

VLO

/dV

VLO

NOTES: 1. Calculated using the box method:

VLOfrequency

VLO frequency temperature drift

VLO frequency supply

voltage drift

I version: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85_C--(--40_C)) T version: (MAX(--40...105_C) -- MIN(--40...105_C))/MIN(--40...105_C)/(105_C--(--40_C))

2. Calculated using the box method: (MAX(1.8...3.6 V) -- MIN(1.8...3.6 V))/MIN(1.8...3.6V)/(3.6 V -- 1.8 V)

(see Note 1)

(see Note 2) 25°C 1.8V -- 3.6V 4 %/V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-40--85°C 2.2 V/3 V 4 12 20

105°C 2.2 V /3 V 22

I: -40--85°C

T: -40--105°C

VCC MIN TYP MAX UNIT

kHz

2.2 V/3 V 0.5 %/°C

MSP430x22x2, MSP430x22x4

LFXT1,HF2

Fmode2XTS1,LFXT1Sx

MHz

LFXT1oscillatorlogiclevel

LFXT1,H

F,logic

squarewaveinputfrequency,

XTS1,LFXT1Sx3

MHz

(

8andFi

19)

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1, high frequency modes (see Note 5)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

LFXT1,HF0

LFXT1,HF1

LFXT1,HF2

LFXT1,HF,logic

L,eff

Duty Cycle HF mode

Fault,HF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

LFXT1 oscillator crystal frequency, HF mode 0

LFXT1 oscillator crystal frequency, HF mode 1

LFXT1 oscillator crystal frequency,

square-wave input frequency, HF mode

Oscillation allowance for HF crystals

see

gure

Integrated effective l oad capacitance, HF mode (see Note 1)

Oscillator fault frequency, HF mode (see Note 4)

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

3. Measured with logic level input frequency but also applies to operation with crystals.

4. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

gure

XTS = 1, LFXT1Sx = 0 1.8 V -- 3.6 V 0.4 1 MHz

XTS = 1, LFXT1Sx = 1 1.8 V -- 3.6 V 1 4 MHz

1.8 V -- 3.6 V 2 10

XTS = 1, LFXT1Sx = 2

XTS = 1, LFXT1Sx = 3

XTS = 0, LFXT1Sx = 0, f

LFXT1,HF

XTS = 0, LFXT1Sx = 1 f

LFXT1,HF

XTS = 0, LFXT1Sx = 2 f

LFXT1,HF

XTS=1(seeNote2) 1 pF

XTS = 1, Measured at P1.4/ACLK, f

LFXT1,HF

XTS = 1, Measured at P1.4/ACLK, f

LFXT1,HF

XTS = 1, LFXT1Sx = 3 (see Notes 3)

=1MHz,C

=4MHz,C

=16MHz,C

=10MHz

=16MHz

L,eff

=15pF

2.2 V -- 3.6 V 2 12

3.0 V -- 3.6 V 2 16

1.8 V -- 3.6 V 0.4 10

2.2 V -- 3.6 V 0.4 12

3.0 V -- 3.6 V 0.4 16

2700

800

300

2.2 V/3 V 40 50 60

2.2 V/3 V 30 300 kHz

MHz

-- Keep as short a trace as possible between the device and the crystal.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1)

100000.00

10000.00

1000.00

LFXT1Sx = 3

100.00

Oscillation Allowance -- Ohms

LFXT1Sx = 1

LFXT1Sx = 2

10.00

0.10 1.00 10.00 100.00

Crystal Frequency -- MHz

Figure 18. Oscillation Allowance vs Crystal Frequency, C

800.0

LFXT1Sx = 3

XT Oscillator Supply Current -- uA

700.0

600.0

500.0

400.0

300.0

200.0

100.0

0.0

0.0 4.0 8.0 12.0 16.0 20.0

LFXT1Sx = 2

LFXT1Sx = 1

Crystal Frequency -- MHz

=15pF,TA=25°C

L,eff

Figure 19. XT Oscillator Supply Current vs Crystal Frequency, C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=15pF,TA=25°C

L,eff

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

Timer_A

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

TA, cap

Timer_B

TB,cap

Timer

Timer_A, capture timing TA 0, TA1 , TA2 2.2 V/3 V 20 ns

Timer_Bclockfrequency

Timer_B, capture timing TB0, TB1, TB2 2.2 V/3 V 20 ns

clockfrequency

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK, E

ternal: TACLK, INCLK,

Duty cycle = 50% ±10%

Internal: SMCLK, ACLK, E

ternal: TBCLK,

Duty cycle = 50% ±10%

2.2 V 10 MHz

3V 16

2.2 V 10 MHz

3V 16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

UARTreceivedeglitchtime

UCLKedgetoSIMOvalid

UCLKedgetoSOMIvalid

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (UART Mode)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

USCI

BITCLK

USCI input clock frequency

BITCLK clock frequency (equals baud rate in MBaud)

UART receive deglitch time (see Note 1)

NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode, see Figure 20 and Figure 21)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

USCI

SU,MI

HD,MI

VAL ID, MO

NOTE: f

For the slave’s parameters t

USCI input clock frequency

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time

UCxCLK

LO∕HI

with t

LO∕HI

SU,SI(Slave)

≥ max(t

VALID,MO(USCI)

External: UCLK Duty cycle = 50% ± 10%

SMCLK, ACLK Duty cycle = 50% ± 10%

UCLK edgetoSIMOvalid, C

=20pF

+ t

and t

VALID,SO(Slave)

2.2V /3 V 1 MHz

2.2 V 50 150 600 ns

3V 50 100 600 ns

2.2 V 110

3V 75

2.2 V 0

3V 0

2.2 V 30

3V 20

SU,SI(Slave),tSU,MI(USCI)

+ t

VALID,SO(Slave)

, see the SPI parameters of the attached slave.

SYSTEM

MHz

USCI (SPI Slave Mode, see Figure 22 and Figure 23)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VAL ID, SO

NOTE: f

For the master’s parameters t

STE lead time STE low to clock

STE lag time Last clock to STE high

STE access time STE low to SOMI data out

STE disable time STE high to SOMI high impedance

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time

UCxCLK

LO∕HI

with t

LO∕HI

≥ max(t

SU,MI(Master)

VALID,MO(Master)

UCLK edgetoSOMIvalid, C

=20pF

+ t

SU,SI(USCI),tSU,MI(Master)

and t

VALID,MO(Master)

2.2 V/3 V 50 ns

2.2 V/3 V 10 ns

2.2 V/3 V 50 ns

2.2 V 20

3V 15

2.2 V 10

3V 10

2.2 V 75 11 0

3V 50 75

+ t

VALID,SO(USCI)

, see the SPI parameters of the attached master.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

1/f

UCxCLK

CKPL=0

UCLK

CKPL=1

SOMI

SIMO

UCLK

SOMI

CKPL=0

CKPL=1

LO/HItLO/HI

VAL I D, MO

SU,MI

HD,MI

Figure 20. SPI Master Mode, CKPH = 0

1/f

UCxCLK

LO/HItLO/HI

SU,MI

VAL I D,MO

HD,MI

SIMO

Figure 21. SPI Master Mode, CKPH = 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

STE

UCLK

SIMO

SOMI

STE

CKPL=0

CKPL=1

STE,ACC

STE,LEAD

1/f

UCxCLK

LO/HItLO/HI

VAL I D,SO

Figure 22. SPI Slave Mode, CKPH = 0

STE,LEAD

SU,SI

HD,SI

STE,LAG

STE,DIS

UCLK

SIMO

SOMI

CKPL=0

CKPL=1

STE,ACC

1/f

UCxCLK

LO/HItLO/HI

SU,SI

VAL I D, SO

Figure 23. SPI Slave Mode, CKPH = 1

HD,SI

STE,DIS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

Pulsewidthofspikessuppressedb

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (I2C Mode) (see Figure 24)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

USCI input clock frequency

SCL clock frequency 2.2 V/3 V 0 400 kHz

Hold time (repeated) START

Setup timefor a repeated START

Data hold time 2.2 V/3 V 0 ns

Data setup time 2.2 V/3 V 250 ns

SetuptimeforSTOP 2.2 V/3 V 4.0 μs

Pulse width ofspikes su

ressed b

input filter

External: UCLK Duty cycle = 50% ± 10%

≤ 100 kHz 2.2 V/3 V 4.0

SCL

> 100 kHz 2.2 V/3 V 0.6

SCL

≤ 100 kHz 2.2 V/3 V 4.7

SCL

> 100 kHz 2.2 V/3 V 0.6

SCL

2.2 V 50 150 600

3V 50 100 600

SYSTEM

MHz

μs

SDA

SCL

HD,STA

1/f

SCL

HD,DAT

SU,STAtHD,STA

SU,DAT

Figure 24. I2C Mode Timing

SU,STO

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

ply

ADC10supplycurren

I:4085C

_5V

REFON=1

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, power supply and input range conditions (see Note 1)

ADC10

PARAMETER TEST CONDITIONS T

Analog supply voltage range

Analog input voltage range (see Note 2)

DC10 su

current

(see Note 3)

VSS=0V 2.2 3.6 V

All Ax terminals. Analog inputs selected in ADC10AE register

ADC10CLK

=5.0MHz

ADC10ON = 1, REFON = 0,

DC10SHT0 = 1,

ADC10SHT1 = 0,

I: -40--85°C T: -40--105°C

ADC10DIV = 0

REF+

REFB,0

REFB,1

Reference supply current, reference bu

er disabled

(see Note 4)

Reference buffer supply current withADC10SR = 0 (see Note 4)

Reference buffer supply current withADC10SR = 1 (see Note 4)

ADC10CLK

ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0

ADC10CLK

ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0

ADC10CLK

ADC10ON = 0, REFON = 1, REF2 REFOUT = 1, ADC10SR=0

ADC10CLK

ADC10ON = 0, REFON = 1 REF2_5V = 0, REFOUT = 1,

=5.0MHz,

I: -40--85°C T: -40--105°C

-40--85°C 2.2 V/3 V 1.1 1.4

=0,

105°C 2.2 V/3 V 1.8

-40--85°C 2.2 V/3 V 0.5 0.7

105°C 2.2 V/3 V 0.8

ADC10SR=1

Input capacitance

Input MUX ON resistance 0V ≤ VAx≤ V

Only one terminal Ax selected at a time

I: -40--85°C T: -40--105°C

NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.

2. The analog input voltage range must be within the selected reference voltage range V

3. The internal reference supply current is not included in current consumption parameter I

4. The internal reference current is supplied via terminal V

. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

VCC MIN TYP MAX UNIT

0 V

2.2 V 0.52 1.05

3V 0.6 1.2

2.2 V/3 V

0.25 0.4 m

27 pF

2.2 V/3 V 2000 Ω

to V

R+

for valid conversion results.

R--

ADC10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

C,REF

Positivebuiltinreferenc

Maximum

REF

loa

REF

loadregulatio

≈

0.5xV

REF

REF2_5V=0

REF2_5V=1

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, built-in voltage reference

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

≤ 1 mA, REF2_5V = 0 2.2

CC,REF+

REF+

LD,VREF+

Positive built-in reference analog supplyvo

age range

Positive built-in reference voltage

Maximum V

load

current

load regulation

REF+

load regulation

response time

Max. capacitance at pin

VREF+

REF+

(see Note 1)

REF+

Temperature coefficient

Settling time of internal

REFON

reference voltage (see Note 2)

Settling time of reference bu

REFBURST

(see Note 2)

NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V

must be limited; the reference buffer may become unstable otherwise.

2. The condition is that the error in a conversion started after t

VREF+

≤ 0.5 mA, REF2_5V = 1 2.8

VREF+

≤ 1 mA, REF2_5V = 1 2.9

VREF+

≤ I

max, REF2_5V = 0 2.2 V/3 V 1.41 1.5 1.59

VREF+

max, REF2_5V = 1 3V 2.35 2.5 2.65

VREF+

2.2 V ±0.5

= 500 μA ± 100 μA,

VREF+

Analog input voltage V

≈ 0.75 V,

2.2 V/3 V ±2

REF2_5V = 0

= 500 μA ± 100 μA,

VREF+

Analog input voltage V

≈ 1.25 V,

REF2_5V = 1

= 100 μA → 900 μA,

VREF+

≈ 0.5

Error of conversion result ≤1LSB

≤±1mA,

VREF+

REFON = 1, REFOUT = 1

= const. with

VREF+

0mA≤ I

VREF+

≤ 1mA

VREF+

= 0.5 mA, REF2_5V = 0,

REFON = 0 → 1

=0.5mA,

VREF+

REF2 5

=0,

, REFON = 1, REFBURST = 1

=0.5mA,

VREF+

REF2 5

=1,

, REFON = 1, REFBURST = 1

ADC10SR=0

ADC10SR=1

ADC10SR=0

ADC10SR=1

ADC10SR=0

ADC10SR=1

REFON

or t

2.2 V/3 V 100 pF

2.2 V/3 V ±100 ppm/°C

3.6 V 30 μs

2.2

is less than ±0.5 LSB.

RefBuf

3V ±1

3V ±2

400

2000

2.5

4.5

REF+/VeREF+

(REFOUT=1),

LSB

μs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

Positiveexternalreferenceinpu

/3V

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, external reference (see Note 1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

eREF+>VeREF--

eREF+

Positive external reference input voltage range (see Note 2)

SREF1 = 1, SREF0 = 0

≤ V

eREF--

SREF1=1,SREF0=1(seeNote3)

eREF--

Negative external reference input voltage range (see Note 4)

eREF+>VeREF--

Differential external reference input

∆V

eREF

voltage range ∆V

eREF=VeREF+

-- V

eREF--

eREF+>VeREF--

0V ≤ V

eREF+

SREF1 = 1, SREF0 = 0

VeREF+

Static input current into V

eREF+

0V ≤V

eREF+

SREF1=1,SREF0=1(seeNote3)

VeREF --

Static input current into V

eREF--

0V ≤ V

eREF--

NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI,isalso

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.

3. Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current I

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

4. The accuracy limits the maximum negative external reference v oltage. Higher reference voltage levels may be applied with reduced accuracy requirements.

5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

≤ VCC-- 0.15 V,

eREF+

1.4 V

1.4 3.0

0 1.2 V

(see Note 5) 1.4 V

≤ VCC,

≤ VCC-- 0.15 V ≤ 3V,

≤ V

2.2

2.2 V/3 V ±1 μA

±1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

perf

performanceof

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, timing parameters

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

For specified

ADC10CLK

DC10 input clockfrequency

ormance o ADC10 linearity parameters

ADC10OSC

ADC10 built-in oscillator frequency

ADC10DIVx = 0, ADC10SSELx = 0, f

ADC10CLK=fADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0, f

CONVERT

Conversion time

ADC10CLK=fADC10OSC

ADC10CLK

from ACLK, MCLK or

SMCLK, ADC10SSELx ≠ 0

ADC10ON

Turn on settling time of the ADC (see Note 1) 100 ns

NOTES: 1. The condition is that the error in a conversion started after t

settled.

ADC10ON

ADC10SR=0

ADC10SR=1

2.2

0.45 6.3

MHz

0.45 1.5

2.2 V/3 V 3.7 6.3 MHz

2.2 V/3 V 2.06 3.51

13×

μs

ADC10DIV× 1/f

ADC10CLK

is less than ±0.5 LSB. The reference and input signal are already

10-bit ADC, linearity parameters

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

NOTES: 1. The reference buffer offset adds to the gain and total unadjusted error.

Integral linearity error 2.2 V/3 V ±1 LSB

Differential linearity error 2.2 V/3 V ±1 LSB

Offset error

Source impedance RS< 100 Ω, 2.2 V/3 V ±1 LSB

SREFx = 010, unbuffered external reference, V

eREF+

=1.5V

SREFx = 010, unbuffered external

Gain error

reference, V

SREFx = 011, buffered external reference(seeNote1), V

=1.5V

eREF+

=2.5V

SREFx = 011, buffered external reference(seeNote1), V

=2.5V

eREF+

SREFx = 010, unbuffered external reference, V

eREF+

=1.5V

SREFx = 010, unbuffered external

Total unadjusted error

reference, V

SREFx = 011, buffered external reference(seeNote1),

=1.5V

eREF+

=2.5V

SREFx = 011, buffered external reference(seeNote1), V

=2.5V

eREF+

2.2 V ±1.1 ±2

3V ±1.1 ±2

2.2 V ±1.1 ±4

3V ±1.1 ±3

2.2 V ±2 ±5

3V ±2 ±5

2.2 V ±2 ±7

3V ±2 ±6

LSB

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MSP430x22x2, MSP430x22x4

ply

Temperaturesensorsupply

REFON=0,INCHx=0Ah

Sensoroutputvoltage

Currentintodividera

ADC10ON=1,INCHx=0Bh

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, temperature sensor and built-in V

PARAMETER

SENSOR

Offset,Sensor

Sensor

Temperature sensor su current (see Note 1)

†

Sensor offset voltage

Sensor output voltage (see Note 3)

Sample time required if

Sensor(sample)

VMID

MID

channel 10 is selected (see Note 4)

Current into divider at channel 11 (see Note 5)

VCCdivider at channel 11

Sample time required if

VMID(sample)

channel 11 is selected (see Note 6)

NOTES: 1. The sensor current I

is high). When REFON = 1, I sensor input (INCH = 0Ah).

2. The following formula can be used to calculate the temperature sensor output voltage: V

Sensor,typ

=TC =TC

Sensor

3. Results based on characterization and/or production test, not TC

4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t

5. No additional current is needed. The V

6. Theontime,t

VMID(on)

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal

SENSOR

is included in I

( 273 + T [°C] ) + V T[°C] + V

Sensor(TA

, is included in the sampling time, t

TEST CONDITIONS VCC MIN TYP MAX UNIT

REFON = 0, INCHx=0Ah, T

=25_C

ADC10ON = 1, INCHx = 0Ah (see Note 2)

Temperature sensor voltage at T

= 105°C (T v ersion only)

Temperature sensor voltage at T

=85°C

Temperature sensor voltage at T

=25°C

Temperature sensor voltage at T

=0°C

ADC10ON = 1, INCHx = 0Ah, Error of conversion result ≤ 1LSB

DC10ON = 1, INCHx=0Bh

DC10ON = 1, INCHx=0Bh,

is ≈0.5 x V

MID

DC10ON = 1, INCHx=0Bh,

Error of conversion result ≤ 1LSB

Offset,sensor

=0°C) [mV]

is used during sampling.

MID

. When REFON = 0, I

REF+

[mV] or

VMID(sample)

2.2 V 40 120

3V 60 160

2.2 V/3 V 3.44 3.55 3.66 mV/°C

2.2 V/3 V 1265 1365 1465

2.2 V/3 V 1195 1295 1395

2.2 V/3 V 985 1085 1185

2.2 V/3 V 895 995 1095

2.2 V/3 V 30 μs

2.2 V NA

3V NA

2.2 V 1.06 1.1 1.14

3V 1.46 1.5 1.54

2.2 V 1400

3V 1220

applies during conversion of the temperature

SENSOR

Sensor

or V

Offset,sensor

; no additional on time is needed.

--100 100 mV

SENSOR(on)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

Supplycurrent(seeNote1)

2.2V/3V

Ikg

(

d2)

2.2V/3V

(I/P)

V(I/P

)

1kH

(I/P)

V(I/P

)

10kHz

/3V

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

operational amplifier OA, supply specifications (MSP430x22x4 only)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V 70 dB

NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively.

operational amplifier OA, input/output specifications (MSP430x22x4 only)

I/P

O/P(OAx)

CMRR Common-mode rejection ratio Noninverting 2.2 V /3 V 70 dB

NOTES: 1. ESD damage can degrade input current leakage.

Supply voltage range 2.2 3.6 V

Fast Mode 180 290

Supply current (see Note 1)

Medium Mode

Slow Mode

2.2 V/3 V

110 190

50 80

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Input voltage range -- 0 . 1 VCC-- 1 . 2 V

TA=--40to+55_C -- 5 ±0.5 5

Input leakage current

seeNotes1an

TA=+55to+85_C

TA= +85 to +105_C

2.2 V/3 V

-- 2 0 ±5 20

-- 5 0 50

Fast Mode 50

Voltage noise density, I/P

Medium Mode

Slow Mode

Fast Mode

Medium Mode

Slow Mode

=1kHz

=10kHz

140

Offset voltage, I/P 2.2 V/3 V ±10 mV

Offset temperature drift, I/P seeNote3 2.2 V/3 V ±10 μV/°C

Offset voltage drift with supply, I/P

High-level output voltage, O/P

Low-level output voltage, O/P

Output resistance (see Figure 25 and Note 4)

0.3 V ≤ VIN≤ VCC-- 1 . 0 V

∆V

≤±10%, TA=25°C

Fast Mode, I

Slow Mode, I

Fast Mode, I

Slow Mode, I

=3kΩ,C

Load

O/P(OAx)

R V

O/P(OAx)

0.2 V ≤ V

Load

< 0.2 V

=3kΩ,C

> VCC-- 1 . 2 V

=3kΩ,C

O/P(OAx)

SOURCE

Load

≤ VCC-- 0 . 2 V

≤ --500 μA

≤ --150 μA

≤ +500 μA

≤ +150 μA

= 50pF,

2.2 V/3 V ±1.5 mV/V

2.2

VCC-- 0 . 2 V

VCC-- 0 . 1 V

150 250

2.2 V/3 V

150 250

0.1 4

2. The input bias current is overridden by the input leakage current.

3. Calculated using the box method

4. Specification valid for voltage-follower OAx configuration

0.2

0.1

μA

√Hz

Ω

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

SRSlewrat

/μs

(seeFigure26andFigure27

)

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

O/P(OAx)

Load

OAx

O/P(OAx)

Load

Figure 25. OAx Output Resistance Tests

operational amplifier OA, dynamic specifications (MSP430x22x4 only)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Fast Mode 1.2

SR Slew rate

Open-loop voltage gain 100 dB

GBW

en(on)

en(off)

Phase margin CL=50pF 60 deg

Gain margin CL=50pF 20 dB

Gain-bandwidth product (see Figure 26 and Figure 27)

Enable time on ton, Noninverting, Gain = 1 2.2 V/3 V 10 20 μs

Enable time off 2.2 V/3 V 1 μs

Medium Mode

Slow Mode 0.3

Noninverting, Fast Mode, R

=47kΩ,CL=50pF

Noninverting, Medium Mode, R

=300 kΩ,CL= 50pF

Non-inverting, Slow Mode, R

=300 kΩ,CL= 50pF

Max

Min

0.2V

2.2 V/3 V

AVCC--0.2V

0.8

2.2

1.4

0.5

OUT

V/μs

MHz

TYPICAL OPEN-LOOP GAIN vs FREQUENC

140

120

100

Gain -- dB

-- 2 0

-- 4 0

-- 6 0

-- 8 0 1 10 100 1000 10000 100000

Fast Mode

Medium Mode

Slow Mode

Input Frequency -- kHz

Figure 26

TYPICALPHASE vs FREQUENC

-- 5 0

Fast Mode

--100

Medium Mode

--150

Phase -- degrees

Slow Mode

--200

--250 1 10 100 1000 10000 100000

Input Frequency -- kHz

Figure 27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

/3V

2.2V/3V

PLH

PHL

(

ighandhigh--low)

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

operational amplifier OA feedback network, resistor network (see Note 1) (MSP430x22x4 only)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

total

unit

NOTES: 1. A single resistor string is composed of 4 R

operational amplifier OA feedback network, comparator mode (OAFCx = 3) (MSP430x22x4 only)

Level

PLH,tPHL

NOTES: 1. The level is not available due to the analog input voltage range of the operational amplifier.

Total resistance of resistor string 76 96 128 kΩ

Unit resistor of resistor string (see Note 2)

unit

+4R

unit

+2R

unit

+2R

unit

+1R

unit

+1R

4.8 6 8 kΩ

unit

+1R

unit

+1R

unit

=16R

unit=Rtotal

2. For the matching (i.e. the relative accuracy) of the unit resistors on a device refer to the gain and level specifications of the respective configurations.

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

OAFBRx = 1, OARRIP = 0 0.245 1/4 0.255

OAFBRx = 2, OARRIP = 0 0.495 1/2 0.505

OAFBRx = 3, OARRIP = 0 0.619 5/8 0.631

OAFBRx = 4, OARRIP = 0 N/A(seeNote1)

OAFBRx = 5, OARRIP = 0 N/A(seeNote1)

OAFBRx = 6, OARRIP = 0 N/A(seeNote1)

Comparator level

OAFBRx = 7, OARRIP = 0

OAFBRx = 1, OARRIP = 1

2.2

N/A(seeNote1)

0.061 1/16 0.065

OAFBRx = 2, OARRIP = 1 0.122 1/8 0.128

OAFBRx = 3, OARRIP = 1 0.184 3/16 0.192

OAFBRx = 4, OARRIP = 1 0.245 1/4 0.255

OAFBRx = 5, OARRIP = 1 0.367 3/8 0.383

OAFBRx = 6, OARRIP = 1 0.495 1/2 0.505

OAFBRx = 7, OARRIP = 1 N/A(seeNote1)

Fast Mode, Overdrive 10 mV 40

Fast Mode, Overdrive 100 mV

Fast Mode, Overdrive 500 mV

Medium Mode, Overdrive 10 mV 60

Propagation delay

ow--

Medium Mode, Overdrive 100 mV 6

μs

Medium Mode, Overdrive 500 mV 5

Slow Mode, Overdrive 10 mV 160

Slow Mode, Overdrive 100 mV 20

Slow Mode, Overdrive 500 mV 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

/3V

Totalharmonicdistortion

GGain

2.2V/3V

Totalharmonicdistortion

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4) (MSP430x22x4 only)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

OAFBRx = 0 0.998 1.00 1.002

OAFBRx = 1 1.328 1.334 1.340

OAFBRx = 2 1.985 2.001 2.017

G Gain

THD

Settle

NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

Total harmonic distortion nonlinearity

Settlingtime(seeNote1) All power modes 2.2 V/3 V 7 12 μs

settling time of the amplifier itself might be faster.

OAFBRx = 3

OAFBRx = 4

OAFBRx = 5 5.22 5.33 5.44

OAFBRx = 6 7.76 7.97 8.18

OAFBRx = 7 15.0 15.8 16.6

ll gains

2.2

2.2 V -- 6 0

3V -- 7 0

2.638 2.667 2.696

3.94 4.00 4.06

operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6) (see Note 1) (MSP430x22x4 only)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

OAFBRx = 1 --0.345 --0.335 --0.325

OAFBRx = 2 --1.023 --1.002 --0.979

OAFBRx = 3 --1.712 --1.668 --1.624

G Gain

THD

Settle

NOTES: 1. This includes the 2 OA configuration “inverting amplifier with input buffer”. Both OA needs to be set to the same power mode OAPMx.

Total harmonic distortion nonlinearity

Settlingtime(seeNote2) All power modes 2.2 V/3 V 7 12 μs

2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster.

OAFBRx = 4

OAFBRx = 5

OAFBRx = 6 --7.37 --6.97 --6.57

OAFBRx = 7 --16.3 --14.8 --13.1

ll gains

2.2 V/ 3 V

2.2 V -- 6 0

3V -- 7 0

--3.10 --3.00 --2.90

--4.51 --4.33 --4.15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

Flash Memory

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

CC(PGM/

ERASE)

FTG

PGM

ERASE

CPT

CMErase

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

RAM

(RAMh)

NOTE 1: This parameter defines the minimum supply voltage VCCwhen the data in RAM remains unchanged. No program execution should

Program and erase supply voltage 2.2 3.6 V

Flash timing generator frequency 257 476 kHz

Supply current from VCCduring program 2.2 V/3.6 V 1 5 mA

Supply current from VCCduring erase 2.2 V/3.6 V 1 7 mA

Cumulative program time (see Note 1) 2.2 V/3.6 V 10 ms

Cumulative mass erase time 2.2 V/3.6 V 20 ms

Program/erase endurance 10

Data retention duration TJ=25°C 100 years

Word or byte program time seeNote2 30

Block program time for first byte or word seeNote2 25

Block program time for each additional byte or word seeNote2 18

Block program end-sequence wait time seeNote2 6

Mass erase time seeNote2 10593

Segment erase time seeNote2 4819

methods: individual word/byte write and block write modes.

2. These values are hardwired into the flash controller’s state machine (t

FTG

=1/f

FTG

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RAM retention supply voltage (see Note 1) CPU halted 1.6 V

happen during this supply voltage condition.

cycles

FTG

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MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

JTAG and Spy-Bi-Wire Interface

PARAMETER

SBW

SBW,Low

SBW,En

SBW,Ret

TCK

Internal

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

Spy-Bi-Wire input frequency 2.2 V / 3 V 0 20 MHz

Spy-Bi-Wire low clock pulse length 2.2 V / 3 V 0.025 15 μs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge, seeNote1)

Spy-Bi-Wire return to normal operation time 2.2 V/ 3 V 15 100 μs

TCK inputfrequency (see Note 2)

Internal pull-down resistance on TEST 2.2 V/ 3 V 25 60 90 kΩ

before applying the first SBWCLK clock edge.

2. f

may be restricted to meet the timing requirements of the module selected.

TCK

JTAG Fuse (see Note 1)

PARAMETER

CC(FB)

NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible, and it is switched to bypass mode.

Supply voltage during fuse-blow condition TA=25°C 2.5 V

Voltage level on TEST for fuse blow 6 7 V

Supply current into TEST during fuse blow 100 mA

Time to blow fuse 1 ms

TEST

CONDITIONS

TEST

CONDITIONS

VCC MIN TYP MAX UNIT

2.2 V/ 3 V 1 μs

2.2 V 0 5

3V 0 10

time after pulling the TEST/SBWCLK pin high

SBW,En

VCC MIN TYP MAX UNIT

MHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger

MSP430x22x2, MSP430x22x4

SLAS504B -- JULY 2006 -- REVISED JULY 2007

P1REN.x

P1DIR.x

P1OUT.x

Module X OUT

P1SEL.x

P1IN.x

Module X IN

P1IRQ.x

P1IE.x

P1IFG.x

P1SEL.x

P1IES.x

Pad Logic

DVSS

DVCC

Direction 0: Input 1: Output

Set

Interrupt

Edge

Select

P1.0/TACLK/ADC10CLK P1.1/T A0 P1.2/T A1 P1.3/T A2

Port P1 (P1.0 to P1.3) pin functions

PIN NAME (P1.X)

P1.0/ 0 TACLK/ADC10CLk

P1.1/TA0 1

P1.2/TA1 2

P1.3/TA2 3

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

P1.0† (I/O) I: 0; O: 1 0

Timer_A3.TACLK 0 1

ADC10CLK 1 1

P1.1† (I/O) I: 0; O: 1 0

Timer_A3.CCI0A 0 1

Timer_A3.TA0 1 1

P1.2† (I/O) I: 0; O: 1 0

Timer_A3.CCI0A 0 1

Timer_A3.TA0 1 1

P1.3† (I/O) I: 0; O: 1 0

Timer_A3.CCI0A 0 1

Timer_A3.TA0 1 1

FUNCTION

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x

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MSP430x22x2, MSP430x22x4

///

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P1 pin schematic: P1.4 to P1.6, input/output with Schmitt trigger and in-system access features

Pad Logic

P1REN.x

P1DIR.x

P1OUT.x

Module X OUT

P1SEL.x

P1IN.x

Module X IN

P1IRQ.x

To JTA G

P1IE.x

P1IFG.x

P1SEL.x

P1IES.x

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

Set

Interrupt

Edge

Select

P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI

From JTAG

Port P1 (P1.4 to P1.6) pin functions

PIN NAME (P1.X)

P1.4/SMCLK/TCK 4

P1.5/TA0/TMS 5

P1.6/TA1/TDI/TCLK 6

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Function controlled by JTAG.

P1.4† (I/O) I: 0; O: 1 0 0

SMCLK 1 1 0

TCK X X 1

P1.5† (I/O) I: 0; O: 1 0 0

Timer_A3.TA0 1 1 0

TMS X X 1

P1.6† (I/O) I: 0; O: 1 0 0

Timer_A3.TA1 1 1 0

TDI/TCLK(seeNote3) X X 1

FUNCTION

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x 4-Wire JTAG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

///

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P1 pin schematic: P1.7, input/output with Schmitt trigger and in-system access features

Pad Logic

P1REN.7

P1DIR.7

P1OUT.7

Module X OUT

P1SEL.7

P1IN.7

Module X IN

P1IRQ.7

To JTA G

P1IE.7

P1IFG.7

P1SEL.7

P1IES.7

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

Set

Interrupt

Edge

Select

P1.7/T A2/TDO/TDI

From JTAG

From JTAG (TDO)

Port P1 (P1.7) pin functions

PIN NAME (P1.X)

P1.7/TA2/TDO/TDI 7

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Function controlled by JTAG.

P1.7† (I/O) I: 0; O: 1 0 0

Timer_A3.TA2 1 1 0

TDO/TDI (see Note 3) X X 1

FUNCTION

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x 4-Wire JTAG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

///

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.0, P2.2, input/output with Schmitt trigger

To A D C 1 0

INCHx = y

ADC10AE0.y

P2REN.x

Pad Logic

P2DIR.x

P2OUT.x

Module X OUT

P2SEL.x

P2IN.x

Module X IN

P2IRQ.x

P2IFG.x

P2SEL.x

P2IES.x

P2IE.x

Direction 0: Input 1: Output

Set

Interrupt

Edge

Select

OA0

DVSS

DVCC

Bus

Keeper

P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1

Port P2 (P2.0, P2.2) pin functions

PIN NAME (P2.X)

P2.0/ACLK/A0/OA0I0 0 0

P2.2/TA0/A2/OA0I1 2 2

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P2.0† (I/O) I: 0; O: 1 0 0

ACLK 1 1 0

A0/OA0I0 (see Note 3) X X 1

P2.2† (I/O) I: 0; O: 1 0 0

Timer_A3.CCI0B 0 1 0

Timer_A3.TA0 1 1 0

A2/OA0I1 (see Note 3) X X 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

Port P2 pin schematic: P2.1, input/output with Schmitt trigger

To A D C 1 0

INCHx = 1

ADC10AE0.1

P2REN.1

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Pad Logic

P2DIR.1

P2OUT.1

Module X OUT

P2SEL.1

P2IN.1

Module X IN

P2IRQ.1

OAADCx

OAFCx

OAPMx

P2IE.1

P2IFG.1

P2SEL.1

P2IES.1

(OAADCx = 10 or OAFCx = 000) and OAPMx > 00

Direction 0: Input 1: Output

Set

Interrupt

Edge

Select

DVSS

DVCC

Bus

Keeper

OA0

P2.1/TAINCLK/SMCLK/ A1/OA0O

To OA0 Feedback Network

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.3, input/output with Schmitt trigger

SREF2

To A D C 1 0 V

To A D C 1 0

INCHx = 3

ADC10AE0.3

P2REN.3

P2DIR.3

P2OUT.3

Module X OUT

P2SEL.3

P2IN.3

Module X IN

R--

Pad Logic

P2.3/TA1/ A3/VREF--/VeREF--/ OA1I1/OA1O

VSS

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

P2IRQ.3

OAADCx

OAFCx

OAPMx

P2IE.3

P2IFG.3

P2SEL.3

P2IES.3

(OAADCx = 10 or OAFCx = 000) and OAPMx > 00

Set

Interrupt

Edge

Select

To OA1 Feedback Network

OA1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Port P2 (P2.1) pin functions

PIN NAME (P2.X)

P2.1/TAINCLK/SMCLK 1 1 /A1/OA0O

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P2.1† (I/O) I: 0; O: 1 0 0

Timer_A3.INCLK 0 1 0

SMCLK 1 1 0

A1/OA0O (see Note 3) X X 1

Port P2 (P2.3) pin functions

PIN NAME (P2.X)

P2.3/TA1/ 3 3 A3/V

REF--/VeREF--

OA1I1/OA1O

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

P2.3† (I/O) I: 0; O: 1 0 0

Timer_A3.CCI1B 0 1 0

Timer_A3.TA1 1 1 0

A3/V

REF--/VeREF--

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

FUNCTION

/OA1I1/OA1O (see Note 3) X X 1

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.4, input/output with Schmitt trigger

To / f r o m AD C 1 0

positive reference

To A D C 1 0

INCHx = 4

ADC10AE0.4

P2REN.4

P2DIR.4

P2OUT.4

Module X OUT

P2SEL.4

P2IN.4

Pad Logic

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0

Module X IN

P2IRQ.4

P2IE.4

P2IFG.4

P2SEL.4

P2IES.4

Interrupt

Port P2 (P2.4) pin functions

PIN NAME (P2.X)

P2.4/TA2/ 4 4 A4/V

REF+/VeREF+

OA1I0

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

P2.4† (I/O) I: 0; O: 1 0 0

Timer_A3.TA2 1 1 0

A4/V

REF+/VeREF+

Set

Edge

Select

FUNCTION

/OA1I0 (see Note 3) X X 1

OA1

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

OSC

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.5, input/output with Schmitt trigger and external R

To DCO

DCOR

P1REN.x

P1DIR.x

P1OUT.x

Module X OUT

P1SEL.x

P1IN.x

Module X IN

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

for DCO

OSC

Pad Logic

P2.5/ROSC

P1IE.x

P1IRQ.x

P1IFG.x

P1SEL.x

P1IES.x

Port P2 (P2.5) pin functions

PIN NAME (P2.X)

P2.5/R

OSC

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

P2.5† (I/O) I: 0; O: 1 0 0

N/A 0 1 0

OSC

Set

Interrupt

Edge

Select

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x DCOR

1 1 0

X X 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.6, input/output with Schmitt trigger and crystal oscillator input

LFXT1 off

LFXT1CLK

P2SEL.7

P2REN.6

P2DIR.6

P2OUT.6

Module X OUT

P2SEL.6

P2IN.6

BCSCTL3.LFXT1Sx = 11

Direction 0: Input 1: Output

LFXT1 Oscillator

DVSS

DVCC

Bus

Keeper

P2.7/XOUT

Pad Logic

P2.6/XIN

Module X IN

P2IRQ.6

P2IE.6

P2IFG.6

P2SEL.6

P2IES.6

Port P2 (P2.6) pin functions

PIN NAME (P2.X)

P2.6/XIN 6

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

P2.6 (I/O) I: 0; O: 1 0

XIN† X 1

Set

Interrupt

Edge

Select

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P2 pin schematic: P2.7, input/output with Schmitt trigger and crystal oscillator output

LFXT1 off

LFXT1CLK

P2SEL.6

P2REN.7

P2DIR.7

P2OUT.7

Module X OUT

P2SEL.7

P2IN.7

BCSCTL3.LFXT1Sx = 11

From P2.6/XIN

Direction 0: Input 1: Output

LFXT1 Oscillator

DVSS

DVCC

Bus

Keeper

P2.6/XIN

Pad Logic

P2.7/XOUT

Module X IN

P2IRQ.7

P2IE.7

P2IFG.7

P2SEL.7

P2IES.7

Port P2 (P2.7) pin functions

PIN NAME (P2.X)

XOUT/P2.7 6

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset.

P2.7 (I/O) I: 0; O: 1 0

XOUT†(seeNote3) X 1

Set

Interrupt

Edge

Select

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P3 pin schematic: P3.0, input/output with Schmitt trigger

To A D C 1 0

INCHx = 5

ADC10AE0.5

P3REN.0

Pad Logic

P3DIR.0

USCI Direction

Control

P3OUT.0

Module X OUT

P3SEL.0

P3IN.0

Module X IN

Direction 0: Input 1: Output

Port P3 (P3.0) pin functions

PIN NAME (P3.X)

P3.0/ 0 5 UC1STE/UC0CLK/A5

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. The pin direction is controlled by the USCI module.

4. UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected.

5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P3.0† (I/O) I: 0; O: 1 0 0

UC1STE/UC0CLK (see Notes 3, 4) X 1 0

A5 (see Note 5) X X 1

FUNCTION

DVSS

DVCC

Bus

Keeper

P3.0/UC1STE/UC0CLK/A5

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x ADC10AE0.y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt trigger

MSP430x22x2, MSP430x22x4

SLAS504B -- JULY 2006 -- REVISED JULY 2007

P3REN.x

P3DIR.x

USCI Direction

Control

P3OUT.x

Module X OUT

P3SEL.x

P3IN.x

Module X IN

Direction 0: Input 1: Output

Port P3 (P3.1 to P3.5) pin functions

PIN NAME (P3.X)

P3.1/ 1 UC1SIMO/UC1SDA

P3.2/ 1 UC1SOMI/UC1SCL

P3.3/ 1 UC1CLK/UC0STE

P3.4/ 1 UC0TXD/UC0SIMO

P3.5/ 1 UC0RXD/UC0SOMI

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. The pin direction is controlled by the USCI module.

4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected.

P3.1† (I/O) I: 0; O: 1 0

UC1SIMO/UC1SDA (see Note 3) X 1

P3.2† (I/O) I: 0; O: 1 0

UC1SOMI/UC1SCL (see Note 3) X 1

P3.3† (I/O) I: 0; O: 1 0

UC1CLK/UC0STE (see Notes 3, 4) X 1

P3.4† (I/O) I: 0; O: 1 0

UC0TXD/UC0SIMO (see Note 3) X 1

P3.5† (I/O) I: 0; O: 1 0

UC0RXD/UC0SOMI (see Note 3) X 1

DVSS

FUNCTION

DVSS

DVCC

Bus

Keeper

Pad Logic

P3.1/UC1SIMO/UC1SCL P3.2/UC1SOMI/UC1SDA P3.3/UC1CLK/UC0STE P3.4/UC0TXD/UC0SIMO P3.5/UC0RXD/UC0SOMI

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt trigger

To A D C 1 0

INCHx = y

ADC10AE0.y

P3REN.x

Pad Logic

P3DIR.x

DVSS

P3OUT.x

Module X OUT

P3SEL.x

P3IN.x

Module X IN

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

OA0/1

P3.6/A6/OA0I2 P3.7/A7/OA1I2

Port P3 (P3.6, P3.7) pin functions

PIN NAME (P3.X)

P3.6/A6/OA0I2 6 6

P3.7/A7/OA1I2 7 7

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. The pin direction is controlled by the USCI module.

4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected.

5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P3.6† (I/O) I: 0; O: 1 0 0

A6/OA0I2 (see Note 5) X X 1

P3.7† (I/O) I: 0; O: 1 0 0

A7/OA1I2 (see Note 5) X X 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x ADC10AE0.y

MIXED SIGNAL MICROCONTROLLER

Port P4 pin schematic: P4.0 to P4.2, input/output with Schmitt trigger

Timer_B Output Tristate Logic

P4SEL.6

P4DIR.6

ADC10AE1.7

P4REN.x

MSP430x22x2, MSP430x22x4

SLAS504B -- JULY 2006 -- REVISED JULY 2007

P4.6/TBOUTH/A15/OA 1I3

Pad Logic

P4DIR.x

P4OUT.x

Module X OUT

P4SEL.x

P4IN.x

Module X IN

Direction 0: Input 1: Output

Port P4 (P4.0 to P4.2) pin functions

PIN NAME (P4.X)

P4.0/TB0 0

P4.1/TB1 1

P4.2/TB2 2

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

P4.0† (I/O) I: 0; O: 1 0

Timer_B3.CCI0A 0 1

Timer_B3.TB0 1 1

P4.1† (I/O) I: 0; O: 1 0

Timer_B3.CCI1A 0 1

Timer_B3.TB1 1 1

P4.2† (I/O) I: 0; O: 1 0

Timer_B3.CCI2A 0 1

Timer_B3.TB2 1 1

FUNCTION

DVSS

DVCC

Bus

Keeper

P4.0/TB0 P4.1/TB1 P4.2/TB2

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P4 pin schematic: P4.3 to P4.4, input/output with Schmitt trigger

Timer_B Output Tristate Logic

P4SEL.6

P4DIR.6

ADC10AE1.7

P4.6/TBOUTH/A15/OA1I3

To A D C 1 0

INCHx = 8+y

ADC10AE1.y

P4REN.x

P4DIR.x

P4OUT.x

Module X OUT

P4SEL.x

P4IN.x

Module X IN

Pad Logic

†

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O

OA0/1

OAADCx

OAPMx

†

If OAADCx = 11and not OAFCx = 000 the ADC input A12 or A13 is internally connected to the OA0 or OA1 output respectively and the connections from the ADC and the operational amplifiers to the pad are disabled.

OAADCx = 01 and OAPMx > 00

To OA0/1 Feedback Network

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Port P4 (P4.3 to P4.4) pin functions

///

PIN NAME (P4.X)

P4.3/TB0/A12/OA0O 3 4

P4.4/TB1/A13/OA1O 4 5

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P4.3† (I/O) I: 0; O: 1 0 0

Timer_B3.CCI0B 0 1 0

Timer_B3.TB0 1 1 0

A12/OA0O (see Note 3) X X 1

P4.4† (I/O) I: 0; O: 1 0 0

Timer_B3.CCI1B 0 1 0

Timer_B3.TB1 1 1 0

A13/OA1O (see Note 3) X X 1

FUNCTION

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P4 pin schematic: P4.5, input/output with Schmitt trigger

Timer_B Output Tristate Logic

P4SEL.6

P4DIR.6

ADC10AE1.7

P4.6/TBOUTH/A15/OA1I3

To A D C 1 0

INCHx = 14

ADC10AE1.6

P4REN.5

P4DIR.5

P4OUT.5

Module X OUT

P4SEL.5

P4IN.5

Module X IN

Pad Logic

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

P4.5/TB3/A14/OA0I3

OA0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Port P4 (P4.5) pin functions

///

PIN NAME (P4.X)

P4.5/TB3/A14/OA0I3 5 6

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P4.5† (I/O) I: 0; O: 1 0 0

Timer_B3.TB2 1 1 0

A14/OA0I3 (see Note 3) X X 1

FUNCTION

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Port P4 pin schematic: P4.6, input/output with Schmitt trigger

To A D C 1 0

INCHx = 15

ADC10AE1.7

P4REN.6

Pad Logic

P4DIR.6

P4OUT.6

Module X OUT

P4SEL.6

P4IN.6

Module X IN

DVSS

DVCC

Direction 0: Input 1: Output

Bus

Keeper

OA1

P4.6/TBOUTH/ A15/OA1I3

Port P4 (P4.6) pin functions

PIN NAME (P4.X)

P4.6/TBOUTH/ 6 7 A15/OA1I3

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals.

P4.6† (I/O) I: 0; O: 1 0 0

TBOUTH 0 1 0

A15/OA1I3 (see Note 3) X X 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

1 1 0

Port P4 pin schematic: P4.7, input/output with Schmitt trigger

MSP430x22x2, MSP430x22x4

MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

P4REN.x

P4DIR.x

P4OUT.x

Module X OUT

P4SEL.x

P4IN.x

Module X IN

Port P4 (P4.7) pin functions

PIN NAME (P4.X)

P4.7/TBCLK 7

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable

2. X: Don’t care

P4.7† (I/O) I: 0; O: 1 0

Timer_B3.TBCLK 0 1

Direction 0: Input 1: Output

FUNCTION

DVSS

DVCC

Bus

Keeper

Pad Logic

P4.7/TBCLK

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x

1 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER

SLAS504B -- JULY 2006 -- REVISED JULY 2007

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).

, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

Time TMS Goes Low After POR

TMS

TEST

Figure 28. Fuse Check Mode Current, MSP430F22xx

NOTE:

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

Data Sheet Revision History

MSP430x22x2, MSP430x22x4

SLAS504B -- JULY 2006 -- REVISED JULY 2007

Literature

Number

SLAS504 Preliminary data sheet release.

Production data sheet release.

SLAS504A

SLAS504B

NOTE: The referring page and figure numbers are referred to the respective document revision.

Updated specification and added characterization graphs. Updated/corrected port pin schematics.

Maximum low-power mode supply current limits decreased. Added note concerning f

to USCI SPI parameters.

UCxCLK

Summary

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

MSP430F2232IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2232IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2232IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2232IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2232TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2232TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2232TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2232TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2234IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2234IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2234IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2234IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2234TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2234TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2234TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2234TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2252IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2252IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2252IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2252IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2252TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

MSP430F2252TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

MSP430F2252TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

MSP430F2252TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

MSP430F2254IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-2-260C-1 YEAR

20-Jul-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

MSP430F2254IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

20-Jul-2007

(3)

no Sb/Br)

MSP430F2254IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2254IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2254TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2254TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2254TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2254TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2272IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2272IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2272IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2272IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2272TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2272TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2272TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2272TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2274IDA ACTIVE TSSOP DA 38 40 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2274IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2274IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2274IRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2274TDA ACTIVE TSSOP DA 38 40 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2274TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSP430F2274TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

MSP430F2274TRHAT ACTIVE QFN RHA 40 250 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

20-Jul-2007

Addendum-Page 3

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS MSP430x22x2, MSP430x22x4 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

description

AVAILABLE OPTIONS

MSP430x22x2 device pinout, DA package

MSP430x22x4 device pinout, DA package

MSP430x22x2 device pinout, RHA package

MSP430x22x4 device pinout, RHA package

MSP430x22x2 functional block diagram

MSP430x22x4 functional block diagram

Terminal Functions, MSP430x22x2

Terminal Functions, MSP430x22x4

short-form description

instruction set

operating modes

interrupt vector addresses

special function registers

interrupt enable 1 and 2

interrupt flag register 1 and 2

memory organization

bootstrap loader (BSL)

flash memory

peripherals

oscillator and system clock

brownout

digital I/O

timer_A3

timer_B3

ADC10

operational amplifier OA (MSP430x22x4 only)

peripheral file map

absolute maximum ratings (see Note 1)

recommended operating conditions

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

active mode supply current (into DVCC+AVCC) excluding external current (see Notes 1 and 2)

low power mode supply currents (into DVCC+AVCC) excluding external current (see Notes 1 and 2)

POR/brownout reset (BOR) (see Notes 1 and 2)

main DCO characteristics

DCO frequency

wake-up from lower power modes (LPM3/4)

crystal oscillator, LFXT1, low frequency modes (see Note 4)

internal very low power, low frequency oscillator (VLO)

crystal oscillator, LFXT1, high frequency modes (see Note 5)

Timer_A

Timer_B

USCI (UART Mode)

10-bit ADC, power supply and input range conditions (see Note 1)

10-bit ADC, built-in voltage reference

10-bit ADC, external reference (see Note 1)

10-bit ADC, timing parameters

10-bit ADC, linearity parameters

operational amplifier OA, supply specifications (MSP430x22x4 only)

operational amplifier OA, input/output specifications (MSP430x22x4 only)

operational amplifier OA, dynamic specifications (MSP430x22x4 only)

Flash Memory

JTAG and Spy-Bi-Wire Interface

APPLICATION INFORMATION

Port P1 (P1.0 to P1.3) pin functions

Port P1 (P1.4 to P1.6) pin functions

Port P1 (P1.7) pin functions

Port P2 (P2.0, P2.2) pin functions

Port P2 (P2.1) pin functions

Port P2 (P2.3) pin functions

Port P2 (P2.4) pin functions

Port P2 (P2.5) pin functions

Port P2 (P2.6) pin functions

Port P2 (P2.7) pin functions

Port P3 (P3.0) pin functions

Port P3 (P3.1 to P3.5) pin functions

Port P3 (P3.6, P3.7) pin functions

Port P4 (P4.0 to P4.2) pin functions

Port P4 (P4.3 to P4.4) pin functions

Port P4 (P4.5) pin functions

Port P4 (P4.6) pin functions

Port P4 (P4.7) pin functions

JTAG fuse check mode

Data Sheet Revision History