TEXAS INSTRUMENTS MSP430x22x2, MSP430x22x4 Technical data
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption
-- Active Mode: 270 μAat1MHz,2.2V
-- Standby Mode: 0.7 μA
-- Off Mode (RAM Retention): 0.1 μA
D Ultrafast Wake-Up From Standby Mode in
Less Than 1 μs
D 16-Bit RISC Architecture, 62.5-ns
Instruction Cycle Time
D Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very-Low-Power Low-Frequency
Oscillator
-- 32-kHz Crystal
-- High-Frequency Crystal up to 16 MHz
-- Resonator
-- External Digital Clock Source
-- External Resistor
D 16-Bit Timer_A With Three
Capture/Compare Registers
D 16-Bit Timer_B With Three
Capture/Compare Registers
D Universal Serial Communication Interface
-- Enhanced UART Supporting
Auto-Baudrate Detection (LIN)
-- IrDA Encoder and Decoder
-- Synchronous SPI
2
C™
-- I
D 10-Bit, 200 -ksps A/D Converter With
Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller
D Two Configurable Operational Amplifiers
(MSP430x22x4 Only)
D Brownout Detector
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
D Bootstrap Loader
D On Chip Emulation Module
D Family Members Include:
MSP430F2232: 8KB + 256B Flash Memory
512B RAM
MSP430F2252: 16KB + 256B Flash Memory
512B RAM
MSP430F2272: 32KB + 256B Flash Memory
1KB RAM
MSP430F2234: 8KB + 256B Flash Memory
512B RAM
MSP430F2254: 16KB + 256B Flash Memory
512B RAM
MSP430F2274: 32KB + 256B Flash Memory
1KB RAM
Available in a 38-Pin Thin Shrink
Small-Outline Package (TSSOP) and 40-Pin
QFN Package
D For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 μs.
The MSP430x22xx series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a
universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer
controller (DTC), two general-purpose operational amplifiers in the MSP430x22x4 devices, and 32 I/O pins.
Typicalapplications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2007 Texas Instruments Incorporated
1
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
T
A
-- 4 0 °Cto85°C
-- 4 0 °C to 105°C
†
Product Preview
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
38-PIN TSSOP
(DA)
MSP430F2232IDA
MSP430F2252IDA
MSP430F2272IDA
MSP430F2234IDA
MSP430F2254IDA
MSP430F2274IDA
MSP430F2232TDA
MSP430F2252TDA
MSP430F2272TDA
MSP430F2234TDA
MSP430F2254TDA
MSP430F2274TDA
PLASTIC
40-PIN QFN
MSP430F2232IRHA
MSP430F2252IRHA
MSP430F2272IRHA
MSP430F2234IRHA
MSP430F2254IRHA
MSP430F2274IRHA
†
MSP430F2232TRHA
†
MSP430F2252TRHA
†
MSP430F2272TRHA
MSP430F2234TRHA
MSP430F2254TRHA
MSP430F2274TRHA
(RHA)
†
†
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x2 device pinout, DA package
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
1TEST/SBWTCK
2DVCC
3P2.5/Rosc
DVSS
XOUT/P2 .7
XIN/P2 .6
RST /NMI /SBWTDIO
P2.0/ACLK /A0
P2 .1 /TAINCLK /SMCLK /A1
P2 .2 /TA 0/A2
P3 .0 /UCB 0STE /UCA 0CLK /A 5
P3 .1 /UCB 0SIMO /UCB 0SDA
P3 .2/UCB 0SOMI /UCB 0SCL
P3 .3 /UCB 0CLK /UCA 0STE
AVSS
P4.0/TB 0
P4.1/TB 1
P4.2/TB 2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 P4.4 /TB 1/A 13
19
MSP430x22x4 device pinout, DA package
38 P1.7 /TA 2/TDO /TDI
37 P1.6 /TA 1/TDI
36 P1.5 /TA 0/TMS
35 P 1.4/SMCLK /TCK
34 P 1.3/TA 2
33 P 1.2/TA 1
32 P 1.1/TA 0
31 P 1.0/TACLK /ADC 10 CLK
30 P2.4 /TA 2/A 4 /VREF+/ VeREF +
29 P2.3 /TA 1/A 3 /VREF-- /VeREF --
28 P 3.7/A7
27 P 3.6/A6
26 P 3.5/UCA 0RXD /UCA0SOMI
25 P 3.4/UCA 0 TXD /UCA0SIMO
P4.7/TBCLK
24
P4.6/TBOUTH /A15
23AVC C
22
P4.5 /TB 2/A 14
21
20
P4.3 /TB 0/A 12
DVSS
XOUT/P 2.7
XIN /P2. 6
RST /NMI /SBWTDIO
P2 .0 / ACLK /A0/OA 0I0
P2 .1 /TAINCLK /SMCLK /A1 /OA 0O
P2 .2 /TA 0/A2 /OA 0I1
P3 .0 /UCB 0STE /UCA 0CLK /A 5
P3 .1 /UCB 0SIMO/UCB 0 SDA
P3.2/UCB 0SOMI/UCB 0 SCL
P3 .3 /UCB 0CLK /UCA 0STE
AVSS
P4 .0 /TB 0
P4 .1 /TB 1
P4 .2 /TB 2
1TEST/SBWTCK
2DVCC
3P2.5/Rosc
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 P 4.4/TB 1/A13 /OA1O
19
38 P1 .7/TA2/TDO /TDI
37 P 1.6/TA 1/TDI
36 P 1.5/TA 0 /TMS
35 P 1.4/SMCLK /TCK
34 P 1.3/TA 2
33 P 1.2/TA 1
32 P 1.1/TA 0
31 P 1.0/TACLK /ADC 10 CLK
30 P 2.4/TA 2 /A 4/VREF +/VeREF +/ OA 1I0
29 P 2.3/TA 1 /A 3/VREF --/ VeREF --/OA 1I1/OA 1O
28 P 3.7/A7/OA 1I2
27 P 3.6/A6/OA 0I2
26 P 3.5/UCA 0RXD /UCA0SOMI
25 P 3.4/UCA 0TXD /UCA0SIMO
P4.7/TBCLK
24
P4.6/TBOUTH/A15/OA1I3
23AVC C
P4.5/TB2/A14 /OA0I3
22
21
P4.3/TB0/A12 /OA0O
20
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3
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
MSP430x22x2 device pinout, RHA package
XOUT /P2.7
XIN /P2. 6
DVSS
RST /NMI /SBWTDIO
P2.0/ACLK /A0
P2 .1 /TAINCLK /SMCLK /A 1
P2.2 /TA 0/A 2
P3 .0 /UCB 0STE /UCA 0CLK /A5
P3 .1 /UCB 0SIMO /UCB 0SDA
P2.5/Rosc
1DVSS
2
3
4
5
6
7
8
9
10
12 14 15 16 17 18 19
P3.2/UCB0SOMI/UCB0SCL
TEST/SBWTCK
DVCC
DVCC
P1.7/T A2/TD O /T D I
3839 37 36 35 34 33 32
13
AVSS
AVCC
P4 .0 /TB0
P3.3/UCB0CLK/UCA0STE
P1 .5 /T A0 / T M S
P1 .6 /T A1 / T D I/T CLK
P4 .1 /TB1
P4 .2 /TB2
P1 .2 /T A1
P1 .3 /T A2
P1 .4 /SM CLK/TC K
30
P1.1/TA0
29
P1.0/TACLK /ADC 10CLK
28
P2 .4 / TA 2 /A4/VREF+/ VeREF+
27
P2 .3 / TA 1 /A3/VREF-- / V e R E F--
26
P3.7/A7
25
P3.6/A6
24
P3 .5 /UCA 0RXD/UCA0SOMI
23
P3 .4 /UCA 0TXD/UCA0SIMO
22
P4.7/TBCLK
21
P4.6/TBOUTH/A15
P4.3 /TB 0/A 1 2
P4.4 /TB 1/A 1 3
P4.5 /TB 2/A 1 4
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x4 device pinout, RHA package
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
XOUT /P2.7
XIN /P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK /A0/OA 0I0
P2 .1 /TAINCLK /SMCLK /A1/ OA 0O
P2 .2 /TA 0/A2 /OA 0I1
P3 .0 /UCB 0STE /UCA 0CLK /A5
P3 .1 /UCB 0SIMO /UCB 0SDA
P2.5/Rosc
1DVSS
2
3
4
5
6
7
8
9
10
12 14 15 16 17 18 19
P3.2/UCB0SOMI/UCB0SCL
TEST/SBWTCK
DVCC
DVCC
P1.7/T A2/TD O /T D I
3839 37 36 35 34 33 32
13
AVSS
AVCC
P4 .0 /TB0
P3.3/UCB0CLK/UCA0STE
P1 .5 /T A0 / T M S
P1 .6 /T A1 / T D I/T CLK
P4 .1 /TB1
P4 .2 /TB2
P1 .2 /T A1
P1 .3 /T A2
P1 .4 /SM CLK/TC K
30
P1.1/TA0
29
P1.0/TACLK /ADC 10CLK
28
P2 .4/TA 2/A4 /VREF+/ VeREF+/ OA1I0
27
P2 .3/TA 1/A3 /VREF-- / V e R E F-- /OA 1 I1/OA1O
26
P3.7/A7/OA1I2
25
P3.6/A6/OA0I2
24
P3 .5 /UCA 0RXD /UCA 0 SOMI
23
P3 .4 /UCA 0TXD /UCA 0SIMO
22
P4.7/TBCLK
21
P4.6/TBOUTH/A15/OA 1I3
P4 .3 /T B0 / A12 /O A 0 O
P4 .4 /T B1 / A13 /O A 1 O
P4.5/TB2/A 14/OA0I3
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5
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
MSP430x22x2 functional block diagram
VCC VSS
System+
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
JTAG
Interface
XOUT
MCLK
ACLK
SMCLK
MAB
MDB
Flash
32kB
16kB
8kB
Brownout
Protection
RST/NMI
XIN
Basic Clock
Spy--Bi Wire
NOTE: See port schematics section for detailed I/O information.
MSP430x22x4 functional block diagram
VCC VSS
System+
16MHz
CPU
incl. 16
Registers
XOUT
MCLK
ACLK
SMCLK
MAB
MDB
Flash
32kB
16kB
8kB
XIN
Basic Clock
RAM
1kB
512B
512B
RAM
1kB
512B
512B
ADC10
1 0 --B i t
12
Channels,
Autoscan,
DTC
Watchdog
WDT+
15/16--Bit
ADC10
1 0 --B i t
12
Channels,
Autoscan,
DTC
Time r_A3
3CC
Registers
OA0, OA1
2OpAmps
P1.x/P2.x
2x8
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull--up/down
resistors
Time r_B3
3CC
Registers,
Shadow
Reg
P1.x/P2.x
2x8
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull--up/down
resistors
P3.x/P4.x
2x8
Ports P3/P4
2x8 I/O
pull--up/down
resistors
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
P3.x/P4.x
2x8
Ports P3/P4
2x8 I/O
pull--up/down
resistors
Emulation
(2BP)
JTAG
Interface
Spy--Bi Wire
Brownout
Protection
RST/NMI
Watchdog
WDT+
15/16--Bit
Time r_A3
3CC
Registers
Time r_B3
3CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
NOTE: See port schematics section for detailed I/O information.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x2, MSP430x22x4
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
Terminal Functions, MSP430x22x2
TERMINAL
NAME
P1.0/TACLK/
ADC10CLK
P1.1/TA0 32 30 I/O General-purpose digital I/O pin
P1.2/TA1 33 31 I/O General-purpose digital I/O pin
P1.3/TA2 34 32 I/O General-purpose digital I/O pin
P1.4/SMCLK/
TCK
P1.5/TA0/
TMS
P1.6/TA1/
TDI/TCLK
P1.7/TA2/
TDO/TDI
P2.0/ACLK/A0 8 6 I/O General-purpose digital I/O pin / ACLK output
P2.1/TAINCLK/SMCLK/A1 9 7 I/O General-purpose digital I/O pin
P2.2/TA0/A2 10 8 I/O General-purpose digital I/O pin
P2.3/TA1/
A3/V
P2.4/TA2/
A4/V
P2.5/
R
XIN/P2.6 6 3 I/O Input terminal of crystal oscillator
XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator
P3.0/
UCB0STE/UCA0CLK/
A5
P3.1/
UCB0SIMO/UCB0SDA
P3.2/
UCB0SOMI/UCB0SCL
P3.3/
UCB0CLK/UCA0STE
P3.4/
UCA0TXD/UCA0SIMO
†
REF--/VeREF--
REF+/VeREF+
OSC
DA RHA
NO. NO.
31 29 I/O General-purpose digital I/O pin
35 33 I/O General-purpose digital I/O pin / SMCLK signal output
36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output
37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output
38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
29 27 I/O General-purpose digital I/O pin
30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
3 40 I/O General-purpose digital I/O pin
11 9 I/O General-purpose digital I/O pin
12 10 I/O General-purpose digital I/O pin
13 11 I/O General-purpose digital I/O pin
14 12 I/O General-purpose digital I/O pin
25 23 I/O General-purpose digital I/O pin
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
Timer_A, capture: CCI1A input, compare: OUT1 output
Timer_A, capture: CCI2A input, compare: OUT2 output
Test Clock input for device programming and test
Test Mode Select input for device programming and test
Test Data Input or Test Clock Input for programming and test
Test Data Output or Test Data Input for programming and test
ADC10, analog input A0
Timer_A, clock signal at INCLK, SMCLK signal output
ADC10, analog input A1
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
ADC10, analog input A4 / positive reference voltage output/input
Input for external DCO resistor to define DCO frequency
General-purpose digital I/O pin
General-purpose digital I/O pin
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
USCI_B0 slave in/master out in SPI mode, SDA I
USCI_B0 slave out/master in in SPI mode, SCL I
USCI_B0 clock input/output / USCI_A0 slave transmit enable
USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode
DESCRIPTION
2
CdatainI2C mode
2
C clock in I2C mode
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7
MSP430x22x2, MSP430x22x4
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
Terminal Functions, MSP430x22x2 (Continued)
TERMINAL
NAME
P3.5/
UCA0RXD/UCA0SOMI
P3.6/A6 27 25 I/O General-purpose digital I/O pin
P3.7/A7 28 26 I/O General-purpose digital I/O pin
P4.0/TB0 17 15 I/O General-purpose digital I/O pin
P4.1/TB1 18 16 I/O General-purpose digital I/O pin
P4.2/TB2 19 17 I/O General-purpose digital I/O pin
P4.3/TB0/
A12
P4.4/TB1
A13
P4.5/TB2
A14
P4.6/TBOUTH
A15
P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin
RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input
TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is
DV
CC
AV
CC
DV
SS
AV
SS
QFN Pad NA Package
†
TDO or TDI is selected via JTAG instruction.
NOTE: IfXOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
DA RHA
NO. NO.
26 24 I/O General-purpose digital I/O pin
20 18 I/O General-purpose digital I/O pin
21 19 I/O General-purpose digital I/O pin
22 20 I/O General-purpose digital I/O pin
23 21 I/O General-purpose digital I/O pin
2 38, 39 Digital supply voltage
16 14 Analog supply voltage
4 1, 4 Digital ground reference
15 13 Analog ground reference
Pad
I/O
USCI_A0 receive data input in UART mode, slave out/master in in SPI mode
ADC10 analog input A6
ADC10 analog input A7
Timer_B, capture: CCI0A input, compare: OUT0 output
Timer_B, capture: CCI1A input, compare: OUT1 output
Timer_B, capture: CCI2A input, compare: OUT2 output
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
Timer_B, compare: OUT2 output
ADC10 analog input A14
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
Timer_B, clock signal TBCLK input
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
NA QFN package pad; connection to DVSSrecommended.
DESCRIPTION
8
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MSP430x22x2, MSP430x22x4
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
Terminal Functions, MSP430x22x4
TERMINAL
NAME
P1.0/TACLK/
ADC10CLK
P1.1/TA0 32 30 I/O General-purpose digital I/O pin
P1.2/TA1 33 31 I/O General-purpose digital I/O pin
P1.3/TA2 34 32 I/O General-purpose digital I/O pin
P1.4/SMCLK/
TCK
P1.5/TA0/
TMS
P1.6/TA1/
TDI/TCLK
P1.7/TA2/
TDO/TDI
P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output
P2.1/TAINCLK/SMCLK/
A1/OA0O
P2.2/TA0/
A2/OA0I1
P2.3/TA1/
A3/V
/OA1I1/OA1O
P2.4/TA2/
A4/V
/OA1I0
P2.5/
R
XIN/P2.6 6 3 I/O Input terminal of crystal oscillator
XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator
P3.0/
UCB0STE/UCA0CLK/
A5
P3.1/
UCB0SIMO/UCB0SDA
P3.2/
UCB01SOMI/UCB0SCL
P3.3/
UCB0CLK/UCA0STE
P3.4/
UCA0TXD/UCA0SIMO
†
REF--/VeREF--
REF+/VeREF+
OSC
DA RHA
NO. NO.
31 29 I/O General-purpose digital I/O pin
35 33 I/O General-purpose digital I/O pin / SMCLK signal output
36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output
37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output
38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK
10 8 I/O General-purpose digital I/O pin
29 27 I/O General-purpose digital I/O pin
30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
3 40 I/O General-purpose digital I/O pin
11 9 I/O General-purpose digital I/O pin
12 10 I/O General-purpose digital I/O pin
13 11 I/O General-purpose digital I/O pin
14 12 I/O General-purpose digital I/O pin
25 23 I/O General-purpose digital I/O pin
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
Timer_A, capture: CCI1A input, compare: OUT1 output
Timer_A, capture: CCI2A input, compare: OUT2 output
Test Clock input for device programming and test
Test Mode Select input for device programming and test
Test Data Input or Test Clock Input for programming and test
Test Data Output or Test Data Input for programming and test
ADC10, analog input A0 / OA0, analog input I0
SMCLK signal output
ADC10, analog input A1 / OA0, analog output
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2 / OA0, analog input I1
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
OA1, analog input I1 / OA1, analog output
ADC10, analog input A4 / positive reference voltage output/input
OA1, analog input I0
Input for external DCO resistor to define DCO frequency
General-purpose digital I/O pin
General-purpose digital I/O pin
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
USCI_B0 slave in/master out in SPI mode, SDA I
USCI_B0 slave out/master in in SPI mode, SCL I
USCI_B0 clock input/output / USCI_A0 slave transmit enable
USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode
DESCRIPTION
2
CdatainI2C mode
2
C clock in I2C mode
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9
MSP430x22x2, MSP430x22x4
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
Terminal Functions, MSP430x22x4 (Continued)
TERMINAL
NAME
P3.5/
UCA0RXD/UCA0SOMI
P3.6/A6/OA0I2 27 25 I/O General-purpose digital I/O pin
P3.7/A7/OA1I2 28 26 I/O General-purpose digital I/O pin
P4.0/TB0 17 15 I/O General-purpose digital I/O pin
P4.1/TB1 18 16 I/O General-purpose digital I/O pin
P4.2/TB2 19 17 I/O General-purpose digital I/O pin
P4.3/TB0/
A12/OA0O
P4.4/TB1
A13/OA1O
P4.5/TB2
A14/OA0I3
P4.6/TBOUTH
A15/OA1I3
P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin
RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input
TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is
DV
CC
AV
CC
DV
SS
AV
SS
QFN Pad NA Package
†
TDO or TDI is selected via JTAG instruction.
NOTE: IfXOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
DA RHA
NO. NO.
26 24 I/O General-purpose digital I/O pin
20 18 I/O General-purpose digital I/O pin
21 19 I/O General-purpose digital I/O pin
22 20 I/O General-purpose digital I/O pin
23 21 I/O General-purpose digital I/O pin
2 38, 39 Digital supply voltage
16 14 Analog supply voltage
4 1, 4 Digital ground reference
15 13 Analog ground reference
Pad
I/O
USCI_A0 receive data input in UART mode, slave out/master in in SPI mode
ADC10 analog input A6 / OA0 analog input I2
ADC10 analog input A7 / OA1 analog input I2
Timer_B, capture: CCI0A input, compare: OUT0 output
Timer_B, capture: CCI1A input, compare: OUT1 output
Timer_B, capture: CCI2A input, compare: OUT2 output
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12 / OA0 analog output
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13 / OA1 analog output
Timer_B, compare: OUT2 output
ADC10 analog input A14 / OA0 analog input I3
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15 / OA1 analog input I3
Timer_B, clock signal TBCLK input
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
NA QFN package pad connection to DVSSrecommended.
DESCRIPTION
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ----> (TOS), R8---- > PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register F
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)----> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) ----> M(TONI)
Absolute F F MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)
Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)
Indirect
autoincrement
Immediate F MOV #X,TONI MOV #45,TONI #45 ----> M(TONI)
NOTE: S = source D = destination
F
F MOV @Rn+,Rm MOV @R10+,R11
MOV Rs,Rd MOV R10,R11 R10 ----> R11
M(R10) -- --> R11
R10 + 2----> R10
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11
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
-- All clocks are active
D Low-power mode 0 (LPM0)
-- CPU is disabled
ACLK and SMCLK remain active
MCLK is disabled
D Low-power mode 1 (LPM1)
-- CPU is disabled
ACLK and SMCLK remain active
MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2)
-- CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3)
-- CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4)
-- CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
NMI
Oscillator fault
Flash memory access violation
Timer_B3 TBCCR0 CCIFG (see Note 3) maskable 0FFFAh 29
Timer_B3
Watchdog Timer WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
Timer_A3
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC10 ADC10IFG (see Note 3) maskable 0FFEAh 21
I/O Port P2
(eight flags)
I/O Port P1
(eight flags)
(see Note 5) 0FFDEh 15
(see Note 6) 0FFDCh ... 0FFC0h 14 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module.
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
5. This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
TAIFG (see Notes 2 and 3)
UCA0RXIFG, UCB0RXIFG
UCA0TXIFG, UCB0TXIFG
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 2 and 3)
TACCR1 CCIFG.
TACCR2 CCIFG
(see Notes 2)
(see Notes 2)
P2IFG.0toP2IFG.7
(see Notes 2 and 3)
P1IFG.0toP1IFG.7
(see Notes 2 and 3)
Reset 0FFFEh 31, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
maskable 0FFF8h 28
maskable 0FFF0h 24
maskable 0FFEEh 23
maskable 0FFECh 22
maskable 0FFE6h 19
maskable 0FFE4h 18
0FFFCh 30
0FFF6h 27
0FFE8h 20
0FFE2h 17
0FFE0h 16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address76543210
00h
ACCVIE NMIIE OFIE WDTIE
rw--0 rw--0 rw--0 rw--0
WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured
OFIE Oscillator fault enable
NMIIE (Non)-maskable interrupt enable
ACCVIE Flash access violation i nterrupt enable
Address76543210
01h
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
in interval timer mode.
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt flag register 1 and 2
Address76543210
02h
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw--0 rw--(0) rw--(1) rw--1 rw --(0)
WDTIFG Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST
PORIFG Power-On interrupt flag. Set on V
NMIIFG Set via RST
Address76543210
03h
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
Legend rw:
rw-0,1:
rw-(0,1):
Reset on V
power up or a reset condition at RST/NMI pin in reset mode.
CC
/NMI pin in reset mode. Reset on VCCpower up.
power up.
CC
/NMI-pin
UCB0
TXIFG
rw--1 rw--0 rw--1 rw--0
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
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15
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
memory organization
MSP430F223x MSP430F225x MSP430F227x
Memory
Main: interrupt vector
Main: code memory
Information memory Size
Boot memory Size
RAM Size 512 Byte
Peripherals 16-bit
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the application report, Features of the
MSP430 Bootstrap Loader, TI literature number SLAA089.
Size
Flash
Flash
Flash
ROM
8-bit
8-bit SFR
8KB Flash
0FFFFh--0FFC0h
0FFFFh--0E000h
256 Byte
010FFh--01000h
1KB
0FFFh--0C00h
03FFh--0200h
01FFh--0100h
0FFh--010h
0Fh--00h
16KB Flash
0FFFFh--0FFC0h
0FFFFh--0C000h
256 Byte
010FFh--01000h
1KB
0FFFh--0C00h
512 Byte
03FFh--0200h
01FFh--0100h
0FFh--010h
0Fh--00h
32KB Flash
0FFFFh--0FFC0h
0FFFFh--08000h
256 Byte
010FFh--01000h
1KB
0FFFh--0C00h
1KB
05FFh--0200h
01FFh--0100h
0FFh--010h
0Fh--00h
BSL Function DA Package Pins RHA Package Pins
Data transmit 32 - P1.1 30 - P1.1
Data receive 10 - P2.2 8-P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0--n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
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MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO),
and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 μs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very
low power LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency Calibration Register Size Address
1MHz
8MHz
12 MHz
16 MHz
CALBC1_1MHZ byte
CALDCO_1MHZ byte
CALBC1_8MHZ byte
CALDCO_8MHZ byte
CALBC1_12MHZ byte
CALDCO_12MHZ byte
CALBC1_16MHZ byte
CALDCO_16MHZ byte
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown r esistor.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
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17
MSP430x22x2, MSP430x22x4
A
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
DA RHA DA RHA
31 - P1.0 29 - P1.0 TACLK TAC L K
9-P2.1 7-P2.1 TAINCLK INCLK
32 - P1.1 30 - P1.1 TA0 CCI0A
10 - P2.2 8-P2.2 TA 0 CCI0B
33 - P1.2 31 - P1.2 TA1 CCI1A
29 - P2.3 27 - P2.3 TA1 CCI1B
34 - P1.3 32 - P1.3 TA2 CCI2A
Device
Input Signal
ACLK ACLK
SMCLK SMCLK
V
SS
V
CC
V
SS
V
CC
ACLK (internal) CCI2B
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
GND
V
CC
Module
Block
Timer N
CCR0 TA0
CCR1 TA1
CCR2 TA2
Module
Output Signal
Output
Pin Number
32 - P1.1 30 - P1.1
10 - P2.2 8-P2.2
36 - P1.5 34 - P1.5
33 - P1.2 31 - P1.2
29 - P2.3 27 - P2.3
37 - P1.6 35 - P1.6
34 - P1.3 32 - P1.3
30 - P2.4 28 - P2.4
38 - P1.7 36 - P1.7
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MSP430x22x2, MSP430x22x4
A
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input
Pin Number
DA RHA DA RHA
24 - P4.7 22 - P4.7 TBCLK TBCLK
24 - P4.7 22 - P4.7 TBCLK INCLK
17 - P4.0 15 - P4.0 TB0 CCI0A
20 - P4.3 18 - P4.3 TB0 CCI0B
18 - P4.1 16 - P4.1 TB1 CCI1A
21 - P4.4 19 - P4.4 TB1 CCI1B
19 - P4.2 17 - P4.2 TB2 CCI2A
Device
Input Signal
ACLK ACLK
SMCLK SMCLK
V
SS
V
CC
V
SS
V
CC
ACLK (internal) CCI2B
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
GND
V
CC
Module
Block
Timer N
CCR0 TB0
CCR1 TB1
CCR2 TB2
Module
Output Signal
Output
Pin Number
17 - P4.0 15 - P4.0
20 - P4.3 18 - P4.3
18 - P4.1 16 - P4.1
21 - P4.4 19 - P4.4
19 - P4.2 17 - P4.2
22 - P4.5 20 - P4.5
universal serial communications interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I
2
C and asynchronous communication protocols such as UART,
2
C.
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19
MSP430x22x2, MSP430x22x4
DeviceInputSignalModuleInputNam
e
DeviceInputSignalModuleInputNam
e
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
operational amplifier OA (MSP430x22x4 only)
The MSP430x22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA0 Signal Connections
Analog Input
Pin Number
DA RHA
8-A0 6-A0 OA0I0 OAxI0
10 - A2 8-A2 OA0I1 OA0I1
10 - A2 8-A2 OA0I1 OAxI1
27 - A6 25 - A6 OA0I2 OAxIA
22 - A14 20 - A14 OA0I3 OAxIB
Device Input Signal Module Input Name
OA1 Signal Connections
Analog Input
Pin Number
DA RHA
30 - A4 28 - A4 OA1I0 OAxI0
10 - A2 8-A2 OA0I1 OA0I1
29 - A3 27 - A3 OA1I1 OAxI1
28 - A7 26 - A7 OA1I2 OAxIA
23 - A15 21 - A15 OA1I3 OAxIB
Device Input Signal Module Input Name
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
ADCcontrolregister0
ADC10CTL0
1B0
h
ADC10 ADC data transfer start address
Timer_B Capture/compare register
Timer_A Capture/compare register
Flash Memory Flash control 3
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
OA1 (MSP430x22x4 only) Operational Amplifier 1 control register 1
OA0 (MSP430x22x4 only) Operational Amplifier 0 control register 1
USCI_B0 USCI_B0 transmit buffer
USCI_A0 USCI_A0 transmit buffer
PERIPHERALS WITH WORD ACCESS
ADC memory
ADC control register 1
ADC control register 0
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
Capture/compare register
Capture/compare register
Timer_B register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_B control
Timer_B interrupt vector
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash control 2
Flash control 1
PERIPHERALS WITH BYTE ACCESS
Operational Amplifier 1 control register 1
Operational Amplifier 0 control register 1
USCI_B0 receive buffer
USCI_B0 status
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TAC T L
TAI V
FCTL3
FCTL2
FCTL1
OA1CTL1
OA1CTL0
OA0CTL1
OA0CTL0
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
1BCh
1B4h
1B2h
1B0h
04Ah
04Bh
049h
048h
0196h
0194h
0192h
0190h
0186h
0184h
0182h
0180h
011Eh
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0C3h
0C2h
0C1h
0C0h
06Fh
06Eh
06Dh
06Bh
06Ah
069h
068h
011Ah
0118h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
PERIPHERALS WITH BYTE ACCESS (continued)
Basic Clock System+ Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P4 Port P4 resistor enable
Port P4 selection
Port P4 direction
Port P4 output
Port P4 input
Port P3 Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
Port P2 Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
Port P1 Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
Special Function SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P4REN
P4SEL
P4DIR
P4OUT
P4IN
P3REN
P3SEL
P3DIR
P3OUT
P3IN
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
IFG2
IFG1
IE2
IE1
053h
058h
057h
056h
011h
01Fh
01Eh
01Dh
01Ch
010h
01Bh
01Ah
019h
018h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
absolute maximum ratings (see Note 1)
Voltage applied at VCCto V
SS
Voltage applied to any pin (see Note 2) --0.3 V to V
Diode current at any device terminal ±2mA.......................................................
Storage temperature range, T
Storage temperature range, T
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Expos ure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(unprogrammed device, see Note 3) --55°C to 150°C..................
stg
(programmed device, see Note 3) --40°C to 105°C....................
stg
. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
SS
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage during program execution, V
Supply voltage during program/erase flash memory, V
Supply voltage, V
Operatingfree-air temperature, T
Processor frequency f
(see Notes 1, 2 and Figure 1)
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
SS
A
(maximum MCLK frequency)
SYSTEM
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
CC
CC
I version -- 4 0 85
T version -- 4 0 105
VCC=1.8V,
Duty cycle = 50% ±10%
VCC=2.7V,
Duty cycle = 50% ±10%
VCC≥ 3.3 V,
Duty cycle = 50% ±10%
1.8 3.6 V
2.2 3.6 V
dc 4.15
dc 12
dc 16
--0.3 V to 4.1 V......................................................
+0.3 V........................................
CC
0 V
MHz
°C
16 MHz
12 MHz
7.5 MHz
System Frequency -- MHz
4.15 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCCof 2.2 V.
Supply Voltage -- V
Legend:
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Figure 1. Operating Area
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430x22x2, MSP430x22x4
A
(
AM)
Activemode(AM
)
A
A
A
(
AM)
Activemode(AM
)
A
A
f
,
A
(
AM)
f
A
CLK
=32,768Hz/8=4,096Hz
g
Activemode(AM
)
Programexecutesinflas
h
ADIVMxDIVSxDIVAx11,
A
(
AM)
f
f
Activemode(AM
)
Programexecutesinflas
h
A
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
active mode supply current (into DVCC+AVCC) excluding external current (see Notes 1 and 2)
I
AM, 1MHz
I
AM, 1MHz
I
AM, 4kHz
I
AM,100kHz
PARAMETER TEST CONDITIONS T
ctive mode
current (1 MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768 Hz,
ACLK
Program executes in flash,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ctive mode
current (1 MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768 Hz,
ACLK
Program executes in RAM,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ctive mode
current (4 kHz)
ctive mode
current (100 kHz)
f
MCLK=fSMCLK
=32,768 Hz/8=4,096 Hz
f
=0Hz,
DCO
Pro
ram executes inflash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
f
MCLK=fSMCLK=fDCO(0, 0)
=0Hz,
ACLK
Program executes in
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
=
,
,
-40--85°C 2.2 V 5 9
105°C 2.2 V 18
-40--85°C 3V 6 10
105°C 3V 20
lash,
≈ 100 kHz,
,
-40--85°C 2.2 V 60 85
105°C 2.2 V 95
-40--85°C 3V 72 95
105°C 3V 105
A
VCC MIN TYP MAX UNIT
2.2 V 270 390
μ
3V 390 550
2.2 V 240
μ
3V 340
μ
μ
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- active mode supply current (into DVCC+AVCC)
8.0
f
=16MHz
7.0
6.0
5.0
4.0
3.0
Active Mode Current -- mA
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC-- Supply Voltage -- V
DCO
f
DCO
f
f
DCO
DCO
=12MHz
=8MHz
=1MHz
Figure 2. Active Mode Current vs VCC,TA=25°C
5.0
TA=85°C
4.0
3.0
VCC=3V
2.0
Active Mode Current -- mA
1.0
VCC=2.2V
0.0
0.0 4.0 8.0 12.0 16.0
f
-- DCO Frequency -- MHz
DCO
TA=85°C
TA=25°C
TA=25°C
Figure 3. Active Mode Current vs DCO Frequency
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430x22x2, MSP430x22x4
A
A
f
A
CLK
f
ACL
K
=0H
z
A
f
1MH
V
A
A
_
V
V
L
(
f
f
f
0MH
f
3(LPM3)curren
t
f
ACL
K
=32,768Hz
A
V
V
L
(
)
f
f
f
0MH
f
f
(
VLO)
3curren
t,(LPM3
)
f
ACL
K
frominternalLFoscillator(VLO)
A
V
f
f
f
0MH
f
f
ACL
K
=0H
z
V
/3V
AseeNote5
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into DVCC+AVCC) excluding external current (see Notes 1 and 2)
I
LPM0, 1MHz
I
LPM0, 100kHz
I
LPM2
I
LPM3,LFXT1
I
LPM3,VLO
I
LPM4
PARAMETER TEST CONDITIONS T
f
=0MHz,
MCLK
Low-power mode
0 (LPM0) current,
seeNote3
f
SMCLK=fDCO
f
= 32,768 Hz,
ACLK
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
f
=0MHz,
MCLK
Low-power mode
0 (LPM0) current,
seeNote3
f
SMCLK=fDCO(0, 0)
=0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
≈ 100 kHz,
,
OSCOFF = 1
Low-power mode
2 (LPM2) current,
seeNote4
f
MCLK=fSMCLK
=
DCO
f
= 32,768 Hz,
ACLK
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
=0MHz,
z,
LBC1_1MHZ,
-40--85°C
105°C
-40--85°C
105°C
-40°C 0.7 1.4
25°C
ow-power mode
3
LPM3)current,
seeNote4
=
DCO
,
=
MCLK
= 32,768 Hz,
SMCLK
,
=
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
z,
85°C
105°C 5 10
-40°C 0.9 1.5
25°C
85°C
105°C 6 12
-40°C 0.4 1.0
25°C
ow-power mode
3 current,
LPM3
seeNote4
=
DCO
MCLK
=
SMCLK
=
z,
rom internal LF oscillator
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
85°C
105°C 4.5 9
,
,
-40°C 0.5 1.2
25°C
85°C
105°C 5.5 11
-40°C 0.1 0.5
25°C
85°C
105°C 4.5 9
Low-power mode
4 (LPM4) current,
seeNote5
=
DCO
MCLK
=0Hz,
=
,
SMCLK
=
z,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
A
VCC MIN TYP MAX UNIT
2.2 V 75 90
3V 90 120
2.2 V 37 48
3V 41 65
22 29
2.2
31
25 32
3
34
2.2
3
2.2
3
2.2
0.7 1.4
2.4 3.3
0.9 1.5
2.6 3.8
0.5 1.0
1.8 2.9
0.6 1.2
2.1 3.3
0.1 0.5
1.5 3.0
μ
μ
μ
μ
μ
μ
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x22x2, MSP430x22x4
V
IT+
Positivegoinginputthresholdvoltag
e
V
V
I
T
Negativegoinginputthresholdvoltag
e
V
V
MIXED SIGNAL MICROCONTROLLER
SLAS504B -- JULY 2006 -- REVISED JULY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports P1, P2, P3, P4, and RST/NMI
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
IT+
V
IT--
--
V
hys
R
Pull
C
I
Positive-going input threshold voltage
Negative-going input threshold voltage
Input voltage hysteresis (V
Pullup/pulldown resistor
IT+
-- V
IT--
)
For pullup: VIN=VSS;
For pulldown: V
Input capacitance VIN=VSSor V
IN=VCC
CC
inputs -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Port P1, P2: P1.x to P2.x, External
t
(int)
External interrupt timing
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
shorter than t
(int)
.
trigger pulse width to set interrupt
flag (see Note 1)
0.45 0.75 V
2.2 V 1.00 1.65
3V 1.35 2.25
0.25 0.55 V
2.2 V 0.55 1.20
3V 0.75 1.65
2.2 V 0.2 1.0
3V 0.3 1.0
20 35 50 kΩ
5 pF
2.2 V/3 V 20 ns
is met. It may be set even with trigger signals
(int)
CC
CC
leakage current -- Ports P1, P2, P3 and P4
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
lkg(Px.x)
NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.
High-impedance leakage current See Notes 1 and 2 2.2 V/3 V ±50 nA
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
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