Ultralow Power Consumption (Standby
Mode Down to 0.1 mA)
D
Five Power-Saving Modes
D
Wakeup From Standby Mode in 6 ms
D
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
D
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
D
Integrated LCD Driver for up to 84
Segments
description
The T exas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several
devices which feature different sets of modules targeted to various applications. The microcontroller is designed
to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated
registers on the CPU, and a constant generator, the MSP430 achieves maximum code ef ficiency . The digitallycontrolled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode
to active mode in less than 6 ms.
DD
D
DD
D
PG Package
(TOP VIEW)
Integrated 12+2 Bit A/D Converter
Family Members Include:
– MSP430P325, 16KB OTP, 512 Byte RAM
EPROM Version Available for Prototyping:
PMS430E325
Serial Onboard Programming
Programmable Code Protection by Security
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
P0.5
RST/NMI
P0.6
P0.7
TCK
R33
TMS
TDI/VPP
R23
R13
TDO/TDI
COM3
COM2
S0
S1
R03
COM1
51
COM0
50
S20/O20/CMPI
49
S19/O19
48
S18/O18
47
S17/O17
46
S16/O16
45
S15/O15
44
S14/O14
43
S13/O13
42
S12/O12
41
S1 1/O11
40
S10/O10
39
S9/O9
38
S8/O8
37
S7/O7
36
S6/O6
35
S5/O5
34
S4/O4
33
S3/O3
S2/O2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
MSP430P325
40°C to 85°C
MSP430P325IPG
MSP430P325IPM
MSP430P325IFN
25°C
PMS430E325FZ
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
description (continued)
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated
12+2 bit A/D converter with six multiplexed inputs.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
°
–
°
°
functional block diagram
PLASTIC
64-PIN QFP
(PG)
PLASTIC
64-PIN QFP
(PM)
———
PLASTIC
68-PIN PLCC
(FN)
CERAMIC
68-PIN JLCC
(FZ)
—
TDI/VPP
TDO/TDI
TMS
TCK
Bus
Conv
RST/NMI
Power-on-
Reset
MAB, 4 Bit
MCB
MDB, 8 Bit
Timer/Port
Applications:
A/D Conv.
Timer, O/P
6
8 b Timer/
Counter
Serial Protocol
Support
Basic
Timer1
f
CMPI
LCD
TXD
RXD
8 I/O’s, All With
1, 2, 3, 4 MUX
XIN Xout/TCLKXBUFP0.0P0.7
Oscillator
FLL
System Clock
CPU
Incl. 16 Reg.
Test
JTAG
ACLK
MCLK
MAB, 16 Bit
MDB, 16 Bit
8/16 kB ROM
16 kB OTP
’C’: ROM
’P’: OTP
ADC
12 + 2 Bit
6 Channels
Current S.
6
256/512 B
RAM
Watchdog
Timer
15/16 Bit
I/O Port
Interr. Cap.
3 Int. Vectors
LCD
84 Segments
Com0–3
S0–19/O2–19
S20/O20CMPI
2
A0–5
SVCC
Rext
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP0.0–5
CIN
R33R13
R23
R03
I/O
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
Terminal Functions
TERMINAL
NAMENO.
AV
CC
AV
SS
A061IAnalog-to-digital converter input port 0 or digital input port 0
A162IAnalog-to-digital converter input port 1 or digital input port 1
A2–A55–8IAnalog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5
CIN11IInput used as enable of counter TPCNT1 – Timer/Port
COM0–351–54OCommon outputs, used for LCD backplanes – LCD
DV
CC
DV
SS
P0.018I/OGeneral-purpose digital I/O
P0.1/RXD19I/OGeneral-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter
P0.2/TXD20I/OGeneral-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter
P0.3–P0.721–25I/OFive general-purpose digital I/Os, bit 3 to bit 7
Rext4IProgramming resistor input of internal current source
RST/NMI59IReset input or non-maskable interrupt input
R0329IInput of fourth positive analog LCD level (V4) – LCD
R1328IInput of third positive analog LCD level (V3) – LCD
R2327IInput of second positive analog LCD level (V2) – LCD
R3326OOutput of first positive analog LCD level (V1) – LCD
SV
CC
S030OSegment line S0 – LCD
S131OSegment line S1 – LCD
S2–S5/O2–O532–35OSegment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD
S20/O20/CMPI50I/OSegment line S20 can be used as comparator input port CMPI – Timer/Port
S6–S9/O6–O936–39OSegment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD
S10–S13/O10–O1340–43OSegment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD
S14–S17/O14–O1744–47OSegment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD
S18-S19/O18-O1948, 49OSegment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD
TCK58ITest clock, clock input terminal for device programming and test
TDO/TDI55I/OTest data output, data output terminal or data input during programming
TDI/VPP56ITest data input, data input terminal or input of programming voltage
TMS57ITest mode select, input terminal for device programming and test
TP0.012OGeneral-purpose 3-state digital output port, bit 0 – Timer/Port
TP0.113OGeneral-purpose 3-state digital output port, bit 1 – Timer/Port
TP0.214OGeneral-purpose 3-state digital output port, bit 2 – Timer/Port
TP0.315OGeneral-purpose 3-state digital output port, bit 3 – Timer/Port
TP0.416OGeneral-purpose 3-state digital output port, bit 4 – Timer/Port
TP0.517I/OGeneral-purpose digital input/output port, bit 5 – Timer/Port
XBUF60OClock signal output of system clock MCLK or crystal clock ACLK
Xin9IInput terminal of crystal oscillator
Xout/TCLK10I/OOutput terminal of crystal oscillator or test clock input
1Positive analog supply voltage
63Analog ground reference
2Positive digital supply voltage
64Digital ground reference
3Switched AVCC to analog-to-digital converter
MSP430P325
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3
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
short-form description
processing unit
The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and it is
distinguished by ease of programming. All operations other than program-flow instructions are consequently
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.
Program Counter
CPU
Sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor frequency.
Four of the registers are reserved for special
use as a program counter, a stack pointer , a status
register, and a constant generator . The remaining
registers are available as general-purpose
registers.
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory
General-Purpose RegisterR14
manipulation.
General-Purpose Register
instruction set
The instruction set for this register-register architecture provides a powerful and easy-to-use assembler
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destinatione.g. ADD R4, R5R4 + R5 → R5
Single operands, destination onlye.g. CALL R8PC → (TOS), R8 → PC
Relative jump, un-/conditionale.g. JNEJump-on equal bit = 0
Each instruction that operates on word and byte data is identified by the suffix B.
Examples:Instructions for word operationInstructions for byte operation
MOVEDE, TONIMOV.BEDE, TONI
ADD#235h, &MEMADD.B#35h, &MEM
PUSHR5PUSH.BR5
SWPBR5—
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
indirect
addressing, ideally suited for computed branches and
The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The software can configure five operating modes:
D
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D
Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D
Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D
Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D
Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.
D
Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
The most general bits that influence current consumption and support fast turnon from low-power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
159870
Reserved For Future
Enhancements
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
Basic Timer1BTIFGMaskable0FFE2h1
I/O port 0, P0.2–7
NOTES: 1. Multiple source flags
2. Timer/Port interrupt flags are located in the T/P registers
3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.
VSCG1SCG0OscOffCPUOffGIENZC
rw-0
WDTIFG
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 4)
RC1FG, RC2FG, EN1FG
P0.27IFG (see Note 1)
(see Note1)
P0.1IFGMaskable0FFF8h12
(see Note 2)
Reset0FFFEh15, highest
Non-maskable,
(Non)-maskable
Maskable0FFE8h4
Maskable0FFE0h0, lowest
0FFFCh14
0FFF6h11
0FFF2h9
0FFF0h8
0FFEEh7
0FFECh6
0FFE6h3
0FFE4h2
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple SW access is
provided with this arrangement.
interrupt enable 1 and 2
Address
0h
76540
321
P0IE.1OFIEWDTIE
rw-0rw-0rw-0rw-0
WDTIE:Watchdog Timer enable signal
OFIE:Oscillator fault enable signal
P0IE.0:Dedicated I/O P0.0
P0IE.1:P0.1 or 8-Bit Timer/Counter, RXD
Address
01hBTIETPIE
76540
rw-0
321
rw-0
ADIE:A/D converter enable signal
TPIE:Timer/Port enable signal
BTIE:Basic Timer1 enable signal
interrupt flag register 1 and 2
Address
02hNMIIFGP0IFG.0
76540
rw-0rw-1rw-0
321
P0IFG.1OFIFGWDTIFG
rw-0rw-0
WDTIFG:Set on overflow or security key violation
or
Reset on VCC power on or reset condition at RST/NMI-pin
OFIFG:Flag set on oscillator fault
P0.0IFG:Dedicated I/O P0.0
P0.1IFG:P0.1 or 8-Bit Timer/Counter, RXD
NMIIFG:Signal at RST
/NMI-pin
P0IE.0
ADIE
rw-0
Address
03hBTIFGADIFG
76540
rw
321
rw-0
BTIFGBasic Timer1 flag
ADFIGAnalog-to-digital converter flag
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7
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
module enable register 1 and 2
Address
04h
Address
05h
Legendrw:
76540321
76540321
rw-0:
memory organization
Bit can be read and written.
Bit can be read and written. It is reset by PUC.
SFR bit not present in device.
MSP430P325
PMS430E325
FFFFh
FFE0h
FFDFh
C000h
Int. Vector
16 kB OTP
or
EPROM
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512B RAM
16b Per.
8b Per.
SFR
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
peripherals
Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all
instructions for memory manipulation.
Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency . The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without any other external components being required.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
oscillator and system clock (continued)
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
D
High frequency in order to react quickly to system hardware requests or events
D
Low frequency in order to minimize current consumption, EMI, etc.
D
Stable frequency for timer applications e.g. real-time clock (RTC)
D
Enable start-stop operation with a minimum of delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency , which is multiplied to achieve the desired
nominal operating range:
f
(system)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO) provides immediate start-up capability together with long term crystal stability . The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the
previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet
the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal
oscillator.
digital I/O
One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output
to the application:
D
All individual I/O bits are programmable independently.
D
Any combination of input, output, and interrupt conditions is possible.
D
Interrupt processing of external events is fully implemented for all eight bits of port P0.
D
Provides read/write access to all registers with all instructions
The six registers are:
= (N+1) × f
crystal)
(
D
Input registerContains information at the pins
D
Output registerContains output information
D
Direction registerControls direction
D
Interrupt flagsIndicates if interrupt(s) are pending
D
Interrupt edge selectContains input signal change necessary for interrupt
D
Interrupt enable Contains interrupt enable pins
All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two
LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three
interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt
event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-Bit Timer/Counter.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
LCD drive
Liquid crystal displays (LCDs) for static, 2-, 3- and 4-MUX operations can be driven directly . The controller LCD
logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module,
not part of data memory . Eight mode and control bits define the operation and current consumption of the LCD
drive. The information for the individual digits can be easily obtained using table programming techniques
combined with the correct addressing mode. The segment information is stored in LCD memory using
instructions for memory manipulation.
The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The
MSP430x32x configuration has four common signal lines and 21 segment lines.
A/D converter
The analog-to-digital converter (ADC) is a cascaded converter type that converts analog signals from VCC to
GND. It is a 12+2 bit converter with a software or automatically-controlled range select. Five inputs can be
selected for analog or digital function. A ratiometric current source can be used on four of the analog pins. The
current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The
conversion is started by setting the start-of-conversion bit (SOC) in the control register and the
end-of-conversions sets the interrupt flag. The analog input signal is sampled starting with SOC during the next
twelve MCLK clock pulses. The power-down bit in the control register controls the operating mode of the ADC
peripheral. The current consumption and operation is stopped when it is set. The system reset PUC sets the
power-down bit.
Basic Timer1
The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support
low current applications. The BTCTL control register contains the flags which control or select the different
operational functions. When the supply voltage is applied or when a reset of the device (RST
watchdog overflow or a watchdog security key violation occurs, and all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.
The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic T imer1 interrupt flag (BTIFG) and the
Basic Timer1 interrupt enable (BTIE) bit.
Watchdog Timer
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog
function is not needed in an application, the module can work as an interval timer, which generates an interrupt
after the selected time interval.
The Watchdog T imer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog T imer control register (WDTCTL), which is an 8-Bit read/write
register. W riting to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated.
the password is read its value is 069h
addition to the Watchdog Timer control bits, two bits included in the WDTCTL configure the NMI pin.
. This minimizes accidental write operations to the WDTCTL register. In
/NMI pin), a
When
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
8-Bit Timer/Counter
The 8-Bit interval timer supports three major functions for the application:
D
Serial communication or data exchange
D
Pulse counting or pulse accumulation
D
Timer
The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-Bit up-counter with preload
register, an 8-Bit control register, an input clock selector, an edge detection (e.g. Start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-Bit
counter.
The 8-Bit counter counts up with an input clock which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.
Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A
write-access to the counter results in loading the content of the preload register into the counter. The software
writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written
immediately after the load of the counter is completed. The enable input enables the count operation. When
the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock
input of the counter.
Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a
data transmission. When this function is activated, the counter starts counting after the start-bit condition is
detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,
which is programmed into the counter. T wo latches are used for input and output data (RXD_FF and TXD_FF)
are clocked by the counter after the programmed timing interval has elapsed.
UART
The serial communication uses software and the 8-Bit Timer/Counter hardware. The hardware supports the
output of the serial data stream, bit-by-bit, with the timing determined by the counter. The software/hardware
interface connects the mixed signal controller to external devices, systems, or networks.
Timer/Port
The Timer/Port module has two 8-Bit counters, an input that triggers one counter , and six 3-state digital outputs.
Both counters have an independent clock-selector for selecting an external signal or one of the internal clocks
(ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate
the counter by selecting one of two external signals. This gate signal sets the interrupt flag, if an external signal
is selected, and the gate stops the counter.
Both timers can be read from and written to by software. The two 8-Bit counters can be cascaded to a 16-bit
counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-Bit
counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate
signal, overflow from the MSB of the cascaded counter).
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Operating free-air temperature range, T
°C
Processor frequency (signal MCLK), f
MH
V
V
3 V/5 V
V
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
absolute maximum ratings
†
Voltage applied at VCC to VSS (see Note 5) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (referenced to VSS) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltage, VCC (MSP430P/E325)2.75.5V
Supply voltage, during programming OTP/EPROM
(AVCC = DVCC = VCC)
Supply voltage, V
p
XTAL frequency, f
Low-level input voltage, VIL (excluding Xin, Xout)V
High-level input voltage, VIH (excluding Xin, Xout)
Low-level input voltage, V
High-level input voltage, V
SS
p
(XTAL)
A
(system)
IL(Xin, Xout)
IH(Xin, Xout)
MSP430P325, PMS430E3252.755.5V
0V
MSP430P325–4085
PMS430E32525
32 768Hz
VCC = 3 VDC2.2
VCC = 5 VDC3.3
VSS+0.8
V
CC
0.2×V
CC
V
CC
CC
=
0.7 V
0.8×V
SS
CC
V
SS
CC
°
z
f(MHz)
3.3
2.2
– Maximum Processor
Frequency – MHz
1.5
Minimum
(system)
f
2.7355.5
VCC – Supply Voltage – V
NOTE: Minimum processor frequency is defined by system clock.
Figure 1. Processor Frequency vs Supply Voltage
VCC (V)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430P325
I
,
P325
A
I
Low power mode, (LPM0, LPM1)
P325
A
I
Low power mode, (LPM2)
A
I
Low power mode, (LPM3)
A
()
V
Positive-going input threshold voltage
V
Negative-going input threshold voltage
V
V
Hysteresis (V
V
)
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
supply current into AVCC+DV
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
(AM)
(CPUOff)
(LPM2)
(LPM3)
I
(LPM4)
NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption in LPM2, LPM3 and LPM4 are
Active mode, A/D conversion in
power-down
p
p
p
Low power mode, (LPM4)
measured with active Basic Timer1 (ACLK selected) and LCD module (f
excluding external current, f
CC
TA = –40°C to 85°C,VCC = 3 V30005000
TA = –40°C to 85°C,VCC = 5 V1000012000
TA = –40°C to 85°C,VCC = 3 V70110
TA = –40°C to 85°C,VCC = 5 V150200
TA = –40°C to 85°C,VCC = 3 V612
TA = –40°C to 85°C,VCC = 5 V1525
TA = –40°C1.52.4
TA = 25°C
TA = 85°C1.62.8
TA = –40°C5.27
TA = 25°C
TA = 85°C47
TA = –40°C0.10.8
TA = 25°C
TA = 85°C0.41.3
system
(LCD)
= 1 MHz
VCC = 3 V
VCC = 5 V
VCC = 3 V/5 V
=1024 Hz, 4 MUX).
1.32
4.26.5
0.10.8
µ
µ
µ
µ
µA
current consumption of active mode versus system frequency
IAM = I
AM[1 MHz]
× f
system
[MHz]
current consumption of active mode versus supply voltage
I
AM
= I
AM[3 V]
+ 200 µA/V × (VCC–3 V)
Schmitt-trigger inputs Port 0, P0.x Timer/Port, CIN, TP 0.5
9. All Timer/Port pins TP0.0 to TP0.5 are Hi-Z. Pins CIN and TP.0 to TP0.5 are connected together during leakage current
measurement. In the leakage measurement the input CIN is included. The input voltage is VSS or VCC.
10. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
11. The input voltage is V
VCC to VSS terminal.
= VSS to VCC , the current source is off, AEN.x bit is normally reset to stop throughput current flowing from
(IN)
Timer/Port: V
(see Note 9)
Port 0: V
(see Note 10)
(S20)
ADC: Ax, x= 0 to 5
(see Note 11)
(TP0.x,CIN
(P0.x)
= VSS to V
CC
)
VCC = 3 V/5 V
CC
CC
CC
CC
VSS+0.4
VSS+1
VSS+0.4
VSS+1
±50nA
±50nA
±50nA
±30nA
input frequency – Port 0: P0.1; Timer/Port: CIN, TP0.5
f
(IN)
or
(H)
output frequency
f
XBUF
t
Xdc
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Input frequencyDCf
(L)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Duty cycle of O/P frequency
P0.x, CIN, TP.5
XBUF,CL = 20 pFf
f
,
= 20 pF,
L
= 3
=
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MCLK
f
XBUF
f
XBUF
3 V300ns
5 V125ns
= 1.1 MHz40%60%
= f
= f
ACLK
ACLK/n
35%65%
50%
(system)
(system)
MHz
MHz
15
MSP430P325
f
N
00 0110 0000
0
f
MH
f
N
0100 0000 FN_4=FN_3=FN_2=0
f
N
0110 0000
1
2xf
(NOM)
MHz
f
N
0100 0000
1
f
N
0110 0000
X
3xf
(NOM)
MHz
f
N
0100 0000
X
f
N
0110 0000 FN_4 =1, FN_3=FN_2=X
4xf
(NOM)
MHz
f
N
0100 0000
X
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
external interrupt timing
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
t
(int)
NOTES: 12. The external signal sets the interrupt flag every time t
conditions to set the flag must be met independently of this timing constraint. Input frequency (t
13. The external signal needs additionally a timing resulting from the maximum input frequency constraint.
RAM
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
RAMh
NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program
CPU halted (see Note 14)1.8V
execution should take place during this supply voltage condition.
DCO
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
f
(NOM)
(NOM)
N
DCO
Sf
DCON
DCO3
DCO26
DCO3
DC26
DCO3
DCO26
DCO3
DCO26
= 1A0h, FN_4=FN_3=FN_2=0VCC = 3 V/5 V1MHz
DCO
=
DCO
= 11
DCO
= 00
DCO
= 11
DCO
= 00
DCO
= 11
DCO
= 00
DCO
= 11
DCO
f
= f
MCLK
NDCO+1
, FN_4=FN_3=FN_2=0VCC = 3 V/5 VA0h1A0h340h
NOM
= S × f
NDCO
Port P0: External trigger signal for the
interrupt flag (see Notes 12 and 13)
is met. It may be set even with trigger signals shorter than t
NOTES: 15. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not
12+2 bit.
16. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.
17. Offset referred to full scale 12/14 bit
18. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
f
TCK frequenc
MH
JTAG/test
()()
()y
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
JTAG
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
(TCK)
R
(TEST)
V
(FB)
I
(FB)
t
(FB)
V
(PP)
I
(PP)
t
(pps)
t
(ppf)
P
n
t
(erase)
NOTES: 19. The TMS and TCK pullup resistors are implemented in all C-, P-, and E-versions.
JTAG/fuse (see Note 20)
EPROM (E) and OTP(P) –
versions only
EPROM (E) versions only
20. Once the JTAG fuse is blown, no further access to the MSP430 JT AG/test feature is possible. The JTAG block switches to by-pass
mode.
21. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.
Pullup resistors on TMS, TCK, TDI
(see Note 19)
Fuse blow voltage, E/P versions
(see Note 21)
Supply current on TDI to blow fuse100mA
Time to blow the fuse1ms
Programming voltage, applied to TDI/VPP1111.513V
Current from programming voltage source70mA
Programming time, single pulse5ms
Programming time, fast algorithm100µs
Number of pulses for successful programming4100Pulses
Data retention TJ < 55°C10year
Erase time wave length 2537 Å at 15 Ws/cm
(UV lamp of 12 mW/ cm2)
Write/Erase cycles1000cycles
y
VCC = 3 VDC5
VCC = 5 VDC10
VCC = 3 V/ 5 V256090kΩ
VCC = 3 V/ 5 V1112V
2
30min
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
vs
OPERATING FREE-AIR TEMPERATURE
1.8
1.5
C
°
1.2
(DCO@ 25 )
0.9
/f
(DCO)
f
0.6
0.3
0
–40–2002040906080
T – Operating Free-Air Temperature – °C
Figure 5
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
1.2
1
0.8
(DCO@ 3 V)
0.6
/f
(DCO)
f
0.4
0.2
0
02
VCC – Supply Voltage – V
46
Figure 6
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical input/output schematics
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
V
CC
(see Note A)
(see Note B)
(see Note B)
(see Note A)
GND
CMOS INPUT (RST/NMI)
V
CC
(see Note A)
(see Note B)
(see Note B)
(see Note A)
V
CC
(see Note A)
(see Note B)
(see Note B)
(see Note A)
GND
CMOS SCHMITT-TRIGGER INPUT (CIN)
GND
I/O WITH SCHMITT-TRIGGER INPUT (P0.x, TP5)CMOS 3-STATE OUTPUT (TP0–4, XBUF)
TDO_Internal
V
CC
60 k TYP
MSP430P/E325: TMS, TCK
NOTES: A. Optional selection of pullup or pulldown resistors with ROM (masked) versions. Anti-parallel diodes are connected between A V
and DVSS.
B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory.
TDO_Control
TDI_Control
TDI_Internal
MSP430P/E325: TDO/TDI
SS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
typical input/output schematics
VC
VD
Control COM0–3
VA
VB
Segment control
VA
VB
Segment control
LCDCTL (LCDM5,6,7)
Data (LCD RAM bits 0–3
or bits 4–7)
LCD OUTPUT (COM0–4, Sn, Sn/On)
NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.
COM 0–3
S0, S1
S2/O2–Sn/On
VPP_ Internal
TDI_ Internal
TDI/VPP
JTAG
Fuse
TDO/TDI_Control
TDO/TDI
JTAG Fuse
TMS
NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage
source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.
B. The TDI/VPP terminal of the ’P325 and ’E325 does not have an internal pullup resistor. An external pulldown resistor is
recommended to avoid a floating node which could increase the current consumption of the device.
C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P325 and ’E325 needs a pullup or a pulldown resistor to avoid
floating a node which could increase the current consumption of the device.
Blow
Control
TDO_ Internal
From/To JTAG_CBT_SIG_REG
Figure 7. MSP430P325/E325: TDI/VPP, TDO/TDI
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity
of the fuse the first time the JT AG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuze check mode occurs with the first negative edge on the TMS pin after power-up or if TMS
is being held low during power-up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
Time TMS Goes Low After POR
TMS
I
TF
I
TDI
Figure 8. Fuse Check Mode Current, MSP430P/E325
Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD
spikes that could cause signal edges on the TMS pin.
Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.
P/E3xx
TDI68k, pulldown
TDO68k, pulldown
TMSOpen
TCKOpen
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
MECHANICAL DATA
PG (R-PQFP-G64) PLASTIC QUAD FLATPACK
52
64
51
1,00
1
18,00 TYP
20,20
19,80
24,40
23,60
0,45
0,25
33
19
0,20
M
32
20
12,00 TYP
18,0014,20
13,80 17,20
0,15 NOM
Gage Plane
2,70 TYP
3,10 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
PINS**
28
44
52
68MO-087AD
MINMAX
0.485
(12,32)(12,57)
A
0.495
BC
0.430
MAXMIN
0.455
(11,56)(10,92)
MINMAX
0.410
(10,41)(10,92)
0.430
0.6300.6100.6300.6550.6950.685
(16,00)(15,49)(16,00)(16,64)(17,65)(17,40)
0.7400.6800.7300.7650.7950.785
(18,79)(17,28)(18,54)(19,43)(20,19)(19,94)
0.9300.9100.9300.9550.9950.985
(23,62)(23,11)(23,62)(24,26)(25,27)(25,02)
4040219/B 03/95
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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