Texas Instruments MSP430P325IFN, MSP430P325IPG, MSP-EVK430B320, MSP430P325IPM, MSP-STK430B320 Datasheet

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

D

Low Supply Voltage Range, 2.7 V – 5.5 V

D

Low Operation Current, 3 mA at 1 MHz,
3 V

D

Ultralow Power Consumption (Standby
Mode Down to 0.1 mA)

D

Five Power-Saving Modes

D

Wakeup From Standby Mode in 6 ms

D

16-Bit RISC Architecture, 300 ns Instruction
Cycle Time

D

Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz

D

Integrated LCD Driver for up to 84
Segments

description

The T exas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several
devices which feature different sets of modules targeted to various applications. The microcontroller is designed
to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated
registers on the CPU, and a constant generator, the MSP430 achieves maximum code ef ficiency . The digitally­controlled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode
to active mode in less than 6 ms.

D
D

D

D
D

D

PG Package

(TOP VIEW)

Integrated 12+2 Bit A/D Converter
Family Members Include:

– MSP430P325, 16KB OTP, 512 Byte RAM
EPROM Version Available for Prototyping:

PMS430E325
Serial Onboard Programming
Programmable Code Protection by Security

Fuse
Avaliable in 64 Pin Quad Flatpack (QFP),

68 Pin Plastic J-Leaded Chip Carrier
(PLCC), 68 Pin J-Leaded Ceramic Chip
Carrier (JLCC) Package (EPROM Version)

SSAVSS

A1A0XBUF

DV

64 636261605958575655545352

CC
CC
CC

A2
A3
A4
A5

Xin

CIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

202122 23 242526 272829303132

P0.3

P0.4

P0.2/TXD

AV
DV
SV

Rext

Xout/TCLK

TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

P0.0

P0.1/RXD

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

P0.5

RST/NMI

P0.6

P0.7

TCK

R33

TMS

TDI/VPP

R23

R13

TDO/TDI

COM3

COM2

S0

S1

R03

COM1

51

COM0

50

S20/O20/CMPI

49

S19/O19

48

S18/O18

47

S17/O17

46

S16/O16

45

S15/O15

44

S14/O14

43

S13/O13

42

S12/O12

41

S1 1/O11

40

S10/O10

39

S9/O9

38

S8/O8

37

S7/O7

36

S6/O6

35

S5/O5

34

S4/O4

33

S3/O3

S2/O2

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  2000, Texas Instruments Incorporated

1

MSP430P325

40°C to 85°C

MSP430P325IPG

MSP430P325IPM

MSP430P325IFN

25°C

PMS430E325FZ

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

description (continued)

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated
12+2 bit A/D converter with six multiplexed inputs.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

°

–

°

°

functional block diagram

PLASTIC

64-PIN QFP

(PG)

PLASTIC

64-PIN QFP

(PM)

— — —

PLASTIC

68-PIN PLCC

(FN)

CERAMIC

68-PIN JLCC

(FZ)

—

TDI/VPP

TDO/TDI

TMS
TCK

Bus

Conv

RST/NMI

Power-on-

Reset

MAB, 4 Bit

MCB

MDB, 8 Bit

Timer/Port

Applications:

A/D Conv.
Timer, O/P

6

8 b Timer/

Counter

Serial Protocol

Support

Basic

Timer1

f

CMPI

LCD

TXD

RXD

8 I/O’s, All With

1, 2, 3, 4 MUX

XIN Xout/TCLK XBUF P0.0 P0.7

Oscillator

FLL

System Clock

CPU

Incl. 16 Reg.

Test

JTAG

ACLK
MCLK

MAB, 16 Bit

MDB, 16 Bit

8/16 kB ROM

16 kB OTP
’C’: ROM

’P’: OTP

ADC

12 + 2 Bit

6 Channels

Current S.

6

256/512 B

RAM

Watchdog

Timer

15/16 Bit

I/O Port

Interr. Cap.

3 Int. Vectors

LCD

84 Segments

Com0–3
S0–19/O2–19
S20/O20CMPI

2

A0–5

SVCC

Rext

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TP0.0–5

CIN

R33 R13

R23

R03

I/O

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Terminal Functions

TERMINAL

NAME NO.

AV

CC

AV

SS

A0 61 I Analog-to-digital converter input port 0 or digital input port 0
A1 62 I Analog-to-digital converter input port 1 or digital input port 1
A2–A5 5–8 I Analog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5
CIN 11 I Input used as enable of counter TPCNT1 – Timer/Port
COM0–3 51–54 O Common outputs, used for LCD backplanes – LCD
DV

CC

DV

SS
P0.0 18 I/O General-purpose digital I/O
P0.1/RXD 19 I/O General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter
P0.2/TXD 20 I/O General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter
P0.3–P0.7 21–25 I/O Five general-purpose digital I/Os, bit 3 to bit 7
Rext 4 I Programming resistor input of internal current source
RST/NMI 59 I Reset input or non-maskable interrupt input
R03 29 I Input of fourth positive analog LCD level (V4) – LCD
R13 28 I Input of third positive analog LCD level (V3) – LCD
R23 27 I Input of second positive analog LCD level (V2) – LCD
R33 26 O Output of first positive analog LCD level (V1) – LCD
SV

CC

S0 30 O Segment line S0 – LCD
S1 31 O Segment line S1 – LCD
S2–S5/O2–O5 32–35 O Segment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD
S20/O20/CMPI 50 I/O Segment line S20 can be used as comparator input port CMPI – Timer/Port

S6–S9/O6–O9 36–39 O Segment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD
S10–S13/O10–O13 40–43 O Segment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD
S14–S17/O14–O17 44–47 O Segment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD
S18-S19/O18-O19 48, 49 O Segment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD
TCK 58 I Test clock, clock input terminal for device programming and test
TDO/TDI 55 I/O Test data output, data output terminal or data input during programming
TDI/VPP 56 I Test data input, data input terminal or input of programming voltage
TMS 57 I Test mode select, input terminal for device programming and test
TP0.0 12 O General-purpose 3-state digital output port, bit 0 – Timer/Port

TP0.1 13 O General-purpose 3-state digital output port, bit 1 – Timer/Port
TP0.2 14 O General-purpose 3-state digital output port, bit 2 – Timer/Port
TP0.3 15 O General-purpose 3-state digital output port, bit 3 – Timer/Port
TP0.4 16 O General-purpose 3-state digital output port, bit 4 – Timer/Port
TP0.5 17 I/O General-purpose digital input/output port, bit 5 – Timer/Port
XBUF 60 O Clock signal output of system clock MCLK or crystal clock ACLK

Xin 9 I Input terminal of crystal oscillator
Xout/TCLK 10 I/O Output terminal of crystal oscillator or test clock input

1 Positive analog supply voltage

63 Analog ground reference

2 Positive digital supply voltage

64 Digital ground reference

3 Switched AVCC to analog-to-digital converter

MSP430P325

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3

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

short-form description

processing unit

The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and it is
distinguished by ease of programming. All operations other than program-flow instructions are consequently
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.

Program Counter

CPU

Sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor frequency.

Four of the registers are reserved for special
use as a program counter, a stack pointer , a status
register, and a constant generator . The remaining
registers are available as general-purpose
registers.

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

R5

Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory

General-Purpose Register R14

manipulation.

General-Purpose Register

instruction set

The instruction set for this register-register architecture provides a powerful and easy-to-use assembler
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC
Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0

Each instruction that operates on word and byte data is identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation

MOV EDE, TONI MOV.B EDE, TONI
ADD #235h, &MEM ADD.B #35h, &MEM
PUSH R5 PUSH.B R5
SWPB R5 —

R15

4

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Table 2. Address Mode Descriptions

ADDRESS MODE s d SYNTAX EXAMPLE OPERATION

Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11
Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 5(R6) M(2 + R5) → M(6 + R6)
Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI)
Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT)
Indirect √ MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6)
Indirect autoincrement √ MOV @Rn+, RM MOV @R10+, R11 M(R10) → R11, R10 + 2 → R10
Immediate √ MOV #X, TONI MOV #45, TONI #45 → M(TONI)

NOTE: s = source d = destination

Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.

operation modes and interrupts

indirect

addressing, ideally suited for computed branches and

The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.

The software can configure five operating modes:

D

Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.

D

Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.

D

Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.

D

Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.

D

Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.

D

Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.

The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.

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5

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

The most general bits that influence current consumption and support fast turnon from low-power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.

15 9 8 7 0

Reserved For Future

Enhancements

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up, external reset, watchdog

NMI, oscillator fault
Dedicated I/O P0.0 P0.0IFG Maskable 0FFFAh 13

Dedicated I/O P0.1 or 8-Bit Timer/Counter
RXD

Watchdog Timer WDTIFG Maskable 0FFF4h 10

ADC ADCIFG Maskable 0FFEAh 5

Timer/Port

Basic Timer1 BTIFG Maskable 0FFE2h 1
I/O port 0, P0.2–7

NOTES: 1. Multiple source flags

2. Timer/Port interrupt flags are located in the T/P registers

3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.

V SCG1 SCG0 OscOff CPUOff GIE N Z C

rw-0

WDTIFG

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 4)

RC1FG, RC2FG, EN1FG

P0.27IFG (see Note 1)

(see Note1)

P0.1IFG Maskable 0FFF8h 12

(see Note 2)

Reset 0FFFEh 15, highest

Non-maskable,

(Non)-maskable

Maskable 0FFE8h 4

Maskable 0FFE0h 0, lowest

0FFFCh 14

0FFF6h 11

0FFF2h 9

0FFF0h 8
0FFEEh 7
0FFECh 6

0FFE6h 3

0FFE4h 2

6

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple SW access is
provided with this arrangement.

interrupt enable 1 and 2

Address
0h

7654 0

321

P0IE.1 OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE: Watchdog Timer enable signal
OFIE: Oscillator fault enable signal
P0IE.0: Dedicated I/O P0.0
P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD

Address
01h BTIE TPIE

7654 0

rw-0

321

rw-0

ADIE: A/D converter enable signal
TPIE: Timer/Port enable signal
BTIE: Basic Timer1 enable signal

interrupt flag register 1 and 2

Address
02h NMIIFG P0IFG.0

7654 0

rw-0 rw-1 rw-0

321

P0IFG.1 OFIFG WDTIFG

rw-0 rw-0

WDTIFG: Set on overflow or security key violation

or

Reset on VCC power on or reset condition at RST/NMI-pin
OFIFG: Flag set on oscillator fault
P0.0IFG: Dedicated I/O P0.0
P0.1IFG: P0.1 or 8-Bit Timer/Counter, RXD
NMIIFG: Signal at RST

/NMI-pin

P0IE.0

ADIE

rw-0

Address
03h BTIFG ADIFG

7654 0

rw

321

rw-0

BTIFG Basic Timer1 flag
ADFIG Analog-to-digital converter flag

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7

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

module enable register 1 and 2

Address
04h

Address
05h

Legend rw:

7654 0321

7654 0321

rw-0:

memory organization

Bit can be read and written.
Bit can be read and written. It is reset by PUC.
SFR bit not present in device.

MSP430P325
PMS430E325

FFFFh
FFE0h

FFDFh

C000h

Int. Vector

16 kB OTP

or

EPROM

03FFh

0200h
01FFh

0100h

00FFh

0010h

000Fh

0000h

512B RAM

16b Per.

8b Per.

SFR

8

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

peripherals

Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all
instructions for memory manipulation.

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog Watchdog Timer control WDTCTL 0120h
ADC Data register

Reserved
Control register
Input enable register
Input register

PERIPHERALS WITH BYTE ACCESS

EPROM EPROM control EPCTL 054h
Crystal buffer Crystal buffer control CBCTL 053h
System clock SCG frequency control

SCG frequency integrator
SCG frequency integrator

Timer/Port T imer/Port enable

Timer/Port data
Timer/Port counter2
Timer/Port counter1
Timer/Port control

8-Bit Timer/Counter 8-Bit Timer/Counter data

8-Bit Timer/Counter preload
8-Bit Timer/Counter control

Basic Timer1 Basic Timer counter2

Basic Timer counter1
Basic Timer control

LCD LCD memory 15

:
LCD memory 1
LCD control & mode

Port P0 Port P0 interrupt enable

Port P0 interrupt edge select
Port P0 interrupt flag
Port P0 direction
Port P0 output
Port P0 input

Special function SFR interrupt flag2

SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1

ADAT

ACTL
AEN
AIN

SCFQCTL
SCFI1
SCFI0

TPE
TPD
TPCNT2
TPCNT1
TPCTL

TCDAT
TCPLD
TCCTL

BTCNT2
BTCNT1
BTCTL

LCDM15
:
LCDM1
LCDCTL

P0IE
P0IES
P0IFG
P0DIR
P0OUT
P0IN

IFG2
IFG1
IE2
IE1

0118h
0116h
0114h
o112h
0110h

052h
051h
050h

04Fh
04Eh
04Dh
04Ch
04Bh

044h
043h
042h

047h
046h
040h

03Fh
:
031h
030h

015h
014h
013h
012h
011h
010h

003h
002h
001h
000h

oscillator and system clock

Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency . The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without any other external components being required.

The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.

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9

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

oscillator and system clock (continued)

The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:

D

High frequency in order to react quickly to system hardware requests or events

D

Low frequency in order to minimize current consumption, EMI, etc.

D

Stable frequency for timer applications e.g. real-time clock (RTC)

D

Enable start-stop operation with a minimum of delay

These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency , which is multiplied to achieve the desired
nominal operating range:

f

(system)

The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO) provides immediate start-up capability together with long term crystal stability . The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the
previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet
the chosen system frequency over a long period of time.

The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal
oscillator.

digital I/O

One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output
to the application:

D

All individual I/O bits are programmable independently.

D

Any combination of input, output, and interrupt conditions is possible.

D

Interrupt processing of external events is fully implemented for all eight bits of port P0.

D

Provides read/write access to all registers with all instructions

The six registers are:

= (N+1) × f

crystal)

(

D

Input register Contains information at the pins

D

Output register Contains output information

D

Direction register Controls direction

D

Interrupt flags Indicates if interrupt(s) are pending

D

Interrupt edge select Contains input signal change necessary for interrupt

D

Interrupt enable Contains interrupt enable pins

All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two
LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three
interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt
event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-Bit Timer/Counter.

10

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

LCD drive

Liquid crystal displays (LCDs) for static, 2-, 3- and 4-MUX operations can be driven directly . The controller LCD
logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module,
not part of data memory . Eight mode and control bits define the operation and current consumption of the LCD
drive. The information for the individual digits can be easily obtained using table programming techniques
combined with the correct addressing mode. The segment information is stored in LCD memory using
instructions for memory manipulation.

The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3­and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The
MSP430x32x configuration has four common signal lines and 21 segment lines.

A/D converter

The analog-to-digital converter (ADC) is a cascaded converter type that converts analog signals from VCC to
GND. It is a 12+2 bit converter with a software or automatically-controlled range select. Five inputs can be
selected for analog or digital function. A ratiometric current source can be used on four of the analog pins. The
current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The
conversion is started by setting the start-of-conversion bit (SOC) in the control register and the
end-of-conversions sets the interrupt flag. The analog input signal is sampled starting with SOC during the next
twelve MCLK clock pulses. The power-down bit in the control register controls the operating mode of the ADC
peripheral. The current consumption and operation is stopped when it is set. The system reset PUC sets the
power-down bit.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support
low current applications. The BTCTL control register contains the flags which control or select the different
operational functions. When the supply voltage is applied or when a reset of the device (RST
watchdog overflow or a watchdog security key violation occurs, and all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.

The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic T imer1 interrupt flag (BTIFG) and the
Basic Timer1 interrupt enable (BTIE) bit.

Watchdog Timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog
function is not needed in an application, the module can work as an interval timer, which generates an interrupt
after the selected time interval.

The Watchdog T imer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog T imer control register (WDTCTL), which is an 8-Bit read/write
register. W riting to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated.

the password is read its value is 069h

addition to the Watchdog Timer control bits, two bits included in the WDTCTL configure the NMI pin.

. This minimizes accidental write operations to the WDTCTL register. In

/NMI pin), a

When

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

8-Bit Timer/Counter

The 8-Bit interval timer supports three major functions for the application:

D

Serial communication or data exchange

D

Pulse counting or pulse accumulation

D

Timer

The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-Bit up-counter with preload
register, an 8-Bit control register, an input clock selector, an edge detection (e.g. Start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-Bit
counter.

The 8-Bit counter counts up with an input clock which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.

Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A
write-access to the counter results in loading the content of the preload register into the counter. The software
writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written
immediately after the load of the counter is completed. The enable input enables the count operation. When
the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock
input of the counter.

Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a
data transmission. When this function is activated, the counter starts counting after the start-bit condition is
detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,
which is programmed into the counter. T wo latches are used for input and output data (RXD_FF and TXD_FF)
are clocked by the counter after the programmed timing interval has elapsed.

UART

The serial communication uses software and the 8-Bit Timer/Counter hardware. The hardware supports the
output of the serial data stream, bit-by-bit, with the timing determined by the counter. The software/hardware
interface connects the mixed signal controller to external devices, systems, or networks.

Timer/Port

The Timer/Port module has two 8-Bit counters, an input that triggers one counter , and six 3-state digital outputs.
Both counters have an independent clock-selector for selecting an external signal or one of the internal clocks
(ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate
the counter by selecting one of two external signals. This gate signal sets the interrupt flag, if an external signal
is selected, and the gate stops the counter.

Both timers can be read from and written to by software. The two 8-Bit counters can be cascaded to a 16-bit
counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-Bit
counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate
signal, overflow from the MSB of the cascaded counter).

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Operating free-air temperature range, T

°C

Processor frequency (signal MCLK), f

MH

V

V

3 V/5 V

V

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

absolute maximum ratings

†

Voltage applied at VCC to VSS (see Note 5) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (referenced to VSS) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal ± 2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature,T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 5: All voltage values relative to VSS.

(unprogrammed device) –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

T

(programmed device) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VCC (MSP430P/E325) 2.7 5.5 V
Supply voltage, during programming OTP/EPROM

(AVCC = DVCC = VCC)
Supply voltage, V

p

XTAL frequency, f

Low-level input voltage, VIL (excluding Xin, Xout) V
High-level input voltage, VIH (excluding Xin, Xout)
Low-level input voltage, V
High-level input voltage, V

SS

p

(XTAL)

A

(system)

IL(Xin, Xout)

IH(Xin, Xout)

MSP430P325, PMS430E325 2.7 5 5.5 V

0 V
MSP430P325 –40 85
PMS430E325 25

32 768 Hz
VCC = 3 V DC 2.2
VCC = 5 V DC 3.3

VSS+0.8

V

CC

0.2×V

CC

V

CC

CC

=

0.7 V

0.8×V

SS
CC

V

SS
CC

°

z

f(MHz)

3.3

2.2

– Maximum Processor

Frequency – MHz

1.5

Minimum

(system)

f

2.7 3 5 5.5
VCC – Supply Voltage – V

NOTE: Minimum processor frequency is defined by system clock.

Figure 1. Processor Frequency vs Supply Voltage

VCC (V)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

MSP430P325

I

,

P325

A

I

Low power mode, (LPM0, LPM1)

P325

A

I

Low power mode, (LPM2)

A

I

Low power mode, (LPM3)

A

()

V

Positive-going input threshold voltage

V

Negative-going input threshold voltage

V

V

Hysteresis (V

V

)

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

supply current into AVCC+DV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(AM)

(CPUOff)

(LPM2)

(LPM3)

I

(LPM4)

NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption in LPM2, LPM3 and LPM4 are

Active mode, A/D conversion in
power-down

p

p

p

Low power mode, (LPM4)

measured with active Basic Timer1 (ACLK selected) and LCD module (f

excluding external current, f

CC

TA = –40°C to 85°C, VCC = 3 V 3000 5000
TA = –40°C to 85°C, VCC = 5 V 10000 12000
TA = –40°C to 85°C, VCC = 3 V 70 110
TA = –40°C to 85°C, VCC = 5 V 150 200
TA = –40°C to 85°C, VCC = 3 V 6 12
TA = –40°C to 85°C, VCC = 5 V 15 25
TA = –40°C 1.5 2.4
TA = 25°C
TA = 85°C 1.6 2.8
TA = –40°C 5.2 7
TA = 25°C
TA = 85°C 4 7
TA = –40°C 0.1 0.8
TA = 25°C
TA = 85°C 0.4 1.3

system

(LCD)

= 1 MHz

VCC = 3 V

VCC = 5 V

VCC = 3 V/5 V

=1024 Hz, 4 MUX).

1.3 2

4.2 6.5

0.1 0.8

µ

µ

µ

µ

µA

current consumption of active mode versus system frequency

IAM = I

AM[1 MHz]

× f

system

[MHz]

current consumption of active mode versus supply voltage

I

AM

= I

AM[3 V]

+ 200 µA/V × (VCC–3 V)

Schmitt-trigger inputs Port 0, P0.x Timer/Port, CIN, TP 0.5

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IT+

p

p

–

IT–

IT+

IT–

hys

VCC = 3 V 1.2 2.1
VCC = 5 V 2.3 3.4
VCC = 3 V 0.5 1.35
VCC = 5 V 1.4 2.3
VCC = 3 V 0.3 1
VCC = 5 V 0.6 1.4

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VOHHigh-level output current

V

VOLLow-level out ut voltage

V

t

t

High level or low level time

XBUF

C

V

CC

V/5 V

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

outputs – Port 0: P0.x; Timer/Port: TP0.0...5; LCD: Sxx/Oxx; XBUF, (see Note 6)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOH = –1.2 mA, VCC = 3 V, See Note 6 VCC–0.4 V

p

p

NOTES: 6. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±9.6 mA to satisfy the maximum

voltage drop specified.

7. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±20 mA to satisfy the maximum voltage
drop specified.

IOH = –3.5 mA, VCC = 3 V, See Note 7 VCC–1 V
IOH = –1.5 mA, VCC = 5 V, See Note 6 VCC–0.4 V
IOH = –4.5 mA, VCC = 5 V, See Note 7 VCC–1 V
IOL = 1.2 mA, VCC = 3 V, See Note 6 V
IOL = 3.5 mA, VCC = 3 V, See Note 7 V
IOL = 1.5 mA, VCC = 5 V, See Note 6 V
IOL = 4.5 mA, VCC = 5 V, See Note 7 V

SS
SS
SS
SS

leakage current (see Note 8)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

lkg(TP)

I

lkg(P0x)

I

lkg(S20)

I

lkg(Ax)

I

lkg(RST

NOTES: 8. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

Leakage current, Timer/Port

Leakage current, port 0
Leakage current, S20 V
Leakage current, ADC
Leakage current, RST/NMI ±50 nA

/NMI)

9. All Timer/Port pins TP0.0 to TP0.5 are Hi-Z. Pins CIN and TP.0 to TP0.5 are connected together during leakage current
measurement. In the leakage measurement the input CIN is included. The input voltage is VSS or VCC.

10. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

11. The input voltage is V
VCC to VSS terminal.

= VSS to VCC , the current source is off, AEN.x bit is normally reset to stop throughput current flowing from

(IN)

Timer/Port: V
(see Note 9)

Port 0: V
(see Note 10)

(S20)

ADC: Ax, x= 0 to 5
(see Note 11)

(TP0.x,CIN

(P0.x)

= VSS to V

CC

)

VCC = 3 V/5 V

CC
CC
CC
CC

VSS+0.4

VSS+1

VSS+0.4

VSS+1

±50 nA

±50 nA
±50 nA
±30 nA

input frequency – Port 0: P0.1; Timer/Port: CIN, TP0.5

f

(IN)

or

(H)

output frequency

f

XBUF

t

Xdc

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input frequency DC f

(L)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Duty cycle of O/P frequency

P0.x, CIN, TP.5

XBUF, CL = 20 pF f

f

,

= 20 pF,

L

= 3

=

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MCLK

f

XBUF

f

XBUF

3 V 300 ns
5 V 125 ns

= 1.1 MHz 40% 60%
= f
= f

ACLK
ACLK/n

35% 65%

50%

(system)

(system)

MHz

MHz

15

MSP430P325

f

N

00 0110 0000

0

f

MH

f

N

0100 0000 FN_4=FN_3=FN_2=0

f

N

0110 0000

1

2xf

(NOM)

MHz

f

N

0100 0000

1

f

N

0110 0000

X

3xf

(NOM)

MHz

f

N

0100 0000

X

f

N

0110 0000 FN_4 =1, FN_3=FN_2=X

4xf

(NOM)

MHz

f

N

0100 0000

X

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

external interrupt timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

(int)

NOTES: 12. The external signal sets the interrupt flag every time t

conditions to set the flag must be met independently of this timing constraint. Input frequency (t

13. The external signal needs additionally a timing resulting from the maximum input frequency constraint.

RAM

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

RAMh

NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program

CPU halted (see Note 14) 1.8 V

execution should take place during this supply voltage condition.

DCO

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

(NOM)

(NOM)

N

DCO

S f

DCO N

DCO3

DCO26

DCO3

DC26

DCO3

DCO26

DCO3

DCO26

= 1A0h, FN_4=FN_3=FN_2=0 VCC = 3 V/5 V 1 MHz

DCO

=

DCO

= 11

DCO

= 00

DCO

= 11

DCO

= 00

DCO

= 11

DCO

= 00

DCO

= 11

DCO

f

= f

MCLK
NDCO+1

, FN_4=FN_3=FN_2=0 VCC = 3 V/5 V A0h 1A0h 340h

NOM

= S × f

NDCO

Port P0: External trigger signal for the
interrupt flag (see Notes 12 and 13)

is met. It may be set even with trigger signals shorter than t

(int)

, FN_4=FN_3=FN_2=

, FN_4=FN_3=0, FN_2=

, FN_4=FN_3=0, FN_2=

, FN_4=0, FN_3= 1, FN_2=

, FN_4= 0, FN_3=1, FN_2=

, FN_4=1, FN_3=FN_2=

1.5 cycle

) is defined in MCLK cycles.

(int)

VCC = 3 V 0.15 0.6
VCC = 5 V 0.18 0.62
VCC = 3 V 1.25 4.7
VCC = 5 V 1.45 5.5

VCC = 3 V 0.36 1.05
VCC = 5 V 0.39 1.2

VCC = 3 V 2.5 8.1
VCC = 5 V 3 9.9

VCC = 3 V 0.5 1.5
VCC = 5 V 0.6 1.8

VCC = 3 V 3.7 11
VCC = 5 V 4.5 13.8

VCC = 3 V 0.7 1.85
VCC = 5 V 0.8 2.4

VCC = 3 V 4.8 13.3
VCC = 5 V 6 17.7

VCC = 3 V/5 V 1.07 1.13

(int)

. The

z

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

()

V

CC

V/5 V

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

f

(DCO26)

4xf

3xf

2xf

NOM

NOM

NOM

f

NOM

f

(DCO26)

f

(DCO3)

FN_2 = 0
FN_3 = 0
FN_4 = 0

f

(DCO26)

f

(DCO3)

FN_2 = 1
FN_3 = 0
FN_4 = 0

f

(DCO26)

f

(DCO3)

FN_2 = X
FN_3 = 1
FN_4 = 0

f

(DCO3)

Legend

Tolerance at Tap 26

DCO Frequency
Adjusted by Bits
2∧9–2∧5 in SCFI1

Tolerance at Tap 3

FN_2 = X
FN_3 = X
FN_4 = 1

crystal oscillator

C

(Xin)

C

(Xout)

Integrated capacitance at input VCC = 3 V/5 V 12 pF
Integrated capacitance at output VCC = 3 V/5 V 12 pF

PUC/POR

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

t

(POR_delay)

V

(POR)

V

(min)

t

(reset)

V

V

POR

PUC/POR Reset is accepted internally 2 µs

V

(POR)

(min)

Figure 2

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

150 250 µs

TA = –40°C 1.5 2.4 V

POR

TA = 25°C
TA = 85°C

= 3

VCC

No POR

1.2 2.1 V

0.9 1.8 V
0 0.4 V

POR

Figure 3. Power-On Reset (POR) vs Supply Voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

17

MSP430P325

V

V/5 V

V

I

Comparator (Timer/Port)

CPON

1

A

V

hys(

)

In ut hysteresis (com arator)

CPON

1

mV

f

6

()

f

6

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

3

2.4

2.5

2.1

LCD

V

O(HLCD)

V

O(LLCD)

I

I(R03)

I

I(R13)

I

I(R23)

r

o(Rx3 to Sxx)

2

1.5

V POR [V]

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.5

1

0.5

0

–40 –20 0 20 40 60 80

Temperature [°C]

Output 1 (HLCD) I
Output 0 (LLCD) I

Input leakage

Resistance I

Figure 4. V

<= 10 nA

(HLCD)

<= 10 nA

(LLCD)

R03 = V
No load at all seg and com pins

R13 = VCC/ 3,
No load at all seg and com pins

R23 = 2 VCC/ 3,
No load at all seg and com pins

(SXX)

SS,

= –3 µA, VCC = 3 V/5 V 50 kΩ

(POR)

1.2

25°C

vs Temperature

= 3

CC

VCC = 3 V/5 V ±20 nA

VCC–0.125 V

V

SS

VSS+0.125

1.8

MAX

MIN

0.9

CC

comparator (Timer/Port)

(com)

V

ref(com)

Internal reference voltage at (–) terminal CPON = 1 VCC = 3 V/5 V 0.23×V

com

wake-up LPM3

t

(LPM3)

18

Delay time

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

p

p

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCC = 3 V 250 350

=

VCC = 5 V 450 600

0.25×V

CC

VCC = 3 V 5 37

=

VCC =5 V 10 42

= 1 MHz

= 2 MHz

f = 3 MHz VCC = 5 V 6

VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V

CC

0.26×V

CC

µ

V

µs

ADC current

∆ISLoad compliance

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

ADC supply current (f

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

I

(ADC)

I

(ADC)

SVCC (switched AVCC)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

(SVCC)

I

(SVCC)

Z

(SVCC)

Input impedance SVCC off, VCC = 3 V/5 V 40 100 kΩ

current source (ADC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(Rext)

R

(ext)

Voltage, (Rext)
External resistor VCC = 3 V/5 V 95 1600 Ω

p

(ADCLK)

V

(Rext)

I

(RI)

VA0..A3 = 0 .. 0.4 × V
V

(Rext)/R(ext)

VA0..A3 = 0 .. 0.4 × V
IS = V

VA0..A3 = 0 .. 0.5 × V
IS = V

VA0..A3 = 0 .. 0.5 × V
IS = V

= 1 MHz)

= V

(SVCC)

= 6 mA,

(Rext)/R(ext)

(Rext)/R(ext)

(Rext)/R(ext)

SVCC on, current source off, VCC = 3 V 200 400 µA
SVCC on, current source off, VCC = 5 V 300 740 µA

SVCC on, I
SVCC off, SVCC = 0 V, VCC = 5 V ±0.1 µA

– V

(RI),

(SVCC)

= 1 mA

(SVCC)

= 6 mA

(SVCC)

= 1 mA

(SVCC)

= 6 mA

= –8 mA, VCC = 2.5 V VCC–0.2 V V

(SVCC)

, IS =

,

VCC = 3 V/5 V, 0.246 ×

VCC = 3 V,

VCC = 3 V,

VCC = 5 V,

VCC = 5 V,

V

(SVCC)

V

–1 1 µA

–3.2 3.2 µA

–1.5 1.5 µA

–3.2 3.2 µA

0.249 ×

(SVCC)

0.252 ×

V

(SVCC)

CC

V

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

MSP430P325

f

Conversion frequency

f

f

V

3 V/5 V

MHz

f

Conversion cycles

f

f

/N

V

3 V/5 V

y

gy

dN/dT

Temperature stability

V

3 V/5 V

LSB/°C

g

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

A/D converter (f

Resolution 12 + 2 bits

(con)

(concyc)

LSB Voltage VCC = 3 V/5 V 0.000061×V
INL

1

INL

2

INL

3

INL

4

DNL

dN/dV

(SVCC)V(SVCC)

Conversion offset 12 bit analog input to
digital value (see Note 17)

Conversion offset 14 bit analog input to
digital value (see Note 17)

Slope 12 bit VCC = 3 V/5 V 0.9925 1 1.0075
Slope 14 bit VCC = 3 V/5 V 0.9982 1 1.0018

C

(IN)

R

(SIN)

(ADCLK)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Integral nonlinearity
(see Note 15)

Differential nonlinearity
(see Note 16)

p

Input capacitance VCC = 3 V/5 V 40 45 pF
Serial input resistance VCC = 3 V/5 V 2 kΩ

= 1 MHz)

rejection ratio

=

(con)

(ADCLK)

=

(ADCLK)

0 ≤ DDV ≤ 127 VCC = 3 V/5 V –2 2 LSB
128 ≤ DDV ≤ 255 VCC = 3 V/5 V –3 3 LSB
256 ≤ DDV ≤ 2047 VCC = 3 V/5 V –7 7 LSB
2048 ≤ DDV ≤ 4095 VCC = 3 V/5 V –10 10 LSB

V

(Rext)/R(ext)

Range B
Range A, B, V

SVCC ±10%
Range A VCC = 3 V/5 V –1.2 –0.49 0.24

Range B VCC = 3 V/5 V –1.7 –0.6 0.49

Range C VCC = 3 V/5 V –1.8 –0.6 0.6

Range D VCC = 3 V/5 V –1.7 0.6 0.49

Range ABCD VCC = 3 V/5 V –0.27 –0.06 0.13

(MCLK)

= 6mA, Range A

(Rext)/R(ext)

12-bit conversion
12+2-bit conversion
12-bit conversion
12+2-bit conversion

= 1 mA,

=

CC

=

CC

VCC = 3 V/5 V –1 1 LSB

=

CC

VCC = 3 V/5 V

0.1 1.5

0.14 1.5
96

132

SVCC

0.008

0.015

1.25

cycles of

ADCLK

V

LSB/V

% FSRA

(see Note 18)

% FSRB

(see Note 18)

% FSRC

(see Note 18)

% FSRD

(see Note 18)

%FSR

(see Note 18)

°

ABCD

NOTES: 15. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not

12+2 bit.

16. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.

17. Offset referred to full scale 12/14 bit

18. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f

TCK frequenc

MH

JTAG/test

() ()

() y

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

JTAG

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(TCK)

R

(TEST)

V

(FB)

I

(FB)

t

(FB)

V

(PP)

I

(PP)

t

(pps)

t

(ppf)

P

n

t

(erase)

NOTES: 19. The TMS and TCK pullup resistors are implemented in all C-, P-, and E-versions.

JTAG/fuse (see Note 20)

EPROM (E) and OTP(P) –
versions only

EPROM (E) versions only

20. Once the JTAG fuse is blown, no further access to the MSP430 JT AG/test feature is possible. The JTAG block switches to by-pass
mode.

21. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.

Pullup resistors on TMS, TCK, TDI
(see Note 19)

Fuse blow voltage, E/P versions
(see Note 21)

Supply current on TDI to blow fuse 100 mA
Time to blow the fuse 1 ms
Programming voltage, applied to TDI/VPP 11 11.5 13 V
Current from programming voltage source 70 mA
Programming time, single pulse 5 ms
Programming time, fast algorithm 100 µs
Number of pulses for successful programming 4 100 Pulses
Data retention TJ < 55°C 10 year

Erase time wave length 2537 Å at 15 Ws/cm
(UV lamp of 12 mW/ cm2)

Write/Erase cycles 1000 cycles

y

VCC = 3 V DC 5
VCC = 5 V DC 10

VCC = 3 V/ 5 V 25 60 90 kΩ

VCC = 3 V/ 5 V 11 12 V

2

30 min

z

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

DIGITAL CONTROLLED OSCILLATOR FREQUENCY

vs

OPERATING FREE-AIR TEMPERATURE

1.8

1.5

C

°

1.2

(DCO@ 25 )

0.9

/f

(DCO)

f

0.6

0.3

0
–40 –20 0 20 40 9060 80

T – Operating Free-Air Temperature – °C

Figure 5

DIGITAL CONTROLLED OSCILLATOR FREQUENCY

vs

SUPPLY VOLTAGE

1.2

1

0.8

(DCO@ 3 V)

0.6

/f

(DCO)

f

0.4

0.2

0

02

VCC – Supply Voltage – V

46

Figure 6

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

typical input/output schematics

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

GND

CMOS INPUT (RST/NMI)

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

GND

CMOS SCHMITT-TRIGGER INPUT (CIN)

GND

I/O WITH SCHMITT-TRIGGER INPUT (P0.x, TP5) CMOS 3-STATE OUTPUT (TP0–4, XBUF)

TDO_Internal

V

CC

60 k TYP

MSP430P/E325: TMS, TCK

NOTES: A. Optional selection of pullup or pulldown resistors with ROM (masked) versions. Anti-parallel diodes are connected between A V

and DVSS.

B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory.

TDO_Control

TDI_Control

TDI_Internal

MSP430P/E325: TDO/TDI

SS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

typical input/output schematics

VC
VD

Control COM0–3

VA

VB

Segment control

VA

VB

Segment control

LCDCTL (LCDM5,6,7)

Data (LCD RAM bits 0–3

or bits 4–7)

LCD OUTPUT (COM0–4, Sn, Sn/On)

NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.

COM 0–3

S0, S1

S2/O2–Sn/On

VPP_ Internal

TDI_ Internal

TDI/VPP

JTAG
Fuse

TDO/TDI_Control

TDO/TDI

JTAG Fuse

TMS

NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage

source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.

B. The TDI/VPP terminal of the ’P325 and ’E325 does not have an internal pullup resistor. An external pulldown resistor is

recommended to avoid a floating node which could increase the current consumption of the device.

C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P325 and ’E325 needs a pullup or a pulldown resistor to avoid

floating a node which could increase the current consumption of the device.

Blow

Control

TDO_ Internal

From/To JTAG_CBT_SIG_REG

Figure 7. MSP430P325/E325: TDI/VPP, TDO/TDI

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity
of the fuse the first time the JT AG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.

Activation of the fuze check mode occurs with the first negative edge on the TMS pin after power-up or if TMS
is being held low during power-up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.

Time TMS Goes Low After POR

TMS

I

TF

I

TDI

Figure 8. Fuse Check Mode Current, MSP430P/E325

Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD
spikes that could cause signal edges on the TMS pin.

Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.

P/E3xx

TDI 68k, pulldown
TDO 68k, pulldown
TMS Open

TCK Open

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

PG (R-PQFP-G64) PLASTIC QUAD FLATPACK

52

64

51

1,00

1

18,00 TYP

20,20
19,80

24,40
23,60

0,45
0,25

33

19

0,20

M

32

20

12,00 TYP

18,0014,20

13,80 17,20

0,15 NOM

Gage Plane

2,70 TYP

3,10 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

0,10 MIN

0,25

0°–10°

1,10
0,70

Seating Plane

0,10

4040101/B 03/95

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325 (PM package)

CC

AV

MECHANICAL DATA

PM PACKAGE

(TOP VIEW)

SS

SS

AVA1A0

DV

XBUF

RST/NMI

TCK

TMS

PP

V

TDO/TDI

TDI/

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

COM0

COM1

COM3

COM2

S20/O20/CMPI

DV

CC

SV

CC

Rext

A2
A3
A4
A5

Xin

Xout/TCLK

CIN
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

63 62 61 60 5964 58

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1718 19

P0.0

P0.2/TXD

P0.1/RXD

21 22 23 24

20

P0.3

P0.4

P0.5

P0.6

56 55 5457

25 26 27 28 29

P0.7

R33

R32

53 52

R13

R03

51 50 49

30 31 32

S1

S0

S2/O2

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

S3/O3

S19/O19
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

27

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

49

64

0,50

48

0,27
0,17

33

1

7,50 TYP

10,20

SQ

9,80

12,20

SQ

11,80

16

0,08

32

17

M

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,45
1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.

0,75
0,45

Seating Plane

0,08

4040152/C 11/96

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325 (FN package)

CC

AV

NC

MECHANICAL DATA

FN PACKAGE

(TOP VIEW)

SS

SS

DV

AV

A1A0XBUF

RST/NMI

TCK

TMS

TDI/VPP

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TDO/TDI

COM3

COM2

COM1

COM0

NC

DV

CC

SV

CC

Rext

A2
A3
A4
A5

Xin

Xout/TCLK

CIN
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

P0.0

87 6 5493

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

28 29

27

NC

P0.1/RXD

NC – No internal connection

30

31 32 33 34

P0.3

P0.4

P0.2/TXD

P0.5

168672

35 36 37 38 39

R33

P0.6

P0.7

R23

66 65

R13

64 63 62 61

S0

R03

40 41 42 43

S1

S2/O2

S3/O3

S20/O20/CMPI

60
59

S19/O19

58

S18/O18

57

S17/O17

56

S16/O16

55

S15/O15

54

S14/O14

53

S13/O13

52

S12/O12

51

S11/O11

50

S10/O10

49

S9/O9

48

S8/O8

47

S7/O7

46

S6/O6

45

S5/O5

44

S4/O4

NC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

29

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

D

D1

13

4

E1E

8

9

NO. OF

PINS

**

D/E

19

13

18

14

0.032 (0,81)

0.026 (0,66)

0.050 (1,27)

0.008 (0,20) NOM

D1/E1

MINMAXMIN

MAX

D2/E2

MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

D2/E2

D2/E2

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

MAX

M

20
28
44
52
68
84

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

30

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

PMS430E325 (FZ package)

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

FZ PACKAGE

(TOP VIEW)

CC

AV

NC

DV

CC

SV

CC

rext

A2
A3
A4
A5

Xin

Xout/TCLK

CIN

TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

P0.0

87 65493

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

28 29

27

NC

P0.1/RXD

NC – No internal connection

SS

SS

A1

AV

DV

30

31 32 33 34

P0.3

P0.4

P0.2/TXD

A0

P0.5

XBUF

RST/NMI

TCK

168672

35 36 37 38 39

R33

P0.6

P0.7

TMS

R23

Vpp

TDO/TDI

TDI/

66 65

R13

R03

COM1

COM3

COM2

64 63 62 61

40 41 42 43

S0

S1

S2/O2

COM0

NC

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

NC

S3/O3

S20/O20/CMPI
S19/O19
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

31

MSP430P325
MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)  45°

5

A B

11

12

A

B

1426

18

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

0.120 (3,05)

25

0.032 (0,81)

0.026 (0,66)

19

0.025 (0,64) R TYP

Seating Plane

0.050 (1,27)

C

(at Seating

Plane)

0.020 (0,51)

0.014 (0,36)

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

NO. OFJEDEC

OUTLINE

MO-087AA

MO-087AB

MO-087AC

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.

PINS**

28

44

52

68MO-087AD

MIN MAX

0.485

(12,32) (12,57)

A

0.495

BC

0.430

MAXMIN

0.455

(11,56)(10,92)

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

4040219/B 03/95

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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