Texas Instruments CD74FCT245SM, CD74FCT245M96, CD74FCT245M, CD74FCT245E Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS271A

Features

• Buffered Inputs

• Typical Propagation Delay: 5.0ns at V

CC

= 5V,

T

A

= 25oC

• Noninverting

• SCR Latchup Resistant BiCMOS Process and
Circuit Design

• Speed of Bipolar FAST™/AS/S

• 64mA Output Sink Current (74 Series)

• 48mA Output Sink Current (54 Series)

• Output Voltage Swing Limited to 3.7V at V

CC

= 5V

• Controlled Output Edge Rates

• Input/Output Isolation to V

CC

• BiCMOS Technology with Low Quiescent Power

Description

The CD54/74FCT245 octal bus transceiver uses a small
geometry BiCMOS technology. The output stage is a combi­nation of bipolar and CMOS transistors that limits the output
HIGH level to two diode drops below V

CC

. This resultant
lowering of output swing (0V to 3.7V) reduces power bus
ringing (a source of EMI) and minimizes V

CC

bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48mA to 64mA.

The CD54/74FCT245 is a noninverting, three-state, bidirec­tional transceiver/buffer intended for two-way transmission
from”A” bus to “B” bus or “B” bus to “A” bus. The logic level
present on the Direction Input (DIR) determines the data direc­tion. When the Output Enable input is HIGH, the outputs are in
the high impedance state.

Pinout

Ordering Information

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74FCT245E 0 to 70 20 Ld PDIP E20.3
CD74FCT245M 0 to 70 20 Ld SOIC M20.3
CD54FCT245E -55 to 125 20 Ld PDIP E20.3

NOTE: When ordering the suffix M and SM packages, usetheentire
part number.Addthe suffix 96to obtainthe variantin the tapeand reel.

CD54FCT245, CD74FCT245

(PDIP, SOIC)

TOP VIEW

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

DIR

A0
A1
A2
A3
A4

A6

A5

A7

GND

V

CC

B0
B1
B2
B3
B4
B5
B6
B7

OE

January 1997 - Revised October 1999

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.

Copyright

© 1999, Texas Instruments Incorporated

CD54FCT245,

CD74FCT245

BiCMOS FCT Interface Logic,

Octal-Bus Tranceivers, Three-State

2

Functional Diagram

IEC Logic Symbol

TRUTH TABLE (NOTE 1)

CONTROL INPUTS

OPERATIONOE DIR

L L B Data to A Bus
L H A Data to B Bus
H X Isolation

NOTES:

1. H = High Voltage Level
L = Low Voltage Level
X = Irrelevant

2. To prevent excess currents in theHigh-Z (isolation) modes, all I/O terminals should be terminated
with 10kΩ to 1 MΩ resistors.

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

B0

B1

B2

B3

B4

B5

B6

B7

A0

A1

A2

A3

A4

A5

A6

A7

1

GND = PIN 10
V

CC

= PIN 20

19

DIR

OE

11

CD74FCT245, CD54FCT245

18
17
16

G3

3
4
5

15
14
13
12

6
7
8
9

3EN1

11

3EN1

19

1

1

2

2

CD54FCT245, CD74FCT245

3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V

DC Input Diode Current, IIK (for VI< -0.5V) . . . . . . . . . . . . . . -20mA

DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA

DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA

DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA

DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA

DC Ground Current (I

GND

). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA

Operating Conditions

Operating Temperature Range (TA) . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

CC

CD74 Series, TA = 0oC to 70oC . . . . . . . . . . . . . . .4.75V to 5.25V

CD54 Series,TA = -55oC to 125oC . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V

CC

DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V

CC

Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” maycause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is calculated in accordance with JESD 51.

Electrical Specifications 74FCT Commercial Temperature Range 0

o

C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V

54FCT Extended Industrial Temperature Range -55oC to 125oC; VCC Max = 5.5V, VCC Min = 4.5V

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

AMBIENT TEMPERATURE (TA)

UNITS

25oC0

o

C TO 70oC -55oC TO 125oC

V

I

IO (mA) MIN MAX MIN MAX MIN MAX

High Level Input Voltage V

IH

4.5 to 5.5 2 - 2 - 2 - V

Low Level Input Voltage V

IL

4.5 to 5.5 - 0.8 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or -15 Min 2.4 - 2.4 - - - V

V

IL

-12 Min 2.4 - - - 2.4 - V

Low Level Output Voltage V

OL

VIH or 64 Min - 0.55 - 0.55 - - V

V

IL

48 Min - 0.55 - - - 0.55 V

High Level Input Current I

IH

V

CC

Max - 0.1 - 1 - 1 µA

Low Level Input Current I

IL

GND Max - -0.1 - -1 - -1 µA

Three-State Leakage
Current

I

OZH

V

CC

Max - 0.5 - 10 - 10 µA

I

OZL

GND Max - -0.5 - -10 - -10 µA

Short Circuit Output Current
(Note 4)

I

OS

VCC or

GND

VO = 0

Max -60 - -60 - -60 - mA

Input Clamp Voltage V

IK

VCC or

GND

-18 Min - -1.2 - -1.2 - -1.2 V

Quiescent Supply Current,
MSI

I

CC

VCC or

GND

0 Max - 8 - 80 - 500 µA

AdditionalQuiescent Supply
Current perInput Pin TTLIn­puts High, 1 Unit Load

∆I

CC

3.4V

(Note 5)

Max - 1.6 - 1.6 - 2 mA

NOTES:

4. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.

5. Inputs that are not measured are at VCC or GND.

6. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max at 70oC.

CD54FCT245, CD74FCT245

4

Switching Specifications t

r

, tf = 2.5ns, CL = 50pF, RL - See Figure 3

PARAMETER SYMBOL

V

CC

(V)

AMBIENT TEMPERATURE (TA)

UNITS

25oC0oC TO 70oC -55oC TO 125oC

TYP MIN TYP MAX MIN TYP MAX

Propagation Delays

Data to Outputs)

t

PLH

, t

PHL

5 5 1.5 - 7 1.5 - 7.5 ns

Output Enable to Output t

PZL

, t

PZH

5 6 1.5 - 9.5 1.5 - 10 ns

Output Disable to Output t

PLZ

, t

PHZ

5 6 1.5 - 7.5 1.5 - 10 ns

Power Dissipation
Capacitance

C

PD

- 49 - 49 - - 49 - pF

Min (Valley) V

OHV

During Switching
of Other Outputs (Output Under Test
Not Switching)

V

OHV

5 0.5------ V

Max (Peak)V

OLP

During Switchingof
Other Outputs(Output UnderTest Not
Switching)

V

OLP

5 1------ V

Input Capacitance C

l

- - - - 10 - - 10 pF

Input/Output Capacitance C

I/O

- - - - 15 - - 15 pF

NOTES:

7. 5V: Min is at 5.5V, Max is at 4.5V.

5V: Min is at 5.25V for 0oC to 70oC, Max is at 4.75V for 0oC to 70oC, Typ is at 5V.

8. CPD, measured per function,is used to determine the dynamic power consumption.

PD (per package) = VCC ICC+∑ (V

CC

2

fl CPD + V

O

2

fO CL+ VCC∆lCC D) where:

VCC = supply voltage

∆lCC = flow through current x unit load

CL = output load capacitance

D = duty cycle of input high

fO = output frequency

fI= input frequency

CD54FCT245, CD74FCT245

5

Test Circuits and Waveforms

NOTE:

9. Pulse Generator for AllPulses: Rate≤ 1.0MHz; Z

OUT

≤ 50Ω;

tf, tr≤ 2.5ns.

FIGURE 1. TEST CIRCUIT

FIGURE 2. SETUP, HOLD, AND RELEASE TIMING FIGURE 3. PULSE WIDTH

FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY

3V

0

DUT

PULSE Z

O

GEN

7V

500Ω

50pF

500Ω

V

CC

R

T

RT = Z

O

V

0

C

L

R

L

R

L

V

I

tr, tf = 2.5ns

(NOTE 9)

SWITCH POSITION

TEST SWITCH

t

PLZ

, t

PZL

, Open Drain Closed

t

PHZ

, t

PZH

, t

PLH

, t

PHL

Open

DEFINITIONS:

CL = Load capacitance, includes jig and probe

capacitance.

RT= Terminationresistance, should be equalto Z

OUT

of

the Pulse Generator.

VIN = 0V to 3V.

Input: tr=tf= 2.5ns (10% to 90%), unless otherwise specified

ASYNCHRONOUS CONTROL

t

H

t

SH

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

t

H

t

SH

PRESET CLEAR

CLOCK ENABLE

ETC.

SYNCHRONOUS CONTROL

t

REM

DAT A

INPUT

TIMING

INPUT

t

W

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

1.5V

1.5V

3V

1.5V
0V

CONTROL INPUT

OUTPUT

NORMALLY LOW

OUTPUT

NORMALLY HIGH

SWITCH

OPEN

t

PZL

3.5V

1.5V

1.5V
0V

t

PLZ

t

PHZ

t

PZH

0V

3.5V

0.3V

0.3V

V

OL

V

OH

SWITCH

CLOSED

ENABLE DISABLE

1.5V

3V

0V

1.5V

3V

0V

t

PLH

SAME PHASE

INPUT TRANSITION

t

PHL

t

PLH

t

PHL

OPPOSITE PHASE

INPUT TRANSITION

OUTPUT

1.5V

V

OH

V

OL

CD54FCT245, CD74FCT245

6

NOTES:

10. V

OLP

is measured with respect to a ground reference near the output under test. V

OHV

is measured with respect to VOH.

11. Input pulses have the following characteristics:
PRR≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.

12. R.F. fixture with 700MHz design rules required. IC should besoldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.

FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS

Test Circuits and Waveforms

(Continued)

OTHER
OUTPUTS

OUTPUT
UNDER
TEST

V

OH

V

OL

V

OH

V

OHV

V

OLP

V

OL

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Copyright  1999, Texas Instruments Incorporated