Siemens TLE4226G Datasheet
Intelligent Sixfold Low-Side Switch
Features
● Quad 50 mA outputs
● Dual 500 mA outputs
● Operating range V
● Output stages with power limiting
● Open-collector outputs
● Shorted load protected within operating range
● Clamp-diodes to ground
● Status signaling
● TTL-compatible control inputs
● Overtemperature monitoring
● Temperature range – 40 to 125 ˚C
= 5 V ± 5 %
S
TLE 4226 G
Bipolar-IC
P-DSO-24-3
Type Ordering Code Package
▼
TLE 4226 G Q67000-A9118 P-DSO-24-3 (SMD)
▼ New type
TLE 4226 G is an integrated, sixfold low-side power switch with power limiting of the 0.5 A outputs,
shorted-load protection of the 50 mA switches and Z-diodes on all switches from output to ground.
TLE 4226 G is particularly suitable for automotive and industrial applications.
Semiconductor Group 1 07.96
Pin Configuration
(top view)
TLE 4226 G
Pin Definitions and Functions
Pin Symbol Function
1 IN1 Input switch 1, active high (50 mA)
2 IN2 Input switch 2, active high (50 mA)
3 IN3 Input switch 3, active high (50 mA)
4 IN4 Input switch 4, active high (50 mA)
5, 6, 7, 8 GND Ground, cooling
9 IN5 Input switch 5, active high (500 mA)
10 IN6 Input switch 6, active high (500 mA)
11 StA Status output analog
12 StD Status output digital (error = low)
13
V
S
Supply voltage
14 PREFST Preferred state input, active low
15 Q6 Output switch 6 (500 mA)
16 Q5 Output switch 5 (500 mA)
17, 18, 19, 20 GND Ground, cooling
21 Q4 Output switch 4 (50 mA)
22 Q3 Output switch 3 (50 mA)
23 Q2 Output switch 2 (50 mA)
24 Q1 Output switch 1 (50 mA)
Semiconductor Group 2
TLE 4226 G
Block Diagram
Semiconductor Group 3
TLE 4226 G
Application Description
Applications in automotive electronics call for intelligent power switches that can be activated by
logic signals, which have to be shorted load protected and which provide error feedback.
This IC contains six power switches connected to ground (low-side switches). On inductive loads
the integrated Z-diodes clamp the discharging voltage.
By means of TTL signals on the control inputs (active high) all six switches can be activated
independently of one another when a high level appears on the preferred-state input. When there
is a low level on the preferred-state input, switches 1 to 4 are switched on, switches 5 and 6 are
switched off regardless of the control-input levels. The inputs are highly resistive and therefore must
not be left unconnected but should always be on fixed potential (noise immunity). Inputs that are not
used, should be connected to low level to reduce the power consumption.
The analog status output signals the following errors by analog voltage levels:
– Overload
– Thermal overload
– Openload or shorted load to ground (only switches 5 and 6)
The following levels signal errors at the analog and digital status outputs.
Errors Analog Status Digital Status
Normal function Low High
Overload
Openload or shorted load to ground (only switches 5 and 6)
Thermal overload
1.0 V to 3.3 V
1.0 V to 1.7 V
> 3.5 V
Low
Low
Low
Possible Input and Output Levels
Supply Voltage
2 to 5 V
5 V
5 V
V
PREFST IN1-6 Q1-Q4 Q5, Q6
S
Low
High
High
Random
Low
High
Low
High
Low
High
High
Low
Semiconductor Group 4
TLE 4226 G
Circuit Description
Input Circuits
The control inputs and the preferred-state input consist of TTL-compatible Schmitt triggers with
hysteresis. Driven by these stages the buffer amplifiers convert the logic signal necessary for driving
the NPN power transistors.
Switching Stages
The output stages consist of NPN power transistors with open collectors. Each stage has its own
protective circuit for limiting power dissipation and shorted load current, which makes the outputs
shorted load protected to the supply voltage throughout the operating range. Integrated clampdiodes limit positive voltage spikes that occur when inductive loads are discharged. Output currents,
caused through negative voltages at the outputs, are compensated up to 50 mA for all outputs in
total.
Monitoring and Protective Functions
Each output is monitored (for overload) in its activated status. For the switches 1 to 4 overload is
detected, if the switches are activated and the output voltage at the transistor is higher than 4.1 V
for more than 10 µs. The concerned output will be shutdown and both status outputs will be set. The
switch can only be activated again if the corresponding input is switched off and then on again. If
the output voltage does not exide 4.1 V, the output is not shutdown and the status outputs are not
set, although an overload may occur. The switches 5 and 6 are protected through a SOA-circuit. It
is suppressed for at least 10 µs when the switch is turned on before it can start limiting the overload
current. The status outputs also monitor openload or shorted load to ground at the switches 5 and
6 in deactivated mode.
An analog signal is applied to the analog status output only when protection function is active. If
several malfunctions appear coincident, the highest voltage level of the analog status output will
dominate. Simultaniously the digital status output will be set.
The IC is also protected against thermal overload. If a chip temperature of typically 155 ˚C is
attained, the status outputs monitor overtemperature. If the temperature continues to increase, the
inputs and outputs of the switches 5 and 6 are shutdown. The switches 1 to 4 will not shutdown, so
precaution has to be taken in the application to prevent a further increase of the chiptemperature,
which may destroy the IC. After cooling down below 140 ˚C the overtemperature monitoring will be
reseted and the outputs of the switches 5 and 6 can be activated again.
If the minimum supply voltage for operation is not maintained, the outputs are deactivated. At a
supply voltage of higher than 1.8 V, the outputs 1 to 4 are switched on, if pin 14 (PREFST) is
connected to ground over a resistance smaller 1 MΩ. The outputs 1 to 4 can be controlled via the
inputs, if pin 14 (PREFST) is switched to high or not connected. Characteristics may be beyond the
specified values. Full function is guaranteed in the supply voltage range of 5 V ± 5%.
Semiconductor Group 5
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