Siemens SFH6318T, SFH6319T Datasheet

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SFH6318T
SFH6319T

LOW CURRENT, HIGH GAIN

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FEATURES

• Industry Standard SOIC-8 Surface Mountable
Package

• High Current Transfer Ratio, 800%

• Low Input Current, 0.5mA

• High Output Current, 60mA

• Isolation Test Voltage, 2500 VAC

• TTL Compatible Output, VOL=0.1 V

• Adjustable Bandwidth-Access to Base

• Underwriters Lab File #E52744

• Available in Tape and Reel (suffix T)

APPLICATIONS

• Logic Ground Isolation-TTL/TTL, TTL/CMOS,
CMOS/CMOS, CMOS/TTL

• EIA RS 232C Line Receiver

• Low Input Current Line Receiver-Long Lines,
Party Lines

• Telephone Ring Detector

• 117 VAC Line Voltage Status Indication-Low
Input Power Dissipation

• Low Power Systems-Ground Isolation

DESCRIPTION

Very high current ratio together with 2500 VAC isolation
are achieved by coupling an LED with an integrated high
gain photodetector in a SOIC-8 package. Separate pins
for the photodiode and output stage enable TTL compat­ible saturation voltages with high speed operation. Pho­todarlington operation is achieved by tying the VCC and
VO terminals together. Access to the base terminal
allows adjustment to the gain bandwidth.

The SFH6318T is ideal for TTL applications since the
300% minimum current transfer ratio with an LED current
of 1.6 mA enables operation with one unit load-in and
one unit load-out with a 2.2 KΩ

The SFH6319T is best suited for low power logic applica­tions involving CMOS and low power TTL. A 400% cur­rent transfer ratio with only 0.5 mA of LED current is
guaranteed from 0°C to 70°C.

Caution:

Due to the small geometries of this device, it should be
handled with Electrostatic Discharge (ESD) precautions.
Proper grounding would prevent damage further and/or
degradation which may be induced by ESD.

RMS

pull-up resistor.

Package Dimensions in Inches (mm)

.120±.002

(3.05±.05)

.240

(6.10)

Pin 1

.004 (.10)
.008 (.20)

.021
(.53)

.192±.005
(4.88±.13)

C

L

.016
(.41)

.050
(1.27)
typ.

TOLERANCE: ±.005 (unless otherwise noted)

Maximum Ratings (25°)
Emitter

Reverse Input Voltage.............................................................. 3 V

Supply and Output Voltage, V

SFH6318T ..................................................................–0.5 to 7 V

SFH6319T ................................................................–0.5 to 18 V

Input Power Dissipation ..................................................... 35 mW

Derate Linearly above 50°C

Free Air Temperature................................................ 0.7 mW/°C

Average Input Current......................................................... 20 mA

Peak Input Current .............................................................. 40 mA

(50% Duty Cycle-1 ms pulse width)

Peak Transient Input Current

(tp≤

1 µsec, 300 pps) .........................................................1.0 A

Detector (Si Photodiode + Photodarlington)

Output Current I

Emitter-Base Reverse Voltage (pin 5-7)................................ 0.5 V

Output Power Dissipation................................................. 150 mW

Derate Linearly from 25°C ........................................... 2 mW/°C

Package

Storage Temperature ......................................... –55°C to +125°C

Operating Temperature........................................ –40°C to +85°C

Lead Soldering Temperature (t=10 sec.).............................260°C

Junction Temperature ..........................................................100°C

Ambient Temperature Range............................. –55°C to +100°C

IsolationTest Voltage between

Emitter and Detector............................................ 2500 VAC

(refer to climate DIN 40046, part 2, Nov. 74)

Pollution Degree (DIN VDE 0110) ................................................2

Creepage Distance .............................................................≥4 mm

Clearance............................................................................≥4 mm

Comparative Tracking Index

per DIN IEC 112/VDE 0303, part 1 .......................................175

Isolation Resistance

V

=500 V, T

IO

V

=500 V, T

IO

(pin 6)..................................................... 60 mA

O

=25°C R

A

ISOL

=100°C R

A

ISOL

OPTOCOUPLER

NC

1

2

Anode

.154±.002
(.391±.05)

.015±.002

.008 (.20)

.020±.004

(.15±.10)

2 plcs.

(pin 8-5), VO (pin 6-5)

CC

.............................................≥10

...........................................≥1011Ω

Cathode

(.38±.05)

3

4

NC

5° max.

40°

R.010

(.25)

max.

8

7

6

5

7°

.058±.005

(1.49±.13)

.125±.005
(3.18±.13)

Lead
Coplanarit
±.0015 (.04
max.

VCC

VB

V

GND

0

RMS

12

Ω

Semiconductor Goup 4–48

This document was created with FrameMaker 4.0.3

10.95

Electro-Optical Characteristics (T

=0°C to 70°C, TA=25°C-Typical, unless otherwise specified)

A

Parameter Symbol Device Min Typ Max Units Test Conditions Note

Current Transfer Ratio CTR SFH6318T 300 1600 2600 % I

Logic Low
Output Voltage

Logic High
Output Current

Logic Low Supply Current I

Logic High Supply Current I

Input Forward Voltage V

Temperature Coefficient,
Forward Voltage

Input Capacitance C

Resistance (Input-Output) R

Capacitance (Input-Output) C

Switching Specifications (T

V

I

OH

CCL

∆VF/∆T

=25°C)

A

SFH6319T 400

SFH6318T 0.1 0.4 V IF=1.6 mA, IO=4.8 mA, VCC=4.5 V 2

OL

SFH6319T 0.1

SFH6318T 0.1 250 µAIF=0 mA, VO=VCC=7 V 2
SFH6319T 0.05 100 µAIF=0 mA, VO=VCC=18 V 2

CCH

F

A

IN

I-O

I-O

1600
2000

0.15

0.25

2600
3500

0.4

0.4

0.4

500

0.2 1.5 mA IF=1.6 mA, VO=OPEN, VCC=18 V 2

0.01 10 µAIF=0 mA, VO=OPEN, VCC=18 V 2

1.4 1.7 V IF=1.6 mA, TA=25°C

–1.8 mV/°CIF=1.6 mA

25 pF f=1 MHz, VF=0

12

10

11

10

0.6 pF f=1 MHz 3

=1.6 mA, VO=0.4 V, VCC=4.5 V 1,2

F

%IF=0.5 mA, VO=0.4 V, VCC=4.5 V

IF=1.6 mA, VO=0.4 V, VCC=4.5 V

VIF=1.6 mA, IO=8 mA, VCC=4.5 V

IF=5 mA, IO=15 mA, VCC=4.5 V
IF=12 mA, IO=24 mA, VCC=4.5 V

V

=500 VDC, TA=25°C

Ω

IO

VIO=500 VDC, TA=100°C

Ω

Parameter Symbol Device Min Typ Max Units Test Conditions Note

Propagation Delay Time
To Logic Low at Output

Propagation Delay Time
To Logic High at Output

Common Mode Transient Im­munity at Logic High Level
Output

Common Mode Transient Im­munity at Logic Low Level Out­put

Notes

1. DC current transfer ratio is defined as the ratio of outpput collector current, IO, to the forward LED input current, IF times 100%.

2. Pin 7 open.

3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together.

4. Using a resistor between pin 5 and 7 will decrease gain and delay time.

5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO>2.0 V) common mode transient immunity in logic
low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode puse signal, VCM, to assure that the
output will remain in a logic low state (i.e. VO<0.8 V).

6. In applications where dv/dt may exceed 50,000 V/µs (such as state discharge) a series resistor, R
from destructively high surge currents. The recommended value is R

t

SFH6318T 2 10 µsIF=1.6 mA, RL=2.2 KΩ

PHL

SFH6319T 6

t

SFH6318T 2 35 µsIF=1.6 mA, RL=2.2 KΩ

PLH

SFH6319T 4

0.6251

1.5607

| CMH |1 KV/µsIF=0 mA, RL=2.2 KΩ

| CML|1 KV/µsIF=1.6 mA, RL=2.2 KΩ

≅ IV

CC

0.15 IF(mA)

µsIF=0.5 mA, RL=4.7 KΩ

IF=12 mA, RL=270 Ω

µsIF=0.5 mA, RL=4.7 KΩ

IF=12 mA, RL=270 Ω

VCM=10 V

p-p

VCM=10 V

p-p

/dt on the leading edge of the commo-

cm

should be included to protect IC

kΩ. Refer to Figure 2.

CC

1,2

2

3

2,4

2,4

5,6

5,6

Semiconductor Group 4–49

SFH6318T/6319T