Siemens HYB3164165AT-40, HYB3164165AT-50, HYB3164165AT-60, HYB3164165ATL-50, HYB3164165ATL-60 Datasheet
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4M x 16-Bit Dynamic RAM
HYB 3164165AT(L) -40/-50/-60
(8k, 4k & 2k Refresh, EDO-Version)
Advanced Information
• 4 194 304 words by 16-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode - EDO - operation
• Performance:
t
RAC
t
CAC
t
AA
t
RC
t
HPC
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation:
RAS access time 40 50 60 ns
CAS access time 10 13 15 ns
Access time from address 20 25 30 ns
Read/write cycle time 69 84 104 ns
Hyper page mode (EDO)
cycle time
-40 -50 -60
HYB 3165165AT(L) -40/-50/-60
HYB 3166165AT(L) -40/-50/-60
-40 -50 -60
16 20 25 ns
HYB3166165AT(L) 1008 612 450 mW
HYB3165165AT(L) 756 504 360 mW
HYB3164165AT(L) 612 324 324 mW
7.2 mW standby (TTL)
3.24 mW standby (MOS)
720 µA standby for L-version
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS
-only refresh, hidden refresh and Self Refresh (L-version only
• 2 CAS / 1 WE byte control
• 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT)
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT)
2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT)
• 256ms refresh period for L-versions
• Plastic Package: P-TSOPII-50 400 mil
Semiconductor Group 1 6.97
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on
an advanced first generation 64Mbit 0,35 µm CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)165AT operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165AT to be
packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities
and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5/6)165ATL parts have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type Ordering
Package Descriptions
Code
8k-refresh versions:
HYB 3164165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns)
HYB 3164165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3164165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
HYB 3164165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3164165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
4k-refresh versions:
HYB 3165165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns)
HYB 3165165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3165165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
HYB 3165165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3165165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
2k-refresh versions:
HYB 3166165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns)
HYB 3166165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3166165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
HYB 3166165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns)
HYB 3166165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns)
Semiconductor Group 2
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
Pin Configuration
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.
A0
A1
A2
A3
A4
A5
VCC
P-TSOPII-50 (400 mil)
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
.
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
VSS
.
LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS
* Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L)
** Pin 32 is A11 for HYB 3164(5)165AT(L) and N.C. for HYB 3166165AT(L)
Pin Names
A0-A12 Address Inputs for 8k-refresh version HYB 3164165T(L)
A0-A11 Address Inputs for 4k-refresh version HYB 3165165T(L)
A0-A10 Address Inputs for 2k-refresh version HYB 3166165T(L)
RAS
OE
I/O1-I/O16 Data Input/Output
, LCAS Column Address Strobe
UCAS
WE
Vcc Power Supply ( + 3.3V)
Vss Ground
Row Address Strobe
Output Enable
Read/Write Input
Semiconductor Group 3
TRUTH TABLE
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
FUNCTION
Standby
Read:Word
Read:Lower Byte
Read:Upper Byte
Write:Word
(Early-Write)
Write:Lower Byte
(Early-Write)
Write:Upper Byte
(Early Write)
Read-ModifyWrite
Hyper Page Mode
Read (Word)
Hyper Page Mode
Read (Word)
1st
Cycle
2nd
Cycle
RAS LCAS UCAS WE OE ROW
ADD
COL
ADD
H H - X H - X X X X X
L L H H L ROW COL
L L H H L ROW COL
L H L H L ROW COL
L L L L X ROW COL
L L H L X ROW COL
L H L L X ROW COL
L L L H - L L - H ROW COL
L H - L H - L H L ROW COL
L H - L H - L H L n/a COL
I/O1I/O16
High Impedance
Data Out
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data In
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data Out, Data In
Data Out
Data Out
Hyper Page Mode
Early Write(Word)
Hyper Page Mode
Early Write(Word)
Hyper Page Mode
RMW
Hyper Page Mode
RMW
RAS only refresh
CAS-before-RAS
refresh
Test Mode Entry
Hidden Refresh
(Read)
Hidden Refresh
(Write)
Self Refresh
(L-version only)
1st
Cycle
2nd
Cycle
1st
Cycle
2st
Cycle
L H - L H - L L X ROW COL
L H - L H - L L X n/a COL
L H - L H - L H - L L - H ROW COL
L H - L H - L H - L L - H n/ a COL
L H H X X ROW n/a
H - L L L H X X n/a
H - L L L L X X n/a
L-H-LL L H L ROW COL
L-H-LL L L X ROW COL
H-L L H X X X X
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
High Impedance
Data Out
Data In
High Impedance
Semiconductor Group 4
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
WE
UCAS
LCAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
.
&
.
No. 2 Clock
Generator
Column
9
13 13
Address
Buffer(9)
Refresh
Controller
Refresh
Counter (13)
13
Row
Address
Buffers(13)
I/O1 I/O2
Data in
Buffer
Row
Decoder
16
9
8192
I/O16
Data out
Buffer
16
Column
Decoder
Sense Amplifier
I/O Gating
512
x16
Memory Array
8192x512x16
OE
16
No. 1 Clock
RAS
Block Diagram for HYB 3164165AT(L)
Semiconductor Group 5
Generator
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
UCAS
LCAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
WE
.
&
.
No. 2 Clock
Generator
Column
10
12 12
Address
Buffer(10)
Refresh
Controller
Refresh
Counter (12)
12
Row
Address
Buffers(12)
I/O1 I/O2
Data in
Buffer
Row
Decoder
16
10
4096
I/O16
Data out
Buffer
16
Column
Decoder
Sense Amplifier
I/O Gating
1024
x16
Memory Array
4096x1024x16
OE
16
No. 1 Clock
RAS
Block Diagram for HYB 3165165AT(L)
Semiconductor Group 6
Generator
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
UCAS
LCAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
WE
.
&
.
No. 2 Clock
Generator
Column
11
11 11
Address
Buffer(11)
Refresh
Controller
Refresh
Counter (11)
11
Row
Address
Buffers(11)
I/O1 I/O2
Data in
Buffer
Row
Decoder
16
11
2048
I/O16
Data out
Buffer
16
Column
Decoder
Sense Amplifier
I/O Gating
2048
x16
Memory Array
2048x2048x16
OE
16
RAS
Block Diagram for HYB3166165AT(L)
Semiconductor Group 7
No. 1 Clock
Generator
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range.............. .......................... ............................... .......................0 to 70 °C
Storage temperature range.............. ........ ........ ........ ........ ........ ........ ........ ........ ........ ...– 55 to 150 °C
Input/output volt age...... ............ ............ ............ ............ ............ ............ ....-0.5 to min (Vcc+0. 5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation..... .... .... .... .... ...... .... .... .... ...... .... .... .... .... ...... .... .... .... ...... .... .... .... .... ...... .... ..... ..1.3 W
Data out current (short circuit)............... .............. ... .. .. .............. .............. .............. .. .............. ....50 mA
Note
Stresses above those list ed under „Absolute M a ximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
T
= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
A
Parameter Symbol Limit Values Unit Note
min. max.
Input high voltage
Input low voltage
Output high voltage (LVTTL)
V
IH
V
IL
V
OH
2.0 Vcc+0.3 V 1)
– 0.3 0.8 V 1)
2.4 – V
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)
V
OL
– 0.4 V
Output „L“level voltage (Iout = +2mA)
Output high voltage (LVCMOS)
V
OH
Vcc-0.2 - V
Output „H“ level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)
V
OL
- 0.2 V
Output „L“ level voltage (Iout = +100uA)
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
I
I
I(L)
O(L)
– 2 2 µ A
– 2 2 µ A
Semiconductor Group 8
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
DC-Characteristics (cont’d)
T
= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
A
Parameter Symbol refresh version Unit Note
2k 4k 8k
Operating Current
-40 ns version
-50 ns version
- -60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Current (
Only Refresh Current:
RAS
RAS=CAS= Vih) I
- -40 ns version
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Hyper Page Mode (EDO) Current:
-40 ns version
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)
Standby Current (
RAS=CAS= Vcc-0.2V) I
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
CAS
Before RAS Refresh Cur rent
-40 ns version
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
I
I
I
I
I
CC1
CC2
CC3
CC4
CC5
CC5
CC6
280
230
185
170
140
115
125
100
85
mA
mA
mA
2) 3)
4)
222mA–
280
230
185
140
105
85
170
140
115
140
105
85
125
100
84
140
105
85
mA
mA
mA
mA
mA
mA
2) 4)
2) 3)
4)
900 900 900 µA–
200 200 200 µA–
280
230
185
170
140
115
170
140
115
mA
mA
mA
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low,
= Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
WE
I
CC7
400 400 400 µA
Capacitance
T
= 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
A
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A11,A12)
Input capacitance (RAS
, CAS, WE, OE) C
I/O capacitance (I/O1-I/O16)
C
I1
I2
C
IO
–5pF
–7pF
–7pF
Semiconductor Group 9
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