Siemens HYB3164160AT-60, HYB3164160ATL-50, HYB3164160ATL-60, HYB3164160AT-40, HYB3164160AT-50 Datasheet

4M x 16-Bit Dynamic RAM

( 8k, 4k & 2k Refresh)

Advanced Information

• 4 194 304 words by 16-bit organization

• 0 to 70 °C operating temperature

• Fast Page Mode operation

• Performance:

HYB 3164160AT(L) -40/-50/-60
HYB 3165160AT(L) -40/-50/-60

HYB 3166160AT(L) -40/-50/-60

-40 -50 -60

t

RAC

t

CAC

t

AA

t

RC

t

PC

• Single + 3.3 V (± 0.3V) power supply

• Low power dissipation:

RAS access time 40 50 60 ns
CAS access time 10 13 15 ns
Access time from address 20 25 30 ns
Read/write cycle time 75 90 110 ns
Fast page mode cycle time 30 35 40 ns

-40 -50 -60
HYB3166160AT(L) 900 558 396 mW
HYB3165160AT(L) 756 468 324 mW
HYB3164160AT(L) 612 378 270 mW

7.2 mW standby (TTL)

3.24 mW standby (MOS)
720 µW standby for L-version

• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),

RAS

-only refresh, hidden refresh and self refresh (L-version only)

• 2 CAS / 1 WE byte control

• 8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT)

4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT)
2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT)

• 256 msec refresh period for L-versions

• Plastic Package: P-TSOPII-50 400 mil

Semiconductor Group 1Semiconductor Group 6.97

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabric ated on
an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performanc e and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address input s permit the HYB 3164(5)160AT to be packaged in a 400
mil wide TSOP-50 package. These packages provide high s ystem bit densities and are compatible
with co mmonly u sed automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts
(L-version) have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information
Type Ordering

Package Descriptions

Code

8k-refresh versions:

HYB 3164160AT-40 P-TSOPII-50 400 mil DRAM (access time 40 ns)
HYB 3164160AT-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3164160AT-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)
HYB 3164160ATL-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3164160ATL-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)

4k-refresh versions:

HYB 3165160AT-40 P-TSOPII-50 400 mil DRAM (access time 40 ns)
HYB 3165160AT-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3165160AT-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)
HYB 3165160ATL-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3165160ATL-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)

2k-refresh versions:

HYB 3166160AT-40 P-TSOPII-50 400 mil DRAM (access time 40 ns)
HYB 3166160AT-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3166160AT-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)
HYB 3166160ATL-50 P-TSOPII-50 400 mil DRAM (access time 50 ns)
HYB 3166160ATL-60 P-TSOPII-50 400 mil DRAM (access time 60 ns)

Semiconductor Group 2

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

Pin Configuration

VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.

A0
A1
A2
A3
A4
A5
VCC

P-TSOPII-50 (400 mil)

O

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

.

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
VSS

.

LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS

* Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L)
** Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L)

Pin Names

A0-A12 Address Inputs for 8k-refresh version HYB 3164160AT(L)
A0-A11 Address Inputs for 4k-refresh version HYB 3165160AT(L)
A0-A10 Address Inputs for 2k-refresh version HYB 3166160AT(L)
RAS
OE
I/O1-I/O16 Data Input/Output

,LCAS Column Address Strobe

UCAS
WE
Vcc Power Supply ( + 3.3V)
Vss Ground

Row Address Strobe
Output Enable

Read/Write Input

Semiconductor Group 3

TRUTH TABLE

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

FUNCTION RAS LCAS UCAS WE OE ROW

ADD
Standby H H - X H - X X X X X High Impedance
Read:Word L L H H L ROW COL Data Out
Read:Lower Byte L L H H L ROW COL Lower Byte:Data Out

Read:Upper Byte L H L H L ROW COL Lower Byte:High-Z

Write:Word
(Early-Write)

Write:Lower Byte
(Early-Write)

Write:Upper Byte
(Early Write)

Read-Modify­Write

Fast Page Mode
Read (Word)

Fast Page Mode
Read (Word)

1st

Cycle

2nd

Cycle

L L L L X ROW COL Data In

L L H L X ROW COL Lower Byte:Data Out

L H L L X ROW COL Lower Byte:High-Z

L L L H - L L - H ROW COL Data Out, Data In

L H - L H - L H L ROW COL Data Out

L H - L H - L H L n/a COL Data Out

COL
ADD

I/O1-

I/O16

Upper-Byte:High-Z

Upper Byte:Data Out

Upper-Byte:High-Z

Upper Byte:Data Out

Fast Page Mode
Early Write(Word)

Fast Page Mode
Early Write(Word)

Fast Page Mode
RMW

Fast Page Mode
RMW

RAS only refresh L H H X X ROW n/a High Impedance
CAS-before-RAS

refresh
Test Mode Entry H - L L L L X X n/a High Impedance
Hidden Refresh

(Read)
Hidden Refresh

(Write)

1st

Cycle

2nd

Cycle

1st

Cycle

2st

Cycle

L H - L H - L L X ROW COL Data In

L H - L H - L L X n/a COL Data In

L H - L H - L H - L L - H ROW COL Data Out, Data In

L H - L H - L H - L L - H n/a COL Data Out, Data In

H - L L L H X X n/a High Impedance

L-H-

L

L-H-

L

L L H L ROW COL Data Out

L L L X ROW COL Data In

Semiconductor Group 4

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

UCAS
LCAS

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10
A11
A12

WE

.

&

.

No. 2 Clock

Generator

Column

9

13 13

Address

Buffer(9)

Refresh

Controller

Refresh

Counter (13)

13

Row

Address

Buffers(13)

I/O1 I/O2

Data in
Buffer

Row

Decoder

16

9

8192

I/O16

Data out

Buffer

16

Column
Decoder

Sense Amplifier

I/O Gating

512

x16

Memory Array

8192x512x16

OE

16

RAS

Block Diagram for HYB 3164160AT(L)

Semiconductor Group 5

No. 1 Clock

Generator

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

UCAS
LCAS

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10
A11

WE

.

&

.

No. 2 Clock

Generator

Column

10

12 12

Address

Buffer(10)

Refresh

Controller

Refresh

Counter (12)

12

Row

Address

Buffers(12)

I/O1 I/O2

Data in
Buffer

Row

Decoder

16

10

4096

I/O16

Data out

Buffer

16

Column

Decoder

Sense Amplifier

I/O Gating

1024

x16

Memory Array

4096x1024x16

OE

16

No. 1 Clock

RAS

Block Diagram for HYB 3165160AT(L)

Semiconductor Group 6

Generator

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

UCAS
LCAS

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10

WE

.

&

.

No. 2 Clock

Generator

Column

11

11 11

Address

Buffer(11)

Refresh

Controller

Refresh

Counter (11)

11

Row

Address

Buffers(11)

I/O1 I/O2

Data in
Buffer

Row

Decoder

16

11

2048

I/O16

Data out

Buffer

16

Column

Decoder

Sense Amplifier

I/O Gating

2048

x16

Memory Array

2048x2048x16

OE

16

RAS

Block Diagram for HYB 3166160AT(L)

Semiconductor Group 7

No. 1 Clock

Generator

HYB3164(5/6)160AT(L)-40/-50/-60

4M x 16-DRAM

Absolute Maximum Ratings

Operating temperature range.............. .......................... ............................... .......................0 to 70 °C

Storage temperature range.............. ........ ........ ........ ........ ........ ........ ........ ........ ........ ...– 55 to 150 °C

Input/output volt age...... ............ ............ ............ ............ ............ ............ ....-0.5 to min (Vcc+0. 5,4.6) V

Power supply voltage....................................................................................................-0.5V to 4.6 V

Power dissipation..... .... .... .... .... ...... .... .... .... ...... .... .... .... .... ...... .... .... .... ...... .... .... .... .... ...... .... ..... ..1.3 W

Data out current (short circuit)............... .............. ... .. .. .............. .............. .. .............. .............. ....50 mA

Note

Stresses above those list ed under „Absolute M a ximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.

DC Characteristics

T

= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V

A

Parameter Symbol Limit Values Unit Note

Input high voltage
Input low voltage
Output high voltage (LVTTL)

Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)

Output „L“level voltage (Iout = +2mA)
Output high voltage (LVCMOS)

Output „H“ level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)

Output „L“ level voltage (Iout = +100uA)
Input leakage current,any input

(0 V < Vin < Vcc , all other pins = 0 V

Output leakage current

(DO is disabled, 0 V < Vout < Vcc )

V
V
V

V

V

V

I

I

IH

IL

OH

OL

OH

OL

I(L)

O(L)

min. max.

2.0 Vcc+0.3 V 1)
– 0.3 0.8 V 1)

2.4 – V

– 0.4 V

Vcc-0.2 - V

- 0.2 V

– 2 2 µA

– 2 2 µA

Semiconductor Group 8