Siemens HYB314405BJ-50, HYB314405BJ-60, HYB314405BJ-70, HYB314405BJL-50, HYB314405BJL-60 Datasheet

1M x 4-Bit Dynamic RAM
(Hyper Page Mode (EDO) version)

Advanced Information

• 1 048 576 words by 4-bit organization

• 0 to 70 ˚C operating temperature

• Hyper Page Mode - EDO

• Performance:

HYB 314405BJ/BJL-50/-60/-70

-50 -60 -70

t
t
t
t
t

RAC

CAC

AA

RC

HPC

RAS access time 50 60 70 ns
CAS access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 89 104 124 ns
Hyper page mode (EDO)

20 25 30 ns

cycle time

• Single + 3.3 V (± 0.3 V) supply

• Low power dissipation

max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
max. 198 mW active (-70 version)

• Standby power dissipation:

7.2 mW max. standby (LVTTL)

3.6 mW max. standby (LVCMOS)
720 µW max. standby (LVCMOS) for Low Power Version

• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,

hidden refresh and test mode capability

• All inputs and outputs LVTTL compatible

• 1024 refresh cycles / 16 ms

• 1024 refresh cycles / 128 ms for Low Power Version

• Plastic Packages: P-SOJ-26/20-5 with 300 mil width

Semiconductor Group 1 4.96

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

The HYB 314405BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by
4-bit. The HYB 314405BJ/BJL utilizes CMOS silicon gate process as well as advances circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314405BJ/BJL to be packed in a standard plastic P-SOJ-26/20
package. This package size provides high system bit densities and is compatible with commonly
used automatic testing and insertion equipment. System oriented features include single + 3.3 V
(± 0.3 V) power supply, direct interfacing with high performance logic device families.

Ordering Information
Type Ordering Code Package Descriptions

HYB 314405BJ-50 Q67100-Q2122 P-SOJ-26/20-5 3.3 V EDO-DRAM

(access time 50 ns)

HYB 314405BJ-60 Q67100-Q2124 P-SOJ-26/20-5 3.3 V EDO-DRAM

(access time 60 ns)

HYB 314405BJ-70 Q67100-Q2126 P-SOJ-26/20-5 3.3 V EDO-DRAM

(access time 70 ns)

HYB 314405BJL-50 on request P-SOJ-26/20-5 3.3 V Low Power EDO-DRAM

(access time 50 ns)

HYB 314405BJL-60 on request P-SOJ-26/20-5 3.3 V Low Power EDO-DRAM

(access time 60 ns)

HYB 314405BJL-70 on request P-SOJ-26/20-5 3.3 V Low Power EDO-DRAM

(access time 70 ns)

Semiconductor Group 2

Pin Configuration

(top view)

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

P-SOJ-26/20-5

Pin Names

A0-A9 Address Input
RAS Row Address Strobe
CAS Column Address Strobe
WE Read/Write Input
OE Output Enable
I/O1 - I/O4 Data Input/Output

V

CC

V

SS

Power Supply (+ 3.3 V)
Ground (0 V)

N.C. No Connection

Semiconductor Group 3

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

Block Diagram

Semiconductor Group 4

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 ˚C

Storage temperature range......................................................................................– 55 to + 150 ˚C

Input/output voltage .....................................................................................................– 1 to + 4.6 V

Power Supply voltage..................................................................................................– 1 to + 4.6 V

Data out current (short circuit) ................................................................................................50 mA

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC Characteristics

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

Condition

1)

1)

1)

1)

1)

2) 3)4)

Input high voltage
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
CMOS Output high voltage (I
CMOS Output low voltage (

= – 2 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

I

= 100 µA) V

OUT

Input leakage current, any input
(0 V <

V

< VCC + 0.3 V, all other input = 0 V)

in

Output leakage current, any input
(DO is disabled, 0 V < V

V

Average

supply current

CC

< VCC + 0.3 V)

OUT

-50 version

-60 version

-70 version

V

I

I

I

IH

IL

OH

OL

OH

OL

I(L)

I(L)

CC1

min. max.

2.0 VCC + 0.5 V
– 1.0 0.8 V

2.4 – V
– 0.4 V

V

– 0.2 – V

CC

– 0.2 V
– 10 10 µA

– 10 10 µA

mA
–
–
–

70
60
55

Standby VCC supply current
(RAS = CAS = WE = VIH)

V

Average

supply current during RAS-only

CC

refresh cycles -50 version

-60 version

-70 version

Average VCC supply current during hyper page
mode (EDO) operation

-50 version

-60 version

-70 version

Semiconductor Group 5

I

I

I

CC2

CC3

CC4

–2mA–

mA
–
–
–

70
60
55

mA

–
–
–

70
60
55

2)4)

2) 3)4)

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

DC Characteristics (cont’d)

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

min. max.

Condition

Standby VCC supply current
(RAS = CAS = WE = VCC – 0.2 V)

Average

V

supply current during

CC

CAS before RAS refresh mode

-50 version

-60 version

-70 version

For Low Power Version only:
Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE = VCC – 0.2 V or 0.2 V,
A0 to A10 = VCC – 0.2 V or 0.2 V;
DI = VCC – 0.2 V or 0.2 V or open,

t

= 125 µs, t

RC

AC Characteristics

T

= 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter

RAS

= t

min = 1 µs)

RAS

5)6)

Symbol

I

I

I

CC5

CC6

CC7

–1

200

–
–
–

70
60
55

mA

µA1)L-version

mA

2)4)

– 250 µA–

Limit Values Unit

Note

Common Parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time t
RAS to column address delay

time

t
t
t
t

t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

-50 -60 -70

min. max. min. max. min. max.

89 – 104 – 124 – ns
35 – 40 – 50 – ns
50 10 k 60 10 k 70 10 k ns
8 10 k 10 10 k 12 10 k ns
0–0–0–ns
8–10–10–ns
0–0–0–ns
8–10–12–ns
12 37 14 45 14 53 ns
10 25 12 30 12 35 ns

Semiconductor Group 6

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

AC Characteristics (cont’d)

T

= 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter

RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall)
Refresh period
Refresh period for L-version

5)6)

Symbol

RSH

CSH

CRP

t

T

t

REF

t

REF

Read Cycle

Access time from RAS t
Access time from

CAS t

Access time from column

t

RAC

CAC

AA

address

Limit Values Unit

Note

-50 -60 -70

min. max. min. max. min. max.

13 15 – 17 – ns
50 60 – 70 – ns
5–5–5–ns
1 501 501 50ns7
– 16– 16– 16ms
– 128 – 128 – 128 ms

– 50 – 60 – 70 ns 8, 9
– 13 – 15 – 17 ns 8, 9
– 25 – 30 – 35 ns 8,10

OE access time t
Column address to

RAS lead

time
Read command setup time
Read command hold time
Read command hold time

referenced to

RAS
CAS to output in low-Z t
Output buffer turn-off delay
Output buffer turn-off delay from

OE
Data to
Data to

CAS low delay t

OE low delay t
CAS high to data delay t
OE high to data delay t

Write Cycle

OEA

t

RAL

t

RCS

t

RCH

t

RRH

CLZ

t

OFF

t

OEZ

DZC

DZO

CDD

ODD

– 13– 15– 17ns
25 – 30 – 35 – ns

0–0–0–ns
0–0–0–ns11
0–0–0–ns11

0–0–0–ns8
0 130 150 17ns12
0 130 150 17ns12

0–0–0–ns13
0–0–0–ns13
10 – 13 – 15 – ns 14
10 – 13 – 15 – ns 14

Write command hold time t
Write command pulse width

WCH

t

WP

8–10–10–ns
8–10–10–ns

Semiconductor Group 7

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

AC Characteristics (cont’d)

T

= 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter

Write command setup time t
Write command to
Write command to

RAS lead time t

CAS lead time t
Data setup time
Data hold time

5)6)

Symbol

WCS

RWL

CWL

t

DS

t

DH

Read-modify-Write Cycle

Read-write cycle time t
RAS to WE delay time t
CAS to WE delay time t
Column address to

WE delay

RWC

RWD

CWD

t

AWD

time

Limit Values Unit

Note

-50 -60 -70

min. max. min. max. min. max.

0–0–0–ns15
13 – 15 – 17 – ns
13 – 15 – 17 – ns
0–0–0–ns16
8–10–12–ns16

118 – 138 – 162 – ns
64 – 77 – 89 – ns 15
27 – 32 – 36 – ns 15
39 – 47 – 54 – ns 15

OE command hold time t

OEH

10 – 13 – 15 – ns

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle

t

HPC

20 – 25 – 30 – ns

time
CAS precharge time t
Access time from

CAS

t

CP

CPA

8–10–10–ns
– 27– 32– 37ns7

precharge
Output data hold time
RAS pulse width in hyper page

t

COH

t

RAS

5–5–5–ns
50 200 k 60 200 k 70 200 k ns

mode
CAS precharge to RAS Delay t

RHCP

27 – 32 – 37 – ns

Hyper Page Mode (EDO) Read-modify-Write Cycle

Hyper page mode (EDO) read-

t

PRWC

58 – 68 – 77 – ns

write cycle time
CAS precharge to WE t

CPWD

41 – 49 – 56 – ns

Semiconductor Group 8