Siemens HYB314400BJ-50, HYB314400BJ-60 Datasheet

1M × 4-Bit Dynamic RAM

Advanced Information

• 1 048 576 words by 4-bit organization

• 0 to 70 °C operating temperature

• Fast Page Mode Operation

• Performance:

HYB 314400BJ-50/-60

-50 -60

RAC

CAC

RAS access time 50 60 ns CAS access time 13 15 ns Access time from address 25 30 ns Read/Write cycle time 95 110 ns Fast page mode cycle time 35 40 ns

• Fast access and cycle time Single + 3.3 V (± 0.3 V) supply with a built-in VBB generator

• Low power dissipation max. 252 mWactive (-50 version) max. 216 mWactive (-60 version)

• Standby power dissipation:

7.2 mW max. standby (LVTTL)

3.6 mW max. standby (LVCMOS)

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify write,

CAS-before-RAS refresh, RAS-only refresh,

hidden refresh and test mode capability

• All inputs and outputs LVTTL-compatible

• 1024 refresh cycles / 16 ms

• Plastic Packages: P-SOJ-26/20-2 with 300 mil width

Semiconductor Group 1 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

The HYB 314400BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 314400BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314400BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 3.3 V (± 0.3 V ) power supply, direct interfacing with high performance logic device families.

Ordering Information Type Ordering Code Package Descriptions

HYB 314400BJ-50 on request P-SOJ-26/20-2 300 mil 3.3 V DRAM (access time 50 ns) HYB 314400BJ-60 on request P-SOJ-26/20-2 300 mil 3.3 V DRAM (access time 60 ns)

Semiconductor Group 2 1998-10-01

P-SOJ-26/20-2

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

Pin Configuration

Pin Names

A0 - A9 Address Input

I/O1

I/O2

RAS

4 5

A1 A7

13 14

26 25 24 23 22

18 17 16 15

SPP02807

I/O4 I/O3 CAS OE

A8A0

A6 A5 A4

RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 - I/O4 Data Input/Output

Power Supply (+ 3.3 V) Ground (0 V)

N.C. No Connection

Semiconductor Group 3 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

WE CAS

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

No.2 Clock

Generator

Column

Address

Buffers (10)

Refresh

Controller

Refresh

Counter (10)

Row

Address

Buffers (10)

I/O1

Data In

Buffer

Row

Decoder

I/O2

1024

I/O3

I/O4

Data Out

Buffer

Column Decoder

Sense Amplifier

I/O Gating

1024

...

Memory Array

1024 1024x

...

RAS

No.1 Clock

Generator

SPB02831

Block Diagram

Semiconductor Group 4 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

Absolute Maximum Ratings

Operating temperature range ........................................................................................... 0 to 70 °C

Storage temperature range.................................................................................... – 55 to + 150 °C

Input/output voltage............................................................................ – 1 to min (VCC+ 0.5, 4.6) V

Power Supply voltage................................................................................................. – 1 to + 4.6 V

Data out current (short circuit) ............................................................................................... 50 mA

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns

Parameter Symbol Limit Values Unit Test

Condition

2, 3, 4

Input high voltage V Input low voltage V TTL Output high voltage (I TTL Output low voltage (I CMOS Output high voltage (I CMOS Output low voltage (I

= – 2 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

= 100 µA) V

OUT

Input leakage current, any input (0 V < VIN < VCC + 0.3 V, all other input = 0 V)

Output leakage current (DO is disabled, 0 < V

OUT

< VCC)

Average VCC supply current

-50 version

-60 version

I(L)

O(L)

CC1

min. max.

2.0 VCC+ 0.5 V – 1.0 0.8 V

2.4 – V – 0.4 V

– 0.2 – V

– 0.2 V – 10 10 µA

– 10 10 µA

mA – –

70 60

Standby VCC supply current

CC2

–2mA

(RAS = CAS = WE = VIH) Average VCC supply current during RAS-only

refresh cycles -50 version

-60 version

Average VCC supply current during fast page mode operation -50 version

-60 version

CC3

CC4

mA – –

70 60

mA – –

50 45

2, 4

2, 3, 4

Semiconductor Group 5 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

DC Characteristics (cont’d)

= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns

Parameter Symbol Limit Values Unit Test

min. max.

Standby VCC supply current

CC5

–1µA

(RAS = CAS = WE = VCC – 0.2 V) Average VCC supply current during

CC6

CAS-before-RAS refresh mode

-50 version

-60 version

– –

70 60

Capacitance

= 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz

Parameter Symbol Limit Values Unit

Condition

2, 4

Input capacitance (A0 to A9) C Input capacitance (RAS, CAS, WE, OE) C Output capacitance (IO1 to IO4) C

min. max.

–5pF –7pF –7pF

Semiconductor Group 6 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

AC Characteristics

= 0 to 70 °C, VCC = 3.3 V ± 0.3 V, tT = 5 ns

5, 6

Parameter Symbol Limit Values Unit Note

-50 -60

min. max. min. max.

Common Parameters

Random read or write cycle time t RAS precharge time t RAS pulse width t CAS pulse width t Row address setup time t Row address hold time t Column address setup time t Column address hold time t RAS to CAS delay time t RAS to column address delay time t RAS hold time t CAS hold time t CAS to RAS precharge time t Transition time (rise and fall) t Refresh period t

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

REF

95 – 110 – ns 35 – 40 – ns 50 10k 60 10k ns 13 10k 15 10k ns 0–0–ns 8–10–ns 0–0–ns 10 – 15 – ns 18 37 20 45 13 25 15 30 ns 13 15 – ns 50 60 – ns 5–5–ns 3 50 3 50 ns

– 16 – 16 ms

Read Cycle

Access time from RAS t Access time from CAS t Access time from column address t OE access time t Column address to RAS lead time t Read command setup time t Read command hold time t Read command hold time referenced to RAS t CAS to output in low-Z t Output buffer turn-off delay t Output buffer turn-off delay from OE t

RAC

CAC

OEA

RAL

RCS

RCH

RRH

CLZ

OFF

OEZ

– 50 – 60 ns – 13 – 15 ns – 25 – 30 ns – 13 – 15 ns 25 – 30 – ns 0–0–ns 0–0–ns 0–0–ns 0–0–ns 0 13 0 15 ns 0 13 0 15 ns

8, 9

8, 10

Semiconductor Group 7 1998-10-01

HYB 314400BJ-50/-60

3.3 V 1M × 4 DRAM

AC Characteristics (cont’d)

= 0 to 70 °C, VCC = 3.3 V ± 0.3 V, tT = 5 ns

5, 6

Parameter Symbol Limit Values Unit Note

-50 -60

min. max. min. max.

Data to OE low delay t CAS high to data delay t OE high to data delay t

DZO

CDD

ODD

0–0–ns 13 – 15 – ns 13 – 15 – ns

Write Cycle

Write command hold time t Write command pulse width t Write command setup time t Write command to RAS lead time t Write command to CAS lead time t Data setup time t Data hold time t Data to CAS low delay t

WCH

WCS

RWL

CWL

DZC

8–10–ns 8–10–ns 0–0–ns

13 – 15 – ns 13 – 15 – ns 0–0–ns 10 – 10 – ns 0–0–ns

Read-Modify-Write Cycle

Read-write cycle time t RAS to WE delay time t CAS to WE delay time t Column address to WE delay time t OE command hold time t

Fast Page Mode Cycle

Fast page mode cycle time t CAS precharge time t Access time from CAS precharge t RAS pulse width t CAS precharge to RAS delay t

Fast Page Mode Read-Modify-Write Cycle

Fast page mode read-write cycle time t CAS precharge to WE t

RWC

RWD

CWD

AWD

OEH

CPA

RAS

RHCP

PRWC

CPWD

131 – 150 – ns 68 – 80 – ns 31 – 35 – ns 43 – 50 – ns 13 – 15 – ns

35 – 40 – ns 10 – 10 – ns – 30 – 35 ns 50 200k 60 200k ns 30 – 35 – ns

71 – 80 – ns 48 – 55 – ns

Semiconductor Group 8 1998-10-01

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