Siemens HYB3116405BJ-70, HYB3116405BT-70, HYB3116405BTL-70, HYB3117405BJ-70, HYB3117405BT-70 Datasheet

3.3V 4M x 4-Bit EDO-Dynamic RAM

Advanced Information

4 194 304 words by 4-bit organization

•

0 to 70 °C operating temperature

•

Performance

•

HYB3116405BJ/BT(L) -50/-60/-70 HYB3117405BJ/BT(L) -50/-60/-70

-50 -60 -70

t

RAC

t

CAC

t

AA

t

RC

t

HPC

RAS

access time 50 60 70 ns access time 13 15 20 ns

CAS Access time from address 25 30 35 ns Read/Write cycle time 84 104 124 ns Hyper page mode (EDO)

20 25 30 ns

cycle time

Single + 3.3 V (± 0.3V ) supply

•

Low power dissipation

•

max. 396 active mW (HYB3117405BJ/BT-50) max. 363 active mW (HYB3117405BJ/BT-60) max. 330 active mW (HYB3117405BJ/BT-70) max. 360 active mW (HYB3116405BJ/BT-50) max. 324 active mW (HYB3116405BJ/BT-60) max. 288 active mW (HYB3116405BJ/BT-70)

7.2 mW standby (LV-TTL)

3.6 mW standby (LV-CMOS) 720 µW standby for L-version Output unlatched at cycle end allows two-dimensional chip selection

•

Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

•

Self Refresh and test mode Hyper page mode (EDO) capability

•

All inputs, outputs and clocks fully TTL-compatible

•

2048 refresh cycles / 32 ms for HYB3117405

•

4096 refresh cycles / 64 ms for HYB3116405 Plastic Package: P-SOJ-26/24-1 (300 mil)

•

P-TSOPII-26/24-1 (300mil)

Semiconductor Group 1 3.96

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

The HYB 3116(7)405BJ/BT(L) is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 3116(7)405BJ/BT(L) utilizes a submicron CMOS silicon ga te process technolog y, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(7)405BJ/BT(L) to be packaged in a standard SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device fam ilies.The HYB3116405BTL parts have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information Type Ordering Code Package Descriptions

HYB 3117405BJ-50 Q67100-Q1119 P-SOJ-26/24-1 300 mil DRAM (access time 50 ns) HYB 3117405BJ-60 Q67100-Q1120 P-SOJ-26/24-1 300 mil DRAM (access time 60 ns) HYB 3117405BJ-70 P-SOJ-26/24-1 300 mil DRAM (access time 70 ns) HYB 3117405BT-50 Q67100-Q1135 P-TSOPII-26/24-1 300 mil DRAM (access time 50 ns) HYB 3117405BT-60 Q67100-Q1136 P-TSOPII-26/24-1 300 mil DRAM (access time 60 ns) HYB 3117405BT-70 Q67100-Q1184 P-TSOPII-26/24-1 300 mil DRAM (access time 70 ns) HYB 3116405BJ-50 Q67100-Q1127 P-SOJ-26/24-1 300 mil DRAM (access time 50 ns) HYB 3116405BJ-60 Q67100-Q1128 P-SOJ-26/24-1 300 mil DRAM (access time 60 ns) HYB 3116405BJ-70 P-SOJ-26/24-1 300 mil DRAM (access time 70 ns) HYB 3116405BT-50 Q67100-Q1143 P-TSOPII-26/24-1 300 mil DRAM (access time 50 ns) HYB 3116405BT-60 Q67100-Q1144 P-TSOPII-26/24-1 300 mil DRAM (access time 60 ns) HYB 3116405BT-70 Q67100-Q1186 P-TSOPII-26/24-1 300 mil DRAM (access time 70 ns) HYB 3116405BTL-50 on reques t P-TSOPII-26/24-1 300 mil LP-DRAM (access time 50 ns) HYB 3116405BTL-60 on reques t P-TSOPII-26/24-1 300 mil LP-DRAM (access time 60 ns) HYB 3116405BTL-70 on reques t P-TSOPII-26/24-1 300 mil LP-DRAM (access time 70 ns)

Semiconductor Group 2

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Vcc I/O1 I/O2 WE RAS N.C.

A10 A0 A1 A2 A3 VCC

Pin Configuration

1 2 3 4 5 6

8 9 10 11 12 13

HYB3117405BJ/BT

26 25 24 23 22 21

19 18 17 16 15 14

Vss I/O4 I/O3 CAS OE A9

A8 A7 A6 A5 A4 Vss

P-SOJ-26/24-1 (300mil) P-TSOPII-26/24-1 (300mil)

Vcc I/O1 I/O2 WE RAS A11

A10 A0 A1 A2 A3 VCC

1 2 3 4 5 6

8 9 10 11 12 13

HYB3116405BJ/BT

26 25 24 23 22 21

19 18 17 16 15 14

Vss I/O4 I/O3 CAS OE A9

A8 A7 A6 A5 A4 Vss

Pin Names

A0 to A10 Row & Column Address Inputs for HYB3117405 A0 to A11 Row Address Inputs for HYB3116405 A0 to A9 Column Address Inputs for HYB3116405 RAS OE I/O1 -I/O4 Data Input/Output CAS WE

V

CC

V

SS

N.C. not connected

Row Address Strobe Output Enable

Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V)

Semiconductor Group 3

WE

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

I/O1 I/O2 I/O3 I/O4

A0

A1 A2 A3 A4 A5 A6 A7 A8 A9

A10

CAS

.

11

11 11

&

No. 2 Clock

Generator

Column

Address

Buffer(11)

Refresh

Controller

Refresh

Counter (11)

11

Row

Address

Buffers(11)

Data in Buffer

Row

Decoder

4

11

2048

Data out

Buffer

4

Column

Decoder

Sense Amplifier

I/O Gating

2048

x4

Memory Array

2048x2048x4

OE

4

No. 1 Clock

RAS

Block Diagram for HYB3117405

Semiconductor Group 4

Generator

WE

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

I/O1 I/O2 I/O3 I/O4

A0

A1 A2 A3 A4 A5 A6 A7 A8 A9

A10 A11

CAS

.

10

12 12

&

No. 2 Clock

Generator

Column

Address

Buffer(10)

Refresh

Controller

Refresh

Counter (12)

12

Row

Address

Buffers(12)

Data in Buffer

Row

Decoder

4

10

4096

Data out

Buffer

4

Column

Decoder

Sense Amplifier

I/O Gating

1024

x4

Memory Array

4096x1024x4

OE

4

No. 1 Clock

RAS

Block Diagram for HYB3116405

Semiconductor Group 5

Generator

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 °C

Storage temperature range.........................................................................................– 55 to 150 °C

Input/output voltage................................................................................-0.5 to min(Vcc+0.5, 4.6) V

Power supply voltage.................................................................................................- 0.5 V to 4.6 V

Power dissipation....................................................................................................................0.5 W

Data out current (short circuit)................................................................................................50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause perm anent dama ge of the device. Exposure to absolute maximu m rating conditions for extended perio ds may affect device reliability.

DC Characteristics

= 0 to 70 °C,

T

A

(values in brackets for HYB3117405)

V

SS

= 0 V,

= 3.3 V ± 0.3 V, tT = 2 ns

V

CC

Parameter Symbol Limit Values Unit Test

mA mA mA

Condition

1)

2) 3) 4)

Input high voltage Input low voltage TTL Output high voltage ( TTL Output low voltage (

I

OUT

CMOS Output high voltage ( CMOS Output low voltage ( Input leakage current

(0 V ≤

≤ Vcc + 0.3V, all other pins = 0 V)

V

IH

Output leakage current (DO is disabled, 0 V ≤

supply current:

Average

V

CC

V

OUT

= – 2 mA)

= 2 mA)

= –100 uA)

I

OUT

= 100 uA)

I

OUT

≤ Vcc + 0.3V)

-50 ns version

-60 ns version

-70 ns version

V V V V V V I

I

IH

IL

OH

OL

OH

OL

I(L)

O(L)

CC1

min. max.

2.0 Vcc+0.5 V – 0.5 0.8 V

2.4 – V –0.4V VCC-0.2 – V –0.2V – 10 10 µA

– 10 10 µA

– – –

100(120) 90 (110) 80 (100)

(RAS

, CAS, address cycling, tRC = tRC min.)

Standby

supply current (RAS =CAS=

V

CC

)

V

IH

Semiconductor Group 6

I

CC2

–2mA–

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

DC Characteristics

= 0 to 70 °C,

T

A

(values in brackets for HYB3117405)

V

SS

= 0 V,

= 3.3 V ± 0.3 V, tT = 2 ns

V

CC

Parameter Symbol Limit Values Unit Test

mA mA mA

Condition

2) 4)

Average

supply current, during RAS-only

V

CC

refresh cycles: -50 ns version

-60 ns version

-70 ns version

I

CC3

min. max.

– – –

100(120) 90 (110) 80 (100)

(RAS

cycling: CAS =

supply current, during hyper page

Average

V

CC

mode EDO): -50 ns version

(RAS

=

, CAS, address cycling, tPC = t

V

IL

supply current

Standby

(RAS Average

V

CC

= CAS =

supply current, during CAS-

V

CC

V

CC

before-RAS refresh mode: -50 ns version

, tRC = tRC min.)

V

IH

– 0.2 V)

-60 ns version

-70 ns version

PC

-60 ns version

-70 ns version

min.

I

CC4

– – –

70 (70) 55 (55) 45 (45)

mA mA mA

2) 3) 4)

)

I

CC5

CC6

–1

200

– – –

100(120) 90 (110) 80 (100)

mA µA

mA mA mA

1) L-version

2) 4)

(RAS

, CAS cycling, tRC = t

Average Self Refresh Current

(CBR cylce with tRAS>TRASSmin., CAS held low, WE

=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

RC

min.)

I

CC7

_1

250

mA µAL-version

Capacitance

= 0 to 70 °C,

T

A

= 3.3 V ± 0.3V, f = 1 MHz

V

CC

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A10, A11) Input capacitance (RAS

, CAS, WE, OE)

I/O capacitance (I/O1 - I/O4)

C

I1

C

I2

C

IO

–5pF –7pF –7pF

Semiconductor Group 7

HYB 3116(7)405BJ/BT(L) -50/-60/-70

3.3V 4Mx4-DRAM

AC Characteristics

= 0 to 70 °C,

T

A

5 )6)

= 5 V ± 10 %, tT = 2 ns

V

CC

Parameter

common parameters

Random read or write cycle time t

precharge time t

RAS RAS

pulse width t pulse width t

CAS Row address setup time t Row address hold time t Column address setup time t Column address hold time t

to CAS delay time t

RAS RAS

to column address delay t hold time t

RAS CAS

hold time t to RAS precharge time t

CAS Transition time (rise and fall) t Refresh period for HYB5116405 t Refresh period for HYB5117405 t Refresh period for L-version t

Symbol

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

T

REF

16E

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

84 – 104 – 124 – ns 30 – 40 – 50 – ns 50 10k 60 10k 70 10k ns 8 10k 10 10k 12 10k ns 0–0–0–ns 8–10–10–ns 0–0–0–ns 8–10–12–ns 12 37 14 45 14 53 ns 10 25 12 30 12 35 ns 13 15 – 17 – ns 40 50 – 60 – ns 5–5–5–ns 150150150ns7 –64–64–64ms –32–32–32ms – 256 – 256 – 256 ms

Read Cycle

Access time from RAS Access time from CAS Access time from column address t

access time t

OE Column address to RAS

lead time t Read command setup time t Read command hold time t Read command hold time

t t

t

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

–50–60–70ns8, 9 –13–15–17ns8, 9 –25–30–35ns8,10 –13–15–17ns 25 – 30 – 35 – ns 0–0–0–ns 0–0–0–ns11 0–0–0–ns11

referenced to RAS CAS

to output in low-Z t

CLZ

0–0–0–ns8

Semiconductor Group 8