GSM-Tester (CMU200 or 4400S incl. Options)
PC-incl. Monitor, Keyboard and Mouse
Bootadapter 2000/2002 (L36880-N9241-A200)
Adapter cable for Bootadapter due to
Troubleshooting Frame A31 (F30032-P588-A1)
Power Supply
Spectrum Analyser
Active RF-Probe incl. Power Supply
Oscilloscope incl. Probe
RF-Connector (N<>SMA(f))
Power Supply Cables
Dongle (F30032-P28-A1) if USB-Dongle is used a special driver for NT is required
BGA Soldering equipment
Reference: Equipment recommendation V1.6
(downloadable from the technical support page)
new Lumberg connector (F30032-P226-A2)
Technical Documentation02/2006
TD_Repair_L3_Theory of Operation_A31_R1.1.pdf Page 6 of 45
The radio part is realizes the conversion of the GMSK-HF-signals from the antenna to the
baseband and vice versa.
In the receiving direction, the signals are split in the I- and Q-component and fed to the A/Dconverter of the logic part. In the transmission direction, the analog GMSK-signal from the
baseband section is converted back to a digital signal and adapted to the following
modulator. This digital modulator injects the modulation into the LO1 control loop via fast
divider switching. This modulated LO1 signal is divided by 2 or 4 to get the DCS1800 /
PCS1900 or GSM850/EGSM900 TX frequency. To reach the output power the signal is
then amplified in the power amplifier.
The RF-part is designed for Quad band operation (GSM850, EGSM900, DCS1800,
PCS1900) and consists of the following components:
• SMARTi SD2 chip set PMB6271 with the following functionality:
26MHz DCXO (Digital Controlled Crystal Oscillator) reference oscillator
PLL for local oscillator LO1
Integrated loop filter for the RF synthesizer
LO1-VCO
Direct conversion receiver with channel filtering
Sigma Delta Modulator
• Transmitter power amplifier (PA) ACPM-7863
• Front-End-Module (FEM) M064 including RX-/TX-switch and GSM900/DCS1800/
PCS1900 receiver SAW-filters for international version
•Front-End-Module (FEM) M026 including RX-/TX-switch and GSM850/EGSM900/
DCS1800/PCS1900 receiver SAW-filters for LAM versio
Technical Documentation02/2006
n
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The voltage regulator for the RF-part is located inside the ASIC D361.It generates the
required 2,8V “RF-operating voltages” named VDD_RF1 and VDD_RF2 for the SD2..The
voltage regulator is activated as well as deactivated via SLEEPQ
VCXOEN_UC
(M4)provided by the EGOLDlite. The temporary deactivation is used to extend
the stand by time.
Circuit diagram
(TDMA-Timer R11)and
VDD_RF1
VDD_RF2
5.3 SMARTi SD2 PMB6271
5.3.1 Integrated 26MHz DCXO reference oscillator
The 26 MHz signal is created by an integrated controlled DCXO Z5001. For temperature
measurements of the DCXO a temperature-dependent resistance is used R4001. The
frequency of the reference oscillator can be adjusted by the baseband via three wire bus
programming. Three active buffer stages are included in SMARTi SD2 to give sufficient
isolation between the baseband-chip (or any other RF / BB chip) and the RF-circuit.
Circuit diagram
SD2
Technical Documentation02/2006
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The local oscillator (LO1) consists of a 23-bit fractional-N PLL and the VCO, both integrated
in the SMARTi SD2 and a loop filter which is internal as well. The PD frequency is 26MHz.
An LO2 is not required. The frequency range of the VCO is 3420MHz to 3980MHz for the
triple-band phone GSM900/1800/1900. Therefore the LO frequency is 4 times the RX/TX
frequency for GSM850/GSM 900 and 2 times RX/TX frequency for DCS1800/PCS1900.
The VCO has 1024 bands that are chosen by the ‘binary automatic band select’ BABS at
the PLL start with the Channel 2 programming word. After the BABS the ‘open loop gain
adjust’ OLGA sets two charge pump currents and measures the corresponding VCO
frequency. So the system knows the result of a loop gain relevant parameter and adjusts
the loop gain automatically by the programmable charge pump current. After this adjustment
the analog locking starts. The worst case specified lock time is 200µs. So the synthesizer is
capable of GPRS class 12. Due to the automatic band select with the fine VCO bands the
tune voltage stays normally quite constant over the channels which enlarges the KVCO
flatness.
The GMSK modulation for TX is injected by adapting the divider value of the PLL very fast
to get the desired modulation. The time constant of the internal loop filter is measured
before each burst as well and tolerances are compensated to get a good modulation.
5.3.3 Receiver
The SMARTi SD2 consists of a direct conversion receiver for GSM850/900/1800/1900. The
GSM850/900/1800/1900 LNAs with balanced inputs are integrated into the chip. The LNA
gain is switchable. For the “High Gain” state the mixers are optimised for conversion gain
and noise figure, in the “Low Gain” state the mixers are optimised to large signal behaviour
for operation at a high input level. The gain step for the LNA is approximately 34dB for all
four bands. There is another fixed gain precision amplifier with 6dB that will be switched on
at reference sensitivity level (-90dBm input level) to avoid accuracy losses at very low input
levels.
A quadrature demodulator converts the amplified RF signal to the final orthogonal output
signals at baseband frequency. The orthogonal LO signals are generated by a divider by 4
for the GSM850 and GSM900 band and by a divider by 2 for the GSM1800 and GSM1900
band.
The resulting in-phase and quadrature signals are fed into the baseband low pass filters
providing sufficient suppression of blocking signals as well as of adjacent channel
interferers and ensures the ADC's anti-aliasing requirements at 13MHz clock rate. A
programmable gain stage for the correction of gain tolerances in thirteen 1dB steps (6dB…+6dB) and the adaptation of the output signals to the baseband ADC's input dynamic
range is implemented.
Technical Documentation02/2006
TD_Repair_L3_Theory of Operation_A31_R1.1.pdf Page 11 of 45
The IQ receiver signals are fed into the AD converters of the EGOLDlite and the differential
baseband signals are digitalised separately for the I and Q path. On EGOLDlite both the
digital and analogue baseband filters of the I/Q-interface are implemented. The analogue
part of the baseband receive section comprises anti-aliasing pre-filters for in-phase and
quadrature components and Σ∆ analogue-to-digital converters with approximately 12 bit
(standard mode) and 14 bit (enhanced mode) resolution with 2 Vpp max differential input
voltage. The complete ADC functionality comprises the ADC and the digital baseband
receive filters.
The baseband receive filters are digital multi rate decimation low pass filters. They consist
of several filter stages with decimations taking place as early as possible. The last filter
stage is an adaptive switchable linear-phase FIR filter. Depending on the level of adjacent
channel interference it selects a filter with appropriate frequency transfer characteristic for
improved channel filtering. Furthermore, the filter coefficients of the last FIR filter stage are
programmable for optimisation purposes.
5.3.4 Transmitter (Sigma Delta)
The innovative part of the SMARTi SD2, the digital modulation principle, is as well
established in the SMARTi SD2. Basis is the fact, that the GMSK modulation can be
considered to be a phase modulation in its origin. This can be achieved by controlling the
frequency of a VCO. There are various methods to do so. One of the smartest is to use a
PLL for this application. The advantage of this method is a low effort in hardware and that a
lot of unwanted spurs are not generated e.g. carrier- or sideband spurs. Therefore a
calibration of the I/Q baseband signals to achieve sufficient sideband- and carrier
suppression is not required any longer.
The I/Q signals are provided by the base band chipset with a 1.0V DC offset and amplitude
of 0.94Vpp over balanced lines. The first step now is to convert the base band signal from
analog to digital. After that the signal passes a digital gaussian filter and is fed to the mash
modulator. This network is calculating the divider settings of the PLL. The VCO is oscillating
from 3.42 GHz to 3.98 GHz. This is twice the frequency for the high band, so a division by 2
is necessary for DCS/PCS operation and a division by 4 for GSM 850/900 operation.
The output signal of the modulator is buffered with two different stages for GSM and
DCS/PCS. The output stage is a single ended nominal 50Ω stage with about 3.5dBm output
power, so no matching elements between SMARTi and PA are necessary.
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Internal/External <> Receiver/Transmitter
The A31 mobile have two antenna switches.
a) The mechanical antenna switch for the differentiation between the internal and
external antenna which is used
b) The electrical antenna switch, for the differentiation between the receiving and
transmitting signals.
To activate the correct tx pathes of this diplexer, the EGOLDlite signals RF_FE_DTR_GSM
and RF_FE_DTR_DCS are required.
Internal/External antenna switch
to / from diplexer
to EGOLDlite
only for RF adjustments on the board.
External
Internal
Technical Documentation02/2006
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