SGS Thomson Microelectronics ST72T121J4, ST72T121J2, ST72121J4, ST72121J2, ST72121 Datasheet

September 1999 1/92

ST72E121

ST72T121

8-BIT MCU WITH 8 TO 16K OTP/EPROM,

384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

DATASHEET

■ User Program Memory (OTP/EPROM):

8 to16K bytes

■ Data RAM: 384 to512 bytesincluding 256 bytes

of stack

■ Master Resetand Power-On Reset

■ Low Voltage Detector (LVD) Reset option

■ Run andPower Saving modes

■ 32 multifunctionalbidirectional I/O lines:

– 9 programmable interrupt inputs
– 4 high sinkoutputs

– 13 alternate functions
– EMI filtering

■ Software or Hardware Watchdog (WDG)

■ Two 16-bit Timers, each featuring:

– 2 Input Captures

1)

– 2 Output Compares

1)

– External Clock input (on Timer A)
– PWM and Pulse Generator modes

■ Synchronous Serial Peripheral Interface (SPI)

■ Asynchronous Serial Communications Interface

(SCI)

■ 8-bit Data Manipulation

■ 63 basic Instructions and 17 main Addressing

Modes

■ 8 x8 Unsigned Multiply Instruction

■ True BitManipulation

■ Complete Development Support on DOS/

WINDOWSTMReal-Time Emulator

■ Full Software Package on DOS/WINDOWS

TM

(C-Compiler, Cross-Assembler, Debugger)

Note: 1. One only on Timer A.

Device Summary

Note: The ROM versions are supportedby the ST72124 family.

TQFP44

PSDIP42

CSDIP42W

(See ordering information at the end of datasheet)

Features ST72T121J2 ST72T121J4

Program Memory - bytes 8K 16K
RAM (stack) - bytes 384 (256) 512 (256)
Peripherals Watchdog, Timers, SPI, SCI and optional Low Voltage Detector Reset
Operating Supply 3 to 5.5 V
CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range - 40°C to + 125°C

Package TQFP44 - SDIP42
OTP/EPROM Devices ST72T121J4/ST72E121J4

1

Rev. 1.7

2/92

Table of Contents

92

1 GENERAL DESCRIPTION . . . . . . ................................................ 4

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................4

1.2 PIN DESCRIPTION . . ..................................................... 5

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . ......... 7

1.4 MEMORY MAP . . . .. . . .. . ................................................8

1.5 OPTION BYTE . . . . .. . ................................................... 11

2 CENTRAL PROCESSING UNIT . . ............................................... 12

2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................12

2.2 MAIN FEATURES . . . .. . . . . . . . . . . . . .. . . . . . . .............................. 12

2.3 CPU REGISTERS . . . .................................................... 12

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . .. . . . . . . ...........15

3.1 CLOCK SYSTEM . . . . . .. . . . . . . ...........................................15

3.1.1 General Description . . . .. . ...........................................15

3.1.2 External Clock . . . . . . . . . . . . . ........................................15

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 16

3.2.1 Introduction . . . .................................................... 16

3.2.2 External Reset . . . . . . ...............................................16

3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 16

3.2.4 Low Voltage DetectorReset . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 INTERRUPTS . . . .. . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . 18

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . ........ 21

3.4.1 Introduction . . . .................................................... 21

3.4.2 Slow Mode . . .. . . . . . . . . . . . . . . . . . . . ................................. 21

3.4.3 Wait Mode . . . . . . . . . . . . . . .. ........................................ 21

3.4.4 Halt Mode . . . . . .................................................... 22

3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . ..................................23

4 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 24

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . ........................................... 24

4.1.1 Introduction . . . .................................................... 24

4.1.2 Functional Description . . . . ........................................... 24

4.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . ........................... 25

4.1.4 Register Description . . . . . . ........................................... 28

4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 30

4.2.1 Introduction . . . .................................................... 30

4.2.2 Main Features . .. . . . ...............................................30

4.2.3 Functional Description . . . . ........................................... 30

4.2.4 Hardware Watchdog Option . .. . . . . . . . ................................. 31

4.2.5 Low Power Modes . . . ............................................... 31

4.2.6 Interrupts . . . . . .. . . . . . . . . . . . . . . . . . ................................. 31

4.2.7 Register Description . . . . . . ........................................... 31

4.3 16-BIT TIMER . . . . . . . .. . . . . . . . . . ........................................ 33

4.3.1 Introduction . . . .................................................... 33

4.3.2 Main Features . .. . . . ...............................................33

4.3.3 Functional Description . . . . ........................................... 33

4.3.4 Low Power Modes . . ............................................... 44

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Table of Contents

4.3.5 Interrupts . . .. . .................................................... 44

4.3.6 Register Description . . . . . . ........................................... 45

4.4 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . 50

4.4.1 Introduction . . . .................................................... 50

4.4.2 Main Features . .. . . . ...............................................50

4.4.3 General Description . . . .. . ........................................... 50

4.4.4 Functional Description . . . . ........................................... 52

4.4.5 Low Power Modes . . . ............................................... 57

4.4.6 Interrupts . . . . . .. . . . . . . . . . . . . . . . . . ................................. 57

4.4.7 Register Description . . . . . . ........................................... 58

4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . .. . . . . . . . . . . . . . . . ...........62

4.5.1 Introduction . . . .................................................... 62

4.5.2 Main Features . .. . . . ...............................................62

4.5.3 General description . . . . . .. . . . . . . . . . .. . . .. . . . . . . . . . . . . . .. . . .. . . . . . . . . 62

4.5.4 Functional Description . . . . ........................................... 64

4.5.5 Low Power Modes . . . ............................................... 71

4.5.6 Interrupts . . .. . .................................................... 71

4.5.7 Register Description . . . . . . ........................................... 72

5 INSTRUCTION SET .. . . . . . . . . . . . . . . . . ........................................ 75

5.1 ST7 ADDRESSING MODES . .. . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 75

5.1.1 Inherent . . . . . . . . . . . ...............................................76

5.1.2 Immediate . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . 76

5.1.3 Direct . ........................................................... 76

5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . ........................... 76

5.1.5 Indirect (Short, Long) . . . . .. . . . . . . . . . .. . . .. . . . . . .. .. . . .. . . .. . . . . . . . . . . 76

5.1.6 Indirect Indexed (Short,Long) . ........................................77

5.1.7 Relative mode (Direct,Indirect) . . . .. . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . 77

5.2 INSTRUCTION GROUPS . . .. . . . . . . . . . . . . ................................. 78

6 ELECTRICALCHARACTERISTICS . . . . . . . . . . . . . . . . .............................. 81

6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................81

6.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 82

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . .. . . . . . . . . . . . . . . . . . . . . ...........83

6.4 RESET CHARACTERISTICS . . . . . . . . . . .................................... 84

6.5 OSCILLATOR CHARACTERISTICS . . . .. . . . . . . .............................. 84

6.6 PERIPHERAL CHARACTERISTICS . . . . . . . .................................. 84

7 GENERAL INFORMATION . . . . . . . . . . ...........................................88

7.1 EPROM ERASURE . . .. . . . . . . . . . . . . .. . . . . . . .............................. 88

7.2 PACKAGE MECHANICALDATA . . . . . . .. . . . . . . . . . ........................... 89

7.3 ORDERING INFORMATION . . . . . .. . . . . . . .................................. 91

8 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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ST72E121 ST72T121

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72T121 HCMOS Microcontroller Unit
(MCU) is a member of the ST7 family.The device
is based on an industry-standard 8-bit core and
features an enhanced instruction set. The device
is normally operated at a 16 MHz oscillator fre­quency. Under software control, the ST72T121
may be placed in either Wait, Slow or Halt modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard
8-bit data management, the ST72T121 features
true bit manipulation, 8x8 unsigned multiplication

and indirect addressing modeson the whole mem­ory. The device includes a low consumption and
fast start on-chip oscillator, CPU, program memo­ry (OTP/EPROM versions), RAM, 32 I/O lines, a
Low Voltage Detector (LVD) and the following on­chip peripherals: industry standard synchronous
SPI and asynchronous SCI serial interfaces, digit­al Watchdog, two independent 16-bit Timers, one
featuring an External Clock Input, and both featur­ing Pulse Generatorcapabilities, 2 Input Captures
and 2 Output Compares (only1 InputCapture and
1 Output Compare on Timer A).

Figure 1. ST72T121 Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSCIN

OSCOUT

RESET

PORT B

TIMER B

PORT C

SPI

PORT E

SCI

PORT D

WATCHDOG

PB0 -> PB4

PC0 -> PC7

PE0 -> PE1

PD0 -> PD5

OSC

Internal
CLOCK

CONTROL

RAM

(384 - 512 Bytes)

PORT F

PF0 -> PF2,4,6,7

TIMER A

PORT A

PA3 -> PA7

(6 bits)

AND LVD

(6 bits)

(8 bits)

V

SS

V

DD

POWER
SUPPLY

PROGRAM

(8 - 16K Bytes)

MEMORY

(2 bits)

(5 bits)

(5 bits)

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ST72E121 ST72T121

1.2 PIN DESCRIPTION
Figure 2. 44-Pin Thin QFP Package Pinout

Figure 3. 42-Pin Shrink DIPPackage Pinout

1
2
3
4
5
6
7
8
9
10
11

33

32
31
30
29

28

27

26

25

24

23

44 43 42 41 40 39 38 37 36 35 34

12 13 1415 16 17 18 19

(EI1)

(EI1)

(EI1)

20 21 22

CLKOUT/PF0

PF1

PF2

OCMP1_A/PF4

ICAP1_A/PF6

PC1/OCMP1_B

PC2/ICAP2_B

EXTCLK_A/PF7

V

DD_0

V

SS_0

PC0/OCMP2_B

PC3/ICAP1_B

PC4/MISO

PC5/MOSI

PB4
PD0

PD5

PD1
PD2
PD3
PD4

V

DD_3

V

SS_3

RESET

TEST/V

PP

1)

PA7

PA6

PA5

PC7/SS
PC6/SCK

PA4

V

SS_1

V

DD_1

PA3

PB3

PB2

PB1

PB0

PE0/TD0

V

DD_2

OSCIN

OSCOUT

V

SS_2

PE1/RDI

(EI3)

(EI2)
(EI2)
(EI2)
(EI2)

(EI0)

1. VPPon EPROM/OTP only

15
16
17
18
19
20
21

CLKOUT/PF0

PF1
PF2

OCMP1_A/PF4

ICAP1_A/PF6

PC1/OCMP1_B

PC2/ICAP2_B

EXTCLK_A/PF7

RESET
TEST/V

PP

1)

PA7
PA6
PA5

PC7/SS
PC6/SCK

28
27
26
25
24
23
22

PC0/OCMP2_B

PC3/ICAP1_B

PC4/MISO
PC5/MOSI

PA4
V

SS_1

V

DD_1

PA3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

29

30

31

32

33

34

PB4
PD0

PD5

PD1
PD2
PD3

PB3
PB2
PB1
PB0

PE0/TD0
V

DD_2

OSCIN
OSCOUT

V

SS_2

42
41
40
39
38
37
36
35

PD4

V

DD_3

V

SS_3

PE1/RDI

(EI3)

(EI1)
(EI1)
(EI1)

(EI0)

(EI2)

(EI2)

(EI2)

(EI2)

1. VPPon EPROM/OTP only

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ST72E121 ST72T121

Table 1. ST72T121Jx Pin Description

Note 1: VPPon EPROM/OTP only.

Pin n°

QFP44

Pin n°

SDIP42

Pin Name Type Description Remarks

1 38 PE1/RDI I/O Port E1 or SCI Receive Data In
2 39 PB0 I/O Port B0 External Interrupt: EI2
3 40 PB1 I/O Port B1 External Interrupt: EI2
4 41 PB2 I/O Port B2 External Interrupt: EI2
5 42 PB3 I/O Port B3 External Interrupt: EI2
6 1 PB4 I/O Port B4 External Interrupt: EI3
7 2 PD0 I/O Port D0
8 3 PD1 I/O Port D1

9 4 PD2 I/O Port D2
10 5 PD3 I/O Port D3
11 6 PD4 I/O Port D4
12 7 PD5 I/O Port D5
13 8 V

DD_3

S Main Power Supply

14 9 V

SS_3

S Ground
15 10 PF0/CLKOUT I/O Port F0 or CPU Clock Output External Interrupt: EI1
16 11 PF1 I/O Port F1 External Interrupt: EI1
17 12 PF2 I/O Port F2 External Interrupt: EI1
18 13 PF4/OCMP1_A I/O Port F4 or Timer A Output Compare 1
19 14 PF6/ICAP1_A I/O Port F6 or Timer A InputCapture 1
20 15 PF7/EXTCLK_A I/O Port F7 or External Clock on Timer A
21 V

DD_0

S Main power supply
22 V

SS_0

S Ground
23 16 PC0/OCMP2_B I/O Port C0 or Timer B Output Compare 2
24 17 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1
25 18 PC2/ICAP2_B I/O Port C2 or Timer B Input Capture 2
26 19 PC3/ICAP1_B I/O Port C3 or Timer B Input Capture 1
27 20 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data
28 21 PC5/MOSI I/O Port C5 or SPI Master Out / Slave In Data
29 22 PC6/SCK I/O Port C6 or SPI Serial Clock
30 23 PC7/SS I/O Port C7 or SPI Slave Select
31 24 PA3 I/O Port A3 External Interrupt: EI0
32 25 V

DD_1

S Main power supply
33 26 V

SS_1

S Ground
34 27 PA4 I/O Port A4 High Sink
35 28 PA5 I/O Port A5 High Sink
36 29 PA6 I/O Port A6 High Sink
37 30 PA7 I/O Port A7 High Sink

38 31 TEST/V

PP

1)

S

Test mode pin. In the EPROM programming
mode, this pin acts as the programming voltage
input V

PP.

This pin must be tied low
in user mode

39 32 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt.
40 33 V

SS_2

S Ground
41 34 OSCOUT O

Input/Output Oscillator pin. These pinsconnect a parallel-resonant crystal, or
an external source to the on-chip oscillator.

42 35 OSCIN I
43 36 V

DD_2

S Main power supply
44 37 PE0/TDO I/O Port E0 or SCI Transmit Data Out

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ST72E121 ST72T121

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex­ternal connections for the device.

The VPPpin is only used for programming OTP
and EPROM devices and must betied to ground in
user mode.

The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC per­formance/cost tradeoff.

The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.

Unused I/Os should be tied high to avoid any un­necessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.

Figure 4. Recommended External Connections

V

PP

V

DD

V

SS

OSCIN
OSCOUT

RESET

V

DD

0.1µF

+

See
Clocks
Section

V

DD

0.1µF

0.1µF

EXTERNAL RESET CIRCUIT

Or configure unused I/O ports

Unused I/O

10nF

4.7K

10K

by software as input with pull-up

V

DD

Detector (LVD) is used

Optional if Low Voltage

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ST72E121 ST72T121

1.4 MEMORY MAP
Figure 5. Program Memory Map

Table 2. Interrupt Vector Map

Vector Address Description Remarks

FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h

FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

Not Used
Not Used
Not Used

SCI Interrupt Vector
TIMER B Interrupt Vector
TIMER A Interrupt Vector

SPI interrupt vector

Not Used

External Interrupt Vector EI3 (PB4)
External Interrupt Vector EI2 (PB0:PB3)
External Interrupt Vector EI1 (PF0:PF2)

External Interrupt Vector EI0 (PA3)

Not Used
Not Used

TRAP (software) Interrupt Vector

RESET Vector

Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt

External Interrupt
External Interrupt
External Interrupt
External Interrupt

CPU Interrupt

0000h

Interrupt & Reset Vectors

HW Registers

027Fh

0080h

Short Addressing

RAM (zero page)

16-bit Addressing

RAM

007Fh

0200h / 0280h

Reserved

0080h

(see Table 3)

FFDFh

FFE0h

FFFFh

(see Table 2)

027Fh

C000h

BFFFh

00FFh

0100h

01FFh

0200h

8K Bytes

E000h

16K Bytes

Program

Short Addressing
RAM (zero page)

0080h

00FFh

01FFh

01FFh

384 Bytes RAM

512 Bytes RAM

256 Bytes Stack/

16-bit Addressing RAM

256 Bytes Stack/

16-bit Addressing RAM

0100h

Memory

Program

Memory

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ST72E121 ST72T121

Table 3. Hardware Register Memory Map

Address Block

Register

Label

Register Name

Reset

Status

Remarks

0000h
0001h
0002h

Port A

PADR
PADDR
PAOR

Data Register
Data Direction Register
Option Register

00h
00h
00h

R/W
R/W
R/W

1)

0003h Reserved Area (1 byte)
0004h
0005h
0006h

Port C

PCDR
PCDDR
PCOR

Data Register
Data Direction Register
Option Register

00h
00h
00h

R/W
R/W

R/W
0007h Reserved Area (1 byte)
0008h
0009h

000Ah

Port B

PBDR
PBDDR
PBOR

Data Register
Data Direction Register
Option Register

00h
00h
00h

R/W

R/W

R/W

1)

000Bh Reserved Area (1 byte)
000Ch
000Dh
000Eh

Port E

PEDR
PEDDR
PEOR

Data Register
Data Direction Register
Option Register

00h
00h

0Ch

R/W

R/W

R/W

1)

000Fh Reserved Area (1 byte)
0010h

0011h
0012h

Port D

PDDR
PDDDR
PDOR

Data Register
Data Direction Register
Option Register

00h
00h
00h

R/W

R/W

R/W

1)

0013h Reserved Area (1 byte)
0014h
0015h
0016h

Port F

PFDR
PFDDR
PFOR

Data Register
Data Direction Register
Option Register

00h
00h
28h

R/W

R/W

R/W

1)

0017h to
001Fh

Reserved Area (9 bytes)

0020h MISCR Miscellaneous Register 00h
0021h
0022h
0023h

SPI

SPIDR
SPICR
SPISR

SPI Data I/O Register
SPI Control Register
SPI Status Register

xxh
xxh

00h

R/W

R/W

Read Only
0024h to
0029h

Reserved Area (6 bytes)

002Ah
002Bh

WDG

WDGCR
WDGSR

Watchdog Control Register
Watchdog Status Register

7Fh
00h

R/W

R/W

3)

002Ch to
0030h

Reserved Area (5 bytes)

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ST72E121 ST72T121

Notes:

1. The bits corresponding to unavailable pins are forcedto 1 by hardware, this affects the reset status value.

2. External pin not available.

3. Not used in versions without Low Voltage Detector Reset.

0031h
0032h
0033h
0034h-0035h

0036h-0037h

0038h-0039h

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

Timer A

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register

00h
00h

xxh
xxh

xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only

2)

Read Only

2)

R/W

2)

R/W

2)

0040h Reserved Area (1 byte)
0041h
0042h
0043h
0044h-0045h

0046h-0047h

0048h-0049h

004Ah-004Bh

004Ch-004Dh

004Eh-004Fh

Timer B

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register

00h
00h

xxh

xxh

xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W

R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h

SCI

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved
SCI Extended Transmit Prescaler Register

C0h

xxh

00x----xb

xxh
00h
00h

---

00h

Read Only
R/W
R/W
R/W
R/W
R/W
Reserved
R/W

0058h to
007Fh

Reserved Area (40 bytes)

Address Block

Register

Label

Register Name

Reset

Status

Remarks

10

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ST72E121 ST72T121

1.5 OPTION BYTE

The user has the option to select software watch­dog or hardware watchdog (see description in the
Watchdog chapter). When programming EPROM
or OTP devices, this option is selected in a menu
by the user of the EPROM programmer before
burning the EPROM/OTP. The Option Byte is lo­cated in a non-user map. No address has to be
specified. TheOption Byteis atFFh after UVeras­ure and must be properly programmed to set de­sired options.

OPTBYTE

Bit 7:4 = Not used

Bit 3 = Reserved, must be cleared.

Bit 2 = Reserved, mustbe set on ST72T121N de­vices and mustbe cleared onST72T121J devices.

Bit 1 = Not used

Bit 0 = WDG

Watchdog disable

0: The Watchdog isenabled after reset (Hardware

Watchdog).

1: The Watchdog is not enabled after reset (Soft-

ware Watchdog).

70

- - - - b3 b2 - WDG

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ST72E121 ST72T121

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU hasa full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

2.2 MAIN FEATURES

■ 63 basicinstructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stackpointer

■ 8 MHzCPU internal frequency

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 6 are not
present in thememory mapping and are accessed
by specificinstructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (Xand Y)

In indexedaddressing modes, these 8-bitregisters
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in­struction (PRE) to indicate that the following in­struction refers to the Y register.)

The Y register is notaffected by theinterrupt auto­matic procedures (notpushed toand popped from
the stack).

Program Counter (PC)

The program counteris a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program CounterLow whichis the LSB) andPCH
(Program Counter High which is the MSB).

Figure 6. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

70

1C11HI NZ

RESET VALUE= RESET VECTOR @ FFFEh-FFFFh

70

70

70

0

7

15 8

PCH

PCL

15

87 0

RESET VALUE = STACKHIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

RESET VALUE= XXh

RESET VALUE = XXh

X = Undefined Value

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ST72E121 ST72T121

CENTRAL PROCESSING UNIT (Cont’d)
CONDITION CODE REGISTER (CC)

Read/Write
Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in­terrupt mask and four flags representative of the
result of the instructionjust executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Bit 4 = H

Half carry

.

This bit isset byhardware when a carry occurs be­tween bits 3 and 4 of the ALU during an ADD or
ADC instruction.It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.

Bit 3 = I

Interrupt mask

.

This bit is set by hardware when entering in inter­rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in­structions andis tested bythe JRM and JRNM in­structions.

Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-

ter it and reset by the IRET instruction atthe end of
the interrupt routine. If the I bit is cleared by soft­ware inthe interrupt routine, pending interrupts are
serviced regardless of the priority levelof the cur­rent interrupt routine.

Bit 2 = N

Negative

.

This bit is set and cleared by hardware.It is repre­sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7

th

bit of the result.
0:The result of the last operationis positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit isaccessed by the JRMIand JRPL instruc­tions.

Bit 1 = Z

Zero

.

This bit is set and clearedby hardware. Thisbit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft­ware. It indicates an overflow or anunderflow has
occurred during the last arithmetic operation.
0: No overflowor underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCFand RCF instructions
and tested by theJRC and JRNC instructions. It is
also affected by the“bit test and branch”, shift and
rotate instructions.

70

111HINZC

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ST72E121 ST72T121

CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)

Read/Write
Reset Value: 01FFh

The Stack Pointer is a 16-bit register which is al­ways pointingto the next free location in the stack.
It isthen decremented afterdata has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).

Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in­struction (RSP), the Stack Pointer contains its re­set value (the SP7 to SP0 bits are set) which is the
stack higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around tothe stack upper limit, with­out indicating the stack overflow. The previously
stored information is then overwritten and there­fore lost.The stack also wrapsin caseof anunder­flow.

The stack is used to save the return address dur­ing a subroutine call and the CPU context during
an interrupt.The user may also directlymanipulate
the stack by means of the PUSH and POP instruc­tions. In the case ofan interrupt, the PCLis stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.

– Whenan interrupt is received, theSP is decre-

mented and the context is pushed on the stack.

– Onreturn frominterrupt, the SP is incremented

and thecontext is popped from the stack.

A subroutine call occupies twolocations and an in­terrupt five locations in the stack area.

Figure 7. Stack Manipulation Example

15 8

00000001

70

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

SP

Y

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address =

0100h

14

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ST72E121 ST72T121

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a crystal orceramic reso­nator, or an external clock signal todrive the inter­nal oscillator. The internal clock (f

CPU

) is derived

from the external oscillator frequency (f

OSC).

The

external Oscillator clock is first divided by 2, and
an additional divisionfactor of 2, 4, 8,or 16 canbe
applied, in Slow Mode, to reduce the frequency of
the f

CPU

; this clock signal is also routed to the on-

chip peripherals. TheCPU clock signal consistsof
a squarewave with a duty cycle of 50%.

The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resona­tor in the frequency range specified for f

osc

.The

circuit shown in Figure 9 is recommended when
using a crystal, and Table 4 lists the recommend­ed capacitance and feedback resistance values.
The crystal and associated componentsshould be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.

Use of an external CMOS oscillator is recom­mended when crystals outside the specified fre­quency ranges are to be used.

3.1.2 External Clock

An externalclock may be applied tothe OSCIN in­put with the OSCOUT pin not connected, as
shown onFigure 8.

Table 4 Recommended Values for 16 MHz

Crystal Resonator (C0< 7pF)

R

SMAX

: Parasitic series resistance of the quartz

crystal (upperlimit).
C0: Parasitic shunt capacitance of the quartz crys-

tal (upper limit 7pF).

C

OSCOUT,COSCIN

: Maximum total capacitance on

pins OSCIN and OSCOUT (the valueincludes the
external capacitance tied to the pin plus the para­sitic capacitance of the board and of the device).

Figure 8. ExternalClock Source Connections

Figure 9. Crystal/Ceramic Resonator

Figure 10. Clock Prescaler Block Diagram

R

SMAX

40 Ω 60 Ω 150 Ω

C

OSCIN

56pF 47pF 22pF

C

OSCOUT

56pF 47pF 22pF

OSCIN OSCOUT

EXTERNAL

CLOCK

NC

OSCIN OSCOUT

C

OSCIN

C

OSCOUT

OSCIN

OSCOUT

C

OSCIN

C

OSCOUT

%2 %2,4,8, 16

f

CPU

to CPU and
Peripherals

15

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ST72E121 ST72T121

3.2 RESET

3.2.1 Introduction

There are four sources of Reset:
– RESET pin (externalsource)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
– Low Voltage Detection Reset (internal source)
The Reset Service Routine vectoris located at ad-

dress FFFEh-FFFFh.

3.2.2 External Reset

The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low for a duration of t

RESET

to reset

the whole application.

3.2.3 ResetOperation

The duration of the Reset state is a minimum of
4096 internal CPU Clock cycles. During the Reset
state, all I/Os take their reset value.

A Reset signal originating from an externalsource
must have a duration of at least t

PULSE

in order to

be recognised. This detection is asynchronous
and therefore the MCUcan enterReset state even
in Halt mode.

At the end of the Reset cycle, the MCU may be
held in the Reset state by an External Reset sig­nal. The RESET pin may thus be used to ensure
VDDhas risen to a point where the MCUcan oper­ate correctly before the user program is run. Fol­lowing a Reset event, or after exiting Halt mode, a
4096 CPU Clock cycle delay period is initiated in
order to allow the oscillator to stabilise and to en­sure that recovery hastaken place from theReset
state.

In the high state, the RESET pin is connected in­ternally to a pull-up resistor (RON). This resistor
can be pulled low by external circuitry to reset the
device.

The RESET pin is an asynchronous signal which
plays a majorrole in EMS performance. In a noisy
environment, it is recommended to use the exter­nal connections shown in Figure4.

Figure 11. Reset Block Diagram

INTERNAL
RESET

WATCHDOG RESET

OSCILLATOR

SIGNAL

COUNTER

RESET

TO ST7

RESET

POWER-ON RESET

V

DD

LOW VOLTAGE DETECTOR RESET

R

ON

16

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ST72E121 ST72T121

RESET (Cont’d)

3.2.4 LowVoltage Detector Reset

The on-chip Low Voltage Detector (LVD) gener­ates a static reset when the supply voltage is be­low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt­age drop islower than the reference value for pow­er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup­ply (hysteresis).

The LVD Reset circuitry generates a reset when
VDDis below:

V

LVDUP

when VDDis rising

V

LVDDOWN

when VDDis falling

Provided the minimun VDDvalue (guaranteed for
the oscillator frequency) is above V

LVDDOWN

, the

MCU can only be in two modes:

- underfull softwarecontrol or

- instatic safe reset
In this condition, secure operation is always en-

sured for the application without the need for ex­ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.

In noisy environments, the power supplymay drop
for short periods and cause the Low Voltage De­tector to generate a Reset too frequently. In such

cases, it is recommended to use devices without
the LVD Reset option and to rely on the watchdog
function to detect application runaway conditions.

Figure12.Low Voltage DetectorResetFunction

Figure 13. Low Voltage Detector Reset Signal

Note: See electrical characteristics for values of

V

LVDUP

and V

LVDDOWN

Figure 14. Temporization timing diagram after an internal Reset

LOW VOLTAGE

DETECTOR RESET

V

DD

FROM

WATCHDOG

RESET

RESET

RESET

V

DD

V

LVDUP

V

LVDDOWN

V

DD

Addresses

$FFFE

Temporization (4096CPU clock cycles)

V

LVDUP

17

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ST72E121 ST72T121

3.3 INTERRUPTS

The ST7 coremay be interruptedby one of two dif­ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt
processing flowchartis shown in Figure 15.
The maskable interrupts mustbe enabledclearing
the I bitin order tobe serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec­tion).

When an interrupt has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registersare saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– ThePC is thenloaded with theinterrupt vector of

the interrupt to service and the first instructionof
the interrupt serviceroutine is fetched (refer to
the Interrupt Mapping Table for vector address­es).

The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registersto be recovered from thestack.

Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.

Priority management

By default, a servicing interrupt can not be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.

In the case several interrupts are simultaneously
pending, an hardware priority defines which one
will be serviced first (seethe Interrupt Mapping Ta­ble).

Non Maskable Software Interrupts

This interrupt is entered when the TRAP instruc­tion is executed regardless of the state of theI bit.
It will be serviced according to the flowchart on
Figure 15.

Interrupts and Low power mode

All interrupts allowthe processor to leave the Wait
low power mode. Only external and specific men­tioned interrupts allow the processor to leave the

Halt low power mode (refer to the “Exit from HALT“
column in the Interrupt Mapping Table).

External Interrupts

External interrupt vectorscan be loaded in the PC
register if the corresponding external interrupt oc­curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.

The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).

External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.

If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically ANDed before entering theedge/
level detection block.

Warning: The type of sensitivity defined in the
Miscellaneous or Interrupt register (if available)
applies to the EI source. In case of an ANDed
source (as described on the I/O ports section), a
low level on an I/O pin configured as input with in­terrupt, masks the interrupt request even in case
of rising-edge sensitivity.

Peripheral Interrupts

Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:

– TheI bit of the CC register is cleared.
– The correspondingenable bit is setin the control

register.

If any of these two conditions is false, theinterrupt
is latched and thus remains pending.

Clearing an interrupt request is done by:
– writing “0” to the corresponding bit in the status

register or

– anaccess to the status register whilethe flag is

set followed bya read or write of an associated
register.

Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en­abled) will therefore be lost ifthe clear sequenceis
executed.

18

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ST72E121 ST72T121

INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart

BIT I SET

Y

N

IRET

Y

N

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

BIT I SET

Y

N

19

20/92

ST72E121 ST72T121

Table 5. Interrupt Mapping

Source

Block

Description

Register

Label

Flag

Exit

from

HALT

Vector

Address

Priority

Order

RESET Reset N/A N/A yes FFFEh-FFFFh
TRAP Software N/A N/A no FFFCh-FFFDh

NOT USED FFFAh-FFFBh
NOT USED FFF8h-FFF9h

EI0 Ext. Interrupt (Ports PA0:PA3) N/A N/A

yes

FFF6h-FFF7h
EI1 Ext. Interrupt (Ports PF0:PF2) N/A N/A FFF4h-FFF5h
EI2 Ext. Interrupt (Ports PB0:PB3) N/A N/A FFF2h-FFF3h
EI3 Ext. Interrupt (Ports PB4:PB7) N/A N/A FFF0h-FFF1h

NOT USED FFEEh-FFEFh

SPI

Transfer Complete

SPISR

SPIF

no

FFECh-FFEDh

Mode Fault MODF

TIMER A

Input Capture 1

TASR

ICF1_A

FFEAh-FFEBh

Output Compare 1 OCF1_A
Input Capture 2 ICF2_A
Output Compare 2 OCF2_A
Timer Overflow TOF_A

TIMER B

Input Capture 1

TBSR

ICF1_B

FFE8h-FFE9h

Output Compare 1 OCF1_B
Input Capture 2 ICF2_B
Output Compare 2 OCF2_B
Timer Overflow TOF_B

SCI

Transmit Buffer Empty

SCISR

TDRE

FFE6h-FFE7h

Transmit Complete TC
Receive Buffer Full RDRF
Idle Line Detect IDLE
Overrun OR

NOT USED FFE4h-FFE5h
NOT USED FFE2h-FFE3h
NOT USED FFE0h-FFE1h

Highest

Priority

Priority

Lowest

20

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ST72E121 ST72T121

3.4 POWER SAVING MODES

3.4.1 Introduction

There are threePower Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis­cellaneous register. Wait and Halt modes may be
entered usingthe WFI and HALT instructions.

3.4.2 Slow Mode

In Slow mode, the oscillator frequency can be di­vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode isused to reduce
power consumption, andenables the user to adapt
clock frequencyto available supply voltage.

3.4.3 Wait Mode

Wait mode places the MCU in a low power con­sumption mode by stoppingthe CPU. Allperipher­als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All otherregisters and memory remain unchanged.
The MCU will remain in Wait mode until an Inter­rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In­terrupt orReset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.

Refer to Figure 16 below.

Figure 16. WAIT Flow Chart

WFI INSTRUCTION

RESET

INTERRUPT

Y

N

N

Y

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

CLEARED

OFF

Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter­rupt routine and cleared when the CC register is
popped.

4096 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

SET

ON

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

SET

ON

21

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ST72E121 ST72T121

POWER SAVINGMODES (Cont’d)

3.4.4 Halt Mode

The Halt mode is the MCU lowest power con­sumption mode. The Halt mode is entered byexe­cuting theHALT instruction. The internal oscillator
is then turnedoff, causing all internalprocessing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog isenabled, ifthe HALTinstruction is
executed while the watchdog systemis enabled,a
watchdog reset is generatedthus resetting the en­tire MCU.

When entering Halt mode, the Ibit in the CC Reg­ister is clearedso as toenable External Interrupts.
If an interrupt occurs, the CPU becomes active.

The MCU canexit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map­ping Table. The oscillator is then turned on and a
stabilization time is provided beforereleasing CPU
operation. Thestabilization timeis 4096 CPUclock
cycles.

After the start up delay, the CPU continuesoper­ation byservicing the interrupt whichwakes it up or
by fetching the reset vector if a reset wakes it up.

Figure 17. HALT Flow Chart

N

N

EXTERNAL

INTERRUPT

1)

RESET

HALT INSTRUCTION

4096 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

2)

I-BIT

ON

OFF

SET

ON

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

OFF

OFF

CLEARED

OFF

Y

Y

WDG

ENABLED?

N

Y

RESET

WATCHDOG

1) or some specific interrupts

Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter­rupt routine and cleared when the CC register is
popped.

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

SET

ON

2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK =OFF

22

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ST72E121 ST72T121

3.5 MISCELLANEOUS REGISTER

The Miscellaneous register allows to select the
SLOW operatingmode, the polarity of external in­terrupt requestsand to output the internal clock.

Register Address:0020h — Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:6 = PEI[3:2]

External Interrupt EI3 and EI2

Polarity Options

.

These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to Table 6.

Table 6. EI2 and EI3 External Interrupt Polarity

Options

Note: Any modification of one of these twobits re-

sets the interrupt request related to this interrupt
vector.

Bit 5 = MCO

Main Clock Out

This bit isset andclearedby software. Whenset, it
enables the output of the Internal Clock on the
PPF0 I/O port.
0 -PF0 is a general purposeI/O port.
1 -MCO alternate function (f

CPU

is output on PF0

pin).

Bit 4:3 = PEI[1:0]

External Interrupt EI1 and EI0

Polarity Options

.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to Table 7.

Table 7. EI0 and EI1 External Interrupt Polarity

Options

Note: Any modification of oneof thesetwo bitsre-

sets the interrupt request related to this interrupt
vector.l

Bit 2:1 = PSM[1:0]

Prescaler forSlow Mode.

These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.

Table 8. f

CPU

Value in Slow Mode

Bit 0 = SMS

Slow Mode Select

This bit is set andcleared by software.
0: Normal Mode - f

CPU=fOSC

/2

(Reset state)

1: Slow Mode -the f

CPU

valueis determined bythe

PSM[1:0] bits.

70

PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS

MODE PEI3 PEI2

Falling edge and low level

(Reset state)

00

Falling edge only 1 0

Rising edge only 0 1

Rising and falling edge 1 1

MODE PEI1 PEI0

Falling edge and low level

(Reset state)

00

Falling edge only 1 0
Rising edge only 0 1

Rising and falling edge 1 1

f

CPU

Value

PSM1 PSM0

f

OSC

/4 0 0

f

OSC

/16 0 1

f

OSC

/8 1 0

f

OSC

/32 1 1

23

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ST72E121 ST72T121

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

The I/O ports offer different functional modes:
– transferofdata through digitalinputs and outputs
and forspecific pins:
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-

ripherals.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin

can be programmedindependently as digital input
(with or without interrupt generation) or digital out­put.

4.1.2 Functional Description

Each portis associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and someof them to an optional register:
– Option Register(OR)
Each I/Opin may beprogrammed using thecorre-

sponding register bits inDDR and OR registers: bit
X corresponding topin Xof the port. The same cor­respondence is used for the DR register.

The following description takes into account the
OR register, for specific ports whichdo not provide
this register refer to the I/O Port Implementation
Section 4.1.3. The generic I/O block diagram is
shown onFigure 19.

4.1.2.1 Input Modes

The input configuration isselected by clearing the
corresponding DDRregister bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can beselected by software
through theOR register.

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con­figured as an output.

Interrupt function

When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In­terrupt request to the CPU. Theinterrupt polarity is
given independently according to the description
mentioned in the Miscellaneous register or in the
interrupt register (where available).

Each pin can independently generate an Interrupt
request.

Each external interrupt vector is linked to a dedi­cated group of I/O port pins (see Interrupts sec­tion). If several input pins are configured as inputs
to the same interrupt vector, their signals are logi­cally ANDed before entering the edge/level detec­tion block. For this reason if one of the interrupt
pins is tied low, it masks the other ones.

4.1.2.2 Output Mode

The pin is configured in output mode by setting the
corresponding DDR registerbit.

In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.

Note: In this mode, the interrupt function is disa­bled.

4.1.2.3 Digital Alternate Function

When an on-chipperipheral is configured to use a
pin, the alternate function is automatically select­ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configuredin output mode (push-pull
or open drain according to the peripheral).

When the signal is going to an on-chip peripheral,
the I/O pin has to be configured ininput mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex­pected value atthe input of the alternate peripher­al input.

2. When the on-chip peripheral uses apin asinput
and output, this pin must be configured asan input
(DDR = 0).

Warning

: The alternate function must not be acti-

vated as long as the pin isconfigured as inputwith
interrupt, in order to avoid generating spurious in­terrupts.

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4.1.2.4 Analog Alternate Function

When the pin isused as an ADC input theI/O must
be configured as input, floating. The analog multi­plexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.

It isrecommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an­alog pin.

Warning

: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.

4.1.3 I/O Port Implementation

The hardware implementation oneach I/O port de­pends on the settingsin the DDR and OR registers
and specific feature ofthe I/O portsuch as ADC In­put (see Figure 19) or true open drain. Switching
these I/O ports from one state to another should
be done in a sequence that prevents unwanted
side effects. Recommended safetransitions areil­lustrated in Figure 18. Other transitions are poten­tially risky and should be avoided, since they are
likely to present unwanted side-effects such as
spurious interrupt generation.

Figure 18. Recommended I/O State Transition Diagram

with interrupt

INPUT

OUTPUT

no interrupt

INPUT

push-pullopen-drain

OUTPUT

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I/O PORTS (Cont’d)
Figure 19. I/O BlockDiagram

Table 9. Port Mode Configuration

Legend:

0 - present, not activated
1 - present and activated

Notes:

– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.

DR

DDR

LATCH

LATCH

DATA BUS

DR SEL

DDR SEL

V

DD

PAD

ANALOG
SWITCH

ANALOG ENABLE

(ADC)

M
U

X

ALTERNATE

ALTERNATE

ALTERNATE ENABLE

COMMON ANALOG RAIL

ALTERNATE

M
U
X

ALTERNATE INPUT

PULL-UP

OUTPUT

P-BUFFER

(S

EE TABLE BELOW)

N-BUFFER

1

0

1

0

OR

LATCH

ORSEL

FROM
OTHER
BITS

EXTERNAL

PULL-UP
CONDITION

ENABLE

ENABLE

GND

(S

EE TABLE BELOW)

(S

EE NOTE BELOW)

CMOS

SCHMITT TRIGGER

SOURCE (EIx)

INTERRUPT

POLARITY

SEL

GND

V

DD

DIODE

(SEE TABLE BELOW)

Configuration Mode Pull-up P-buffer V

DD

Diode

Floating 0 0 1
Pull-up 1 0 1
Push-pull 0 1 1
True Open Drain not present not present not present
Open Drain (logic level) 0 0 1

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Table 10. Port Configuration

* Reset state (The bits corresponding to unavailable pins are forced to1 by hardware, this affects the reset statusvalue).

Warning: All bits of the DDR register which correspond tounconnected I/Os must be left at their reset value. They must
not be modified by the user otherwise a spurious interrupt may be generated.

Port Pin name

Input (DDR = 0) Output (DDR = 1)

OR= 0 OR = 1 OR = 0 OR=1

Port A

PA3 floating* pull-up with interrupt open-drain push-pull

PA4:PA7 floating* true open drain, high sink capability
Port B PB0:PB4 floating* pull-up with interrupt open-drain push-pull
Port C PC0:PC7 floating* pull-up open-drain push-pull
Port D PD0:PD5 floating* pull-up open-drain push-pull
Port E PE0:PE1 floating* pull-up open-drain push-pull

Port F

PF0:PF2 floating* pull-up with interrupt open-drain push-pull

PF4, PF6,PF7 floating* pull-up open-drain push-pull

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4.1.4 Register Description

4.1.4.1 Data registers

Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Port D Data Register (PDDR)
Port E Data Register (PEDR)
Port F Data Register (PFDR)
Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = D7-D0

Data Register 8 bits.

The DR register has a specific behaviour accord­ing to the selected input/output configuration. Writ­ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either theDR register latch
content (pin configuredas output) or the digital val­ue applied to the I/O pin (pin configured as input).

4.1.4.2 Data direction registers

Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
Port D Data Direction Register (PDDDR)
Port E Data Direction Register (PEDDR)
Port F Data Direction Register (PFDDR)
Read/Write

Reset Value: 0000 0000 (00h) (input mode)

Bit 7:0 = DD7-DD0

Data Direction Register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.

0: Input mode
1: Output mode

4.1.4.3 Option registers

Port A OptionRegister (PAOR)
Port B OptionRegister (PBOR)
Port C Option Register (PBOR)
Port D Option Register (PBOR)
Port E OptionRegister (PBOR)
Port F Option Register (PFOR)
Read/Write

Reset Value: see Register Memory Map Table 3

Bit 7:0 = O7-O0

Option Register8 bits.

The OR register allow to distinguish in input mode
if the interrupt capability or the floating configura­tion is selected.

In output mode it select push-pull or open-drain
capability.

Each bit is set and clearedby software.
Input mode:

0: floating input
1: input pull-up with interrupt

Output mode:
0: open-drain configuration

1: push-pull configuration

70

D7 D6 D5 D4 D3 D2 D1 D0

70

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

70

O7 O6 O5 O4 O3 O2 O1 O0

28