Samsung S3C7324 Datasheet

S3C7324/P7324 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and
watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD
functions and audio applications.

Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast
response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.

OTP

The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The
S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7324 is comparable to S3C7324, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C7324/P7324

FEATURES

Memory

— 256 × 4-bit RAM
— 4096 × 8-bit ROM

I/O Pins

— Input only: 8 pins
— I/O: 16 pins
— Output only: 8 pins sharing with segment driver

outputs

LCD Controller/Driver

— Maximum 14-digit LCD direct drive capability
— 28 segment and 4 common pins
— Display modes: Static, 1/2 duty (1/2 bias)

1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

— Internal resistor circuit for LCD bias

8-Bit Basic Timer

— Programmable interval timer
— Watchdog timer

Bit Sequential Carrier

— Support 16-bit serial data transfer in arbitrary

format

Interrupts

— Two internal vectored interrupts
— Three external vectored interrupts
— Two quasi-interrupts

Memory-Mapped I/O Structure

— Data memory bank 15

Two Power-Down Modes

— Idle mode (only CPU clock stops)
— Stop mode (main system clock stops)
— Subsystem clock stops

Oscillation Sources

— Crystal, ceramic, or RC for main system clock
— Crystal or external oscillator for subsystem clock
— Main system clock frequency: 4.19 MHz (typical)

8-Bit Timer

— Programmable 8-bit timer

Watch Timer

— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Clock source generation for LCD

24-Bit Frequency Counter (FC)

— Level = 300mVpp (Min.)
— AMF input range = 0.5 MHz to 10 MHz
— FMF input range = 30 MHz to 150 MHz

A/D Converter

— 4-channels with 8-bit resolution
— 17 µs (Min.) conversion speed

— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)

Operating Temperature

— – 40 °C to 85 °C

Operating Voltage Range

— 1.8 V to 5.5 V at 3 MHz
— 3.0 V to 5.5 V at FC mode

Package Type

— 64-pin QFP

1-2

S3C7324/P7324 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

N

I

XT

IN

X

OUT

XT

RESET

OUT Watchdog

Timer

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3

P2.0

P2.1
P2.2/FMF
P2.3/AMF

P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3

P4.0-P4.3
P5.0-P5.3

P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2

I/O Port 1

Input

Port 2

Input

Port 3

A/D

Converter

I/O

Port 4, 5

I/O Port 6

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

Logic Unit

256 x 4-Bit

Data

Memory

and

Clock

Instruction

Register

Program

Counter

Program

Status Word

Stack

Pointer

4-Kbyte

Program

Memory

Basic

Timer

Freq.

Counter

8-Bit

Timer

LCD Driver/

Countroller

Output

Port 8,9

Watch
Timer

FMF
AMF

COM0-COM3

SEG0-SEG19

P8.0-P8.3/
SEG27-SEG24

P9.0-P9.3/
SEG23-SEG20

Figure 1-1. S3C7324 Simplified Block Diagram

1-3

PRODUCT OVERVIEW S3C7324/P7324

PIN ASSIGNMENTS

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

64

63

62

61

60

59

58

57

56

55

54

53

52

P2.0

P2.1
P2.2/FMF
P2.3/AMF

P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3

VDD

VSS

X

OUT

XIN

TEST

XTIN

XT

OUT

RESET

P1.0/INT0
P1.1/INT1
P1.2/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S3C7324

(Top View)

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/SEG20
P9.2/SEG21
P9.1/SEG22
P9.0/SEG23
P8.3/SEG24
P8.2/SEG25
P8.1/SEG26
P8.0/SEG27

1-4

20

21

22

23

24

25

26

27

28

29

30

31

32

P4.0

P4.1

P4.2

P4.3

P5.0

P5.1

P5.2

P5.3

P6.1/KS0

P6.2/KS1

P1.3/INT4

P6.0/BUZ

P6.3/KS2

Figure 1-2. S3C7324 64-QFP Pin Assignment

S3C7324/P7324 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C7324 Pin Descriptions

Pin Name Pin

P1.0
P1.1
P1.2
P1.3

Type

I/O 4-bit I/O port.

1-bit or 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can

Description Number Share

Pin

17
18
19
20

INT0
INT1
INT2
INT4

Reset
Value

Circuit

Type

Input D-4

be configured by software.

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1
P3.2
P3.3

P4.0–P4.3
P5.0–P5.3

I 4-bit input port. 1-bit and 4-bit read and

test are possible.
Pull-up resistors can be configured by
software.

I 4-bit input port.

1-bit and 4-bit read and test are possible
Pull-up resistors can be configured by
software.

I/O 4-bit I/O ports. N-channel open-drain

output up to 5 V. 1-bit and 4-bit read,

1
2
3
4

5
6
7
8

21–24
25–28

–

–
FMF
AMF

ADC0
ADC1
ADC2
ADC3

–

–

Input A-4

A-4
B-4
B-4

Input F-13

Input E-2

write, and test are possible. Ports 4 and
5 can be paired to support 8-bit data.
Pull-up resistors can be configured by
software.

P6.0
P6.1
P6.2
P6.3

I/O 1-bit and 4-bit read, write, and test are

possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.

29
30
31
32

BUZ
KS0
KS1
KS2

Input D-2

D-4
D-4

D-4
SEG0–SEG19 O LCD segment signal output 60–41 – Output H-16
P8.0–P8.3

P9.0–P9.3

O 4-bit output ports. 1-bit and 4-bit write

and test are possible. Ports 8 and 9 can

33–36
37–40

SEG27–

SEG20

Output H-16

be paired to support 8-bit data.
COM0–COM3 O LCD common signal output 64–61 – Output H-16
V

V
X

DD
SS

OUT

, X

IN

– Main power supply 9 – – –
– Main ground 10 – – –
– Crystal, ceramic, or RC oscillator pins for

11,12 – – –
main system clock. (For external clock
input, use XIN and input XIN's reverse

XT

OUT

, XT

phase to X

IN

– Crystal oscillator pin for a subsystem

clock. (For external clock input, use XT

OUT

)

15,14 – – –

IN

and input XTIN's reverse phase to
XT

)

OUT

1-5

PRODUCT OVERVIEW S3C7324/P7324

Table 1-1. S3P7324 Pin Descriptions (Continued)

Pin Name Pin

Type

SEG20–SEG27 O LCD segment signal output 40–33 P9.0–P9.3

Description Number Share

Pin

Reset
Value

Circuit

Type

Output H-16

P8.0–P8.3
ADC0–ADC3 I ADC input ports 5–8 P3.0–P3.3 Input F-13
FMF

AMF
INT4 I External interrupt input with detection of

I External FM/AM frequency inputs 3

20 P1.3 Input A-4

P2.2

4

P2.3

Input B-4

rising or falling edges.

INT2 I Quasi-interrupt with detection of rising

19 P1.2 Input A-4

edge signals.

INT1
INT0

I External interrupt. The triggering edges

for INT0 and INT1 are able to be

18
17

P1.1
P1.0

Input A-4

selected. Only INT0 is synchronized with
the system clock.

BUZ O 2, 4, 8, or 16 kHz frequency output for

29 P6.0 Input D-2
buzzer sound with 4.19 MHz main
system clock.

KS0–KS2 I Quasi-interrupt input with falling edge

30–32 P6.1–P6.3 Input D-4

detection.

RESET

TEST – System test pin(must be connected to

I System reset signal 16 – Input B

13 – – –
V

SS)

NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.

1-6

S3C7324/P7324 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

P-CHANNEL

IN

DD

Figure 1-3. Pin Circuit Type A

V

DD

Pull-up
Enable

In

N-CHNNEL

IN

Figure 1-5. Pin Circuit Type B

Type A

Feedback
Enable

Pull-down
Enable

Figure 1-4. Pin Circuit Type A-4

Figure 1-6. Pin Circuit Type B-4

1-7

PRODUCT OVERVIEW S3C7324/P7324

V

DD

V

DD

Pull-up

Data

Enable

Output

Disable

Figure 1-7. Pin Circuit Type C

V

DD

Pull-up
Enable

Data

Output

Disable

Circuit

TYPE C

I/O

Out

Data

Output

Disable

Data

Output

Circuit

TYPE C

Disable

Figure 1-9. Pin Circuit Type D-4

V

DD

PNE

V

DD

I/O

Pull-up
Enable

I/O

1-8

Figure 1-8. Pin Circuit Type D-2

Figure 1-10. Pin Circuit Type E-2

S3C7324/P7324 PRODUCT OVERVIEW

V

DD

Pull-up Enable

Data

ADCEN

ADC Select

To ADC

Figure 1-11. Pin Circuit Type F-13

In

1-9

PRODUCT OVERVIEW S3C7324/P7324

V

DD

V

LC0

V

LC1

SEG/COM

and Port Data

V

LC2

Figure 1-12. Pin Circuit Type H-16

Out

1-10

S3C7324/P7324 ELECTRICAL DATA

15 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point
— Clock timing measurement at X

— Clock timing measurement at XT
— Input timing for RESET

— Input timing for external interrupts

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request

IN

IN

15-1

ELECTRICAL DATA S3C7324/P7324

Table 15-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

V

I

V

IN

O

OH

All I/O ports

One I/O port active – 15 mA

– – 0.3 to + 6.5 V

– 0.3 to V

–

– 0.3 to VDD + 0.3

DD

+ 0.3

All I/O ports active – 30

Output Current Low

I

OL

One I/O port active + 30 (Peak value)

(note)

+ 15

Total value for ports 1, 4, 5 and 6 + 100 (Peak value)

(note)

+ 60

Operating Temperature
Storage Temperature

T

A

T

stg

– – 40 to + 85
– – 65 to + 150

°

C

NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty .

Table 15-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input high
voltage

V

IH1

All input pins except those
specified below

V

IH2

P1, P3, RESET, P2.0−1 and

0.7 V

0.8 V

DD

DD

–

V

DD

V

DD

P6.1−3

Input low
voltage

V

IH3

V

IL1

V

IL2

XIN, X

, XTIN, and XT

OUT

OUT

All input pins except those
specified below

P1, P3, RESET, P2.0−1 and

V

– 0.1 V

DD

– –

DD

0.3 V

0.2 V

DD

DD

P6.1−3

Output high
voltage

V

V

OH1

IL3

XIN, X

, XTIN, and XT

OUT

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

OUT

0.1

V

DD

– 1.0

– – V

Ports 1, 4, 5, and 6

V

OH2

VDD = 4.5 V to 5.5 V

V

– 2.0

DD

IOH = –100 µA Port 8 and 9

V

V

15-2