Samsung S3C72N4, S3C72N2, S3P72N4 Datasheet
S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4
offers an excellent design solution for a wide variety of applications that require LCD functions.
Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast
response to internal and external events. In addition, the S3C72N2/C72N4 's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.
OTP
The S3C72N2/C72N4 microcontroller is also available in OTP (One Time Programmable) version, S3P72N4 .
The S3P72N4 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM.
The S3P72N4 is comparable to S3C72N2/C72N4, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW S3C72N2/C72N4/P72N4
FEATURES
Memory
— 288 × 4-bit RAM
— 2048 × 8-bit ROM (S3C72N2)
— 4096 × 8-bit ROM (S3C72N4)
I/O Pins
— Input only: 4 pins
— I/O: 12 pins
— Output: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
— Maximum 16-digit LCD direct drive capability
— 32 segment, 4 common pins
— Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
8-Bit Basic Timer
— Programmable interval timer
Interrupts
— Two internal vectored interrupts
— Two external vectored interrupts
— Two quasi-interrupts
Memory-Mapped I/O Structure
— Data memory bank 15
Two Power-Down Modes
— Idle mode (only CPU clock stops)
— Stop mode (main or sub system oscillation stops)
Oscillation Sources
— Crystal, ceramic, or RC for main system clock
— Crystal or external oscillator for subsystem clock
— Main system clock frequency: 4.19 MHz (typical)
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)
— Watchdog timer
8-Bit Timer/Counter
— Programmable 8-bit timer
— External event counter
— Arbitrary clock frequency output
Watch Timer
— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Clock source generation for LCD
Bit Sequential Carrier
— Support 16-bit serial data transfer in arbitrary
format
Instruction Execution Times
— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)
Operating Temperature
— – 40 °C to 85 °C
Operating Voltage Range
— 2.0 V to 5.5 V at 4.19 MHz
— 1.8 V to 5.5 V at 3 MHz
Package Type
— 64-pin QFP
1-2
S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.3/TCL0
P2.0/TCLO0
P6.0-P6.3/
KS0-KS3
P8.0-P8.7
SEG24-SEG31
INT0, INT1, INT2
8-Bit Timer/
Counter0
I/O Port 6
Output Port 8
Watchdog
Timer
RESET
Interrupt
Control
Xin
XTin
Interrupt
Control
Block
Internal
Interrupts
Instruction Decoder
Arithmetic
and
Logic Unit
288 x 4-Bit
Data Memory
XTout
Block
Xout
Basic
Timer
Instruction
2/4 KByte
Program
Memory
Watch
Timer
Register
Program
Counter
Program
Status
Word
Stack
Pointer
P2.3/BUZ
LCD
Driver/
Controller
Input
Port 1
I/O Port 2
I/O Port 3
BIAS
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
P8.0-P8.7/
SEG24-SEG31
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram
1-3
PRODUCT OVERVIEW S3C72N2/C72N4/P72N4
PIN ASSIGNMENTS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
64636261605958575655545352
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
VDD
VSS
Xout
Xin
TEST
XTin
XTout
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S3C72N2
S3C72N4
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7
20212223242526272829303132
P2.1
P1.3/TCL0
P2.2/CLO
P2.0/TCLO0
P2.3/BUZ
P3.2
P3.3
P6.0/KS0
P3.1/LCDSY
P3.0/LCDCK
P6.1/KS1
P6.2/KS2
P6.3/KS3
Figure 1-2. S3C72N2/C72N4 64-QFP Pin Assignment
1-4
S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72N2/C72N4 Pin Descriptions
Pin Name Pin
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
Type
I 4-bit input port.
1-bit or 4-bit read and test is possible.
4-bit pull-up resistors are software
assignable.
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
4-bit pull-up resistors are software
Description Number Share
Pin
17
18
19
20
21
22
23
24
INT0
INT1
INT2
TCL0
TCLO0
–
CLO
BUZ
Reset
Value
Circuit
Type
Input A-4
Input D
assignable.
P3.0
P3.1
P3.2
P3.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
Each individual pin can be specified as
25
26
27
28
LCDCK
LCDSY
Input D
input or output. 4-bit pull-up resistors are
software assignable.
P6.0–P6.3 I/O 4-bit I/O ports. Pins are individually
29–32 KS0–KS3 Input D
software configurable as input or output.
1-bit and 4-bit read/write and test is
possible. 4-bit pull-up resistors are
software assignable.
P8.0–P8.7 O Output port for 1-bit data (for use as
CMOS driver only)
40–33 SEG24–
SEG31
Output H-1
SEG0–SEG23 O LCD segment signal output 64–41 – Output H
SEG24–SEG31 O LCD segment signal output 40–33 P8.0–P8.7 Output H-1
COM0–COM3 O LCD common signal output 1–4 – Output H
V
LC0–VLC2
– LCD power supply.
6–8 – – –
Built-in voltage dividing resistors
BIAS – LCD power control 5 – – –
LCDCK I/O LCD clock output for display expansion 25 P3.0 Input D
1-5
PRODUCT OVERVIEW S3C72N2/C72N4/P72N4
Table 1-1. S3C72N2/C72N4 Pin Descriptions (Continued)
Pin Name Pin
Type
LCDSY I/O LCD synchronization clock output for
Description Number Share
Pin
26 P3.1 Input D
Reset
Value
Circuit
Type
LCD display expansion
TCL0 I External clock input for timer/counter 0 20 P1.3 Input A-4
TCLO0 I/O Timer/counter 0 clock output 21 P2.0 Input D
INT0
INT1
I External interrupt. The triggering edge for
INT0 and INT1 is selectable. Only INT0 is
17
18
P1.0
P1.1
Input A-4
synchronized with the system clock.
INT2 I Quasi-interrupt with detection of rising
19 P1.2 Input A-4
edge signals.
KS0–KS3 I/O Quasi-interrupt input with falling edge
29–32 P6.0–P6.3 Input D
detection.
CLO I/O CPU clock output 23 P2.2 Input D
BUZ I/O 2, 4, 8 or 16 kHz frequency output for
24 P2.3 Input D
buzzer sound with 4.19 MHz main system
clock or 32.768 kHz subsystem clock.
X
X
,
IN
OUT
– Crystal, ceramic or RC oscillator pins for
12,11 – – –
main system clock. (For external clock
input, use XIN and input XIN’s reverse
phase to X
XT
XT
,
IN
OUT
– Crystal oscillator pins for subsystem
clock. (For external clock input, use XT
and input XTIN’s reverse phase to XT
V
DD
V
SS
RESET
– Main power supply 9 – – –
– Ground 10 – – –
– Reset signal 16 – Input B
TEST – Test signal input (must be connected to
OUT
)
14,15 – – –
IN
)
OUT
13 – – –
VSS)
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
1-6
S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
P-CHANNEL
IN
N-CHNNEL
Figure 1-3. Pin Circuit Type A
V
DD
PULL-UP
RESISTOR
P-CHANNEL
IN
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
Figure 1-5. Pin Circuit Type C
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
CIRCUIT
TYPE C
V
DD
V
DD
PULL-UP
RESISTOR
P-CHANNEL
P-CHANNEL
OUT
N-CHANNEL
I/O
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A-4 (P1)
CIRCUIT TYPE A
Figure 1-6. Pin Circuit Type D (P2, P3, and P6)
1-7
PRODUCT OVERVIEW S3C72N2/C72N4/P72N4
V
LC0
V
V
LC1
DD
LCD SEGMENT/
COMMON DATA
V
LC2
OUT
Figure 1-7. Pin Circuit Type H (SEG/COM)
V
DD
V
LC0
IN
SCHMITT TRIGGER
Figure 1-9. Pin Circuit Type B (RESET)
V
LC1
LCD SEGMENT/
& PORT 8 DATA
V
LC2
Figure 1-8. Pin Circuit Type H-1 (P8)
1-8
OUT
S3C72N2/C72N4/P72N4 ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72N2/C72N4 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
STANDARD ELECTRICAL CHARACTERISTICS
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
MISCELLANEOUS TIMING WAVEFORMS
— A.C timing measurement point
— Clock timing measurement at X
— Clock timing measurement at XT
— TCL0 timing
— Input timing for RESET
— Input timing for external interrupts
STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
IN
IN
13-1
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