Samsung S3C72C8, S3P72C8 Datasheet
S3C72C8/P72C8 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-96-dot LCD direct drive capability flexible 16-bit timer/counter, and 4-chanel comparator, the
S3C72C8 offers an excellent design solution for a low CDP and a card reader.
Up to 28 pins of the 44-pin QFP or up to 26 pins of the 42-pin SDIP package can be dedicated to I/O. Eight
vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced
CMOS technology provides for low power consumption.
OTP
The S3C72C8 microcontroller is also available in OTP (One Time Programmable) version, S3P72C8. S3P72C8
microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P72C8 is comparable to S3C72C8, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW S3C72C8/P72C8
FEATURES
Memory
• 512 × 4-bit RAM (including LCD display RAM)
• 8,192 × 8-bit ROM
28 I/O Pins
• I/O: 26 pins (44-pin QFP, 42-pin SDIP)
• Output only: 2 pins (44-pin QFP)
LCD Controller/Driver
• 12 segments and 8 common terminals
(3, 4, and 8 common selectable)
• Internal resistor circuit for LCD bias
• All dot can be switched on/off
8-bit Basic Timer
• 4 interval timer functions
• Watch-dog timer
16-bit Timer/Counter 1
• Programmable 16-bit timer/counter
• Arbitrary clock output
• External event counter
• External clock signal divider
• Configurable as two 8-bit timer/counters
• Serial I/O interface clock generator
Watch Timer
• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
• Four frequency outputs to BUZ pin
• Clock source generation for LCD
8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• LSB-first or MSB-first transmission selectable
• Internal or external clock source
Interrupts
• Four internal vectored interrupts
• Five external vectored interrupts
• Two quasi-interrupts
Bit Sequential Carrier
• Supports 16-bit serial data transfer in arbitrary
format
Memory-Mapped I/O Structure
• Data memory bank 15
Power-Down Modes
• Idle mode (only CPU clock stops)
• Stop mode (main system oscillation stops)
• Sub system clock stop mode
Oscillation Sources
• Crystal, ceramic, or RC for main system clock
• Crystal oscillator for subsystem clock
• Main system clock frequency: 0.4 MHz-6 MHz
• Subsystem clock frequency: 32.768 kHz
• CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
• 0.67, 1.33, 10.7 µs at 6 MHz (main)
• 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
• 122 µs at 32.768 kHz (subsystem)
Operating Temperature
• – 40 °C to 85 °C
Operating Voltage Range
• 1.8 V to 5.5 V
Package Type
• 44-pin QFP, 42-pin SDIP
Comparator
• 4 channel mode: internal reference (4-bit
resolution)
• 3 channel mode: external reference
1-2
S3C72C8/P72C8 PRODUCT OVERVIEW
BLOCK DIAGRAM
Watch Dog
8-Bit Timer/
Counter1A
8-Bit Timer/
Counter1B
P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
P3.0/INTP30
P3.1/INTP31
P5.0-P5.3/
SEG0-SEG3
P6.0-P6.3/
SEG4-SEG7
P7.0-P7.3/
SEG8-SEG11
16-Bit
Timer/
Counter
I/O Port 2
I/O Port 3
I/O Port 5
I/O Port 6
I/O Port 7
RESET XTOUTXTIN
Interrupt
Control
Block
Internal
Interrupts
Instruction Decoder
Arithmetic
and
Logic Unit
Clock
XOUTXIN
Instruction
Register
Program
Counter
Program
Status Word
Stack
Pointer
Timer
Basic Timer
Watch Timer
LCD
Driver/
Controller
SIO
I/O Port 0
I/O Port 1
COM0-COM3
COM4-COM7/
SEG15-SEG12
SEG0-SEG3/
P5.0-P5.3
SEG4-SEG7/
P6.0-P6.3
SEG8-SEG11/
P7.0-P7.3
SCK
P0.0/
P0.1/SO
P0.2/SI
P0.3/BTCO
P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4
P4.0
P4.1
Output Port 4
44 QFP Only
512 x 4-Bit
Data
Memory
8 K Byte
Program
Memory
Figure 1-1. S3C72C8 Simplified Block Diagram
Comparator
1-3
PRODUCT OVERVIEW S3C72C8/P72C8
PIN ASSIGNMENTS
P4.0
P4.1
P1.3/BUZ/INT4
P1.2/CLO/INT2
P1.1/TCL1/INT1
P1.0/TCLO1/INT0
COM0
COM1
COM2
COM3
COM4/SEG15
4443424140393837363534
P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
1
2
3
4
5
6
7
8
9
10
11
S3C72C8
(44-QFP-1010B)
1213141516171819202122
RESET
P0.2/SI
P0.1/SO
P0.3/BTCO
P0.0/SCK
P3.1/INTP31
P3.0/INTP30
SEG0/P5.0
33
32
31
30
29
28
27
26
25
24
23
SEG1/P5.1
SEG2/P5.2
SEG3/P5.3
Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
1-4
S3C72C8/P72C8 PRODUCT OVERVIEW
COM1
COM0
P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4
P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P0.3/BTCO
P0.2/SI
P0.1/SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP-600)
S3C72C8
Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
COM2
COM3
COM4/SEG15
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
SEG3/P5.3
SEG2/P5.2
SEG1/P5.1
SEG0/P5.0
P3.0/INTP30
P3.1/INTP31
P0.0/SCK
1-5
PRODUCT OVERVIEW S3C72C8/P72C8
Table 1-1. S3C72C8 Pin Descriptions
Pin Name Pin
Type
P0.0
I/O 4-bit I/O port.
P0.1
P0.2
P0.3
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as
input or output; Individual pins are software
Description Circuit
Type
E–1 16 (22)
Number Share Pin
15 (21)
14 (20)
13 (19)
configurable as open-drain or push-pull output;
Individual pull-up resistors are software
assignable; pull-up resistors are automatically
disabled for output pins.
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
I/O Same as port 0. E–1 39 (3)
40 (4)
41 (5)
42 (6)
I/O Same as port 0 except that port 2 is not
configurable as n-channel open drain and is
configurable as analog input pin.
F–8 1 (7)
2 (8)
3 (9)
4 (10)
I/O 2-bit I/O port
1-bit and 4-bit read/write and test is possible.
E–3 18 (24)
17 (23)
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
2-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
P4.0
P4.1
O 2-bit output port.
1-bit and 4-bit read/write and test is possible.
E-2 44
43
Individual pins are software configurable as
open-drain or push-pull output.
P5.0-P5.3 I/O 4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
H-13 19-22
(25-28)
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
4-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
P6.0-P6.3 I/O Same as port5 H-13 23-26
(29-32)
P7.0-P7.3 I/O Same as port5 H-13 27-30
(33-36)
SCK
SO
SI
BTCO
TCLO1/INT0
TCL1/INT1
CLO/INT2
BUZ/INT4
K0/CIN0
K1/CIN1
K2/CIN2
K3/CIN3
INTP30
INTP31
SEG0-SEG3
SEG4-SEG7
SEG8-SEG11
1-6
S3C72C8/P72C8 PRODUCT OVERVIEW
Table 1-1. S3C72C8 Pin Descriptions (Continued)
Pin Name Pin
Type
SEG0-SEG3 I/O LCD segment display signal output pins H–13 19-22
Description Circuit
Type
Number Share Pin
P5.0-P5.3
(25-28)
SEG4-SEG7 23-26
P6.0-P6.3
(29-32)
SEG8-SEG11 27-30
P7.0-P7.3
(33-36)
SEG12-SEG15 O LCD segment display output pins H–6 31-34
COM7-COM4
(37-40)
COM0-COM3 O LCD common signal output pins H–4 38-35
(2-1,
42-41)
COM4-COM7 I/O LCD common signal output pins H–6 34-31
(40-37)
SCK
I/O Serial interface clock signal E–1 16 (22) P0.0
SO I/O Serial data output E–1 15 (21) P0.1
SI I/O Serial data input E–1 14 (20) P0.2
BTCO I/O Basic timer overflow signal E–1 13 (19) P0.3
TCLO1 I/O Timer/counter external clock output E–1 39 (3) P1.0/INT0
TCL1 I/O Timer/counter external clock input E–1 40 (4) P1.1/INT1
CLO I/O Clock output E–1 41 (5) P1.2/INT2
BUZ I/O Frequency output to buzzer E–1 42 (6) P1.3/INT4
RESET
X
in, Xout
XT
in, XTout
I
System RESET pin
– Clock input and output pins for main system
clock
– Clock input and output pins for subsystem
clock
B 12 (18) –
– 8-7
(14-13)
– 10-11
(16-17)
CIN0–CIN3 I Analog input port for Comparator F–8 1-4
(7-10)
K0–K3 I/O External interrupts. The triggering edge is
selectable.
INT0
INT1
I External interrupts. The triggering edge for
INT0 and INT1 is selectable.
F–8 1-4
(7-10)
E–1 39 (3)
40 (4)
P2.0/CIN0
-P2.3/CIN3
P1.0/TCLO1
-P1.1/TCL1
–
SEG12–
SEG15
–
–
P2.0/K0
-P2.3/K3
1-7
PRODUCT OVERVIEW S3C72C8/P72C8
Table 1-1. S3C72C8 Pin Descriptions (Continued)
Pin Name Pin
Type
INT2 I Quasi-interrupt with detection of rising or
Description Circuit
Type
E-1 41 (5) P1.2/CLO
Number Share Pin
falling edges.
INT4 I External interrupt with detection of rising or
E-1 42 (6) P1.3/BUZ
falling edges.
INTP30
INTP31
I Key scan interrupts inputs. E-3 18-17
(24-23)
TEST I System test pin – 9 (15) –
V
DD
V
SS
NOTES:
1. Parentheses indicate pin number for 42-SDIP package.
2. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
– Power supply pin – 5 (11) –
– Ground pin – 6 (12) –
P3.0, P3.1
1-8
S3C72C8/P72C8 PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
Pull-Up
Resistor
In
Schmitt Trigger Input
Figure 1-4. Pin Circuit Type B
Pull-Up
Resistor
Enable
PNE
Data
Output
DIsable
VDD
Pull-up
Resistor
P-CH
VDD
I/O
Figure 1-5. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW S3C72C8/P72C8
VDD
PNE
Data
Pull-Up
Resistor
Enable
PNE
Ouput
Disable
Data
Figure 1-6. Pin Circuit Type E-2
VDD
Pull-Up
Resistor
Circuit
Type E-4
Out
P-CH
I/O
LCON.1
1-10
Figure 1-7. Pin Circuit Type E-3
S3C72C8/P72C8 PRODUCT OVERVIEW
VDD
PNE
VDD
Data
VLC1
Out
Figure 1-8. Pin Circuit Type E-4
COM Data
VLC4
VSS
Out
LPOT.3
Figure 1-9. Pin Circuit Type H-4
1-11
PRODUCT OVERVIEW S3C72C8/P72C8
VDD
VLC1
VLC2
SEG/COM Data
Out
VSS
VLC4
VLC3
Figure 1-10. Pin Circuit Type H-6
LPOT.3
1-12
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