Samsung M471B1G73EB0-YK0 User Manual
Rev. 1.1, Apr. 2015
M471B5173EB0
M471B1G73EB0
204pin Unbuffered SODIMM
1.35V
based on 4Gb E-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
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© 2015 Samsung Electronics Co., Ltd.GG All rights reserved.
- 1 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
Revision History
Revision No. History Draft Date Remark Editor
1.0 - First SPEC Release Jul. 2014 - S.H.Kim
1.1 - Added to 1866(13-13-13) speed from Product line-up Apr. 2015 - J.Y.Lee
- 2 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
Table Of Contents
204pin Unbuffered SODIMM based on 4Gb E-die
1. DDR3L Unbuffered SODIMM Ordering Information......................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. x64 DIMM Pin Configurations (Front side/Back Side)...................................................................................................5
5. Pin Description .............................................................................................................................................................6
6. Input/Output Functional Description..............................................................................................................................7
7. Function Block Diagram:...............................................................................................................................................8
7.1 4GB, 512Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 8
7.2 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)........................................................................9
8. Absolute Maximum Ratings ..........................................................................................................................................10
8.1 Absolute Maximum DC Ratings............................................................................................................................... 10
8.2 DRAM Component Operating Temperature Range ................................................................................................10
9. AC & DC Operating Conditions.....................................................................................................................................10
9.1 Recommended DC Operating Conditions ..............................................................................................................10
10. AC & DC Input Measurement Levels ..........................................................................................................................11
10.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................11
10.2 VREF Tolerances .................................................................................................................................................. 13
10.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................14
10.3.1. Differential Signals Definition ......................................................................................................................... 14
10.3.2. Differential Swing Requirement for Clock (CK -
10.3.3. Single-ended Requirements for Differential Signals ......................................................................................16
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 17
10.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................18
10.5 Slew rate definition for Differential Input Signals ................................................................................................... 18
11. AC & DC Output Measurement Levels .......................................................................................................................18
11.1 Single Ended AC and DC Output Levels...............................................................................................................18
11.2 Differential AC and DC Output Levels ................................................................................................................... 18
11.3 Single-ended Output Slew Rate ............................................................................................................................ 19
11.4 Differential Output Slew Rate ................................................................................................................................ 20
12. IDD specification definition..........................................................................................................................................21
13. IDD SPEC Table .........................................................................................................................................................23
14. Input/Output Capacitance ...........................................................................................................................................25
15. Electrical Characteristics and AC timing .....................................................................................................................26
15.1 Refresh Parameters by Device Density................................................................................................................. 26
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................26
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................26
15.3.1. Speed Bin Table Notes .................................................................................................................................. 31
16. Timing Parameters by Speed Grade ..........................................................................................................................32
16.1 Jitter Notes ............................................................................................................................................................36
16.2 Timing Parameter Notes........................................................................................................................................ 37
17. Physical Dimensions :.................................................................................................................................................38
17.1 512Mbx8 based 512Mx64 Module (1 Rank) - M471B5173EB0 ............................................................................38
17.2 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73EB0................................................................................39
CK) and Strobe (DQS - DQS) ............................................. 14
- 3 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
1. DDR3L Unbuffered SODIMM Ordering Information
Part Number Density Organization
M471B5173EB0-YK0/MA 4GB 512Mx64 512Mx8(K4B4G0846E-BY##)*8 1 30mm
M471B1G73EB0-YK0/MA 8GB 1Gx64 512Mx8(K4B4G0846E-BY##)*16 2 30mm
NOTE :
1. "##" - K0/MA
2. K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)
- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11)
Component Composition
1
Number of
Rank
Height
2. Key Features
Speed
tCK(min) 2.5 1.875 1.5 1.25 1.071 ns
CAS Latency 6 7 9 11 13 nCK
tRCD(min) 15 13.125 13.5 13.75 13.91 ns
tRP(min) 15 13.125 13.5 13.75 13.91 ns
tRAS(min) 37.5 37.5 36 35 34 ns
tRC(min) 52.5 50.625 49.5 48.75 47.91 ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
•V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933MHz fCK for
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10,11,13
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333),8 (DDR3-1600) and 9(DDR3-1866)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
DDQ
1866Mb/sec/pin
write [either On the fly using A12 or MRS]
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13
85C, 3.9us at 85C < T
CASE
CASE
95C
Unit
3. Address Configuration
Organization Row Address Column Address Bank Address Auto Precharge
512Mx8(4Gb) based Module A0-A15 A0-A9 BA0-BA2 A10/AP
- 4 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1
3
V
REFDQ
V
2
SS
4 DQ4 KEY
V
SS
71
V
SS
72
V
SS
5 DQ0 6 DQ5 73 CKE0 74 CKE1
7 DQ1 8
9
V
SS
10 DQS0 77 NC 78
V
SS
75
11 DM0 12 DQS0 79 BA2 80
13
V
SS
14
V
SS
81
15 DQ2 16 DQ6 83 A12/
V
DD
V
DD
76
82
V
A15
A14
V
DD
3
3
DD
BC 84 A11 153 DM5 154 DQS5
17 DQ3 18 DQ7 85 A9 86 A7 155
19
V
SS
20
V
SS
87
V
DD
88
V
DD
21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47
23 DQ9 24 DQ13 91 A5 92 A4 161
25
27
V
SS
26
DQS1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53
29 DQS1 30
31
V
SS
32
V
SS
93
V
DD
94
V
DD
RESET 97 A1 98 A0 167
V
SS
99
V
DD
100
V
DD
33 DQ10 34 DQ14 101 CK0 102 CK1 171
35 DQ11 36 DQ15 103 CK0 104 CK1 173
37
V
SS
38
V
SS
39 DQ16 40 DQ20
41 DQ17 42 DQ21
43
45
V
SS
44
DQS2 46 DM2
47 DQS2 48
49
V
SS
50 DQ22
V
SS
V
SS
51 DQ18 52 DQ23
53 DQ19 54
55
V
SS
56 DQ28
V
SS
57 DQ24 58 DQ29
59 DQ25 60
61
V
SS
62 DQS3
V
SS
105 V
107
A10/AP 108 BA1 177 DQ51 178
109
111 V
113
115
117 V
119
121
123 V
125
127 V
129
DD
106
V
DD
BA0 110 RAS 179
DD
112
V
DD
WE 114 S0 183 DQ57 184
CAS 116 ODT0 185
V
DD
A13
DD
118
3
120 ODT1 189
S1 122 NC 191 DQ58 192 DQ62
DD
124
TEST 126
SS
128
V
V
REFCA
V
DD
SS
DQ32 130 DQ36 199
63 DM3 64 DQS3 131 DQ33 132 DQ37 201 SA1 202 SCL
65
V
SS
66
V
SS
133 V
SS
134
V
SS
67 DQ26 68 DQ30 135 DQS4 136 DM4
69 DQ27 70 DQ31
137
DQS4 138
V
SS
NOTE :
1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
139 V
141
143
145 V
147
149
151
SS
DQ34 142 DQ39
DQ35 144
SS
DQ40 148 DQ45
DQ41 150
V
SS
V
SS
140 DQ38
V
SS
146 DQ44
V
SS
152 DQS5
156
V
SS
157 DQ42 158 DQ46
V
SS
162
V
SS
163 DQ48 164 DQ52
169
V
SS
DQS6
DQS6
V
SS
168
170
172
174 DQ54
V
SS
DM6
V
SS
175 DQ50 176 DQ55
V
SS
V
SS
180 DQ60
181 DQ56 182 DQ61
V
SS
V
SS
186 DQS7
187 DM7 188 DQS7
V
SS
190
V
SS
193 DQ59 194 DQ63
195
V
SS
196
V
SS
197 SA0 198 NC
203
V
DDSPD
V
TT
200 SDA
204
V
TT
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 5 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
5. Pin Description
Pin Name Description Number Pin Name Description Number
CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64
CK0, CK1 Clock Inputs, negative line 2 DM0-DM7
CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8
RAS Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8
CAS Column Address Strobe 1 RESET Reset Pin 1
WE Write Enable 1 TEST
S0, S1 Chip Selects 2
A0-A9, A11,
A13-A15
Address Inputs 14
A10/AP Address Input/Autoprecharge 1
A12/BC Address Input/Burst chop 1
BA0-BA2 SDRAM Bank Addresses 3
V
V
V
REFDQ
V
REFCA
V
DDSPD
V
DD
SS
TT
ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3
SCL Serial Presence Detect (SPD) Clock Input 1 Total 204
SDA SPD Data Input/Output 1
SA0-SA1 SPD Address 2
NOTE:
*The V
DD
and V
pins are tied common to a single power-plane on these designs.
DDQ
Data Masks/ Data strobes,
Termination data strobes
Logic Analyzer specific test pin (No connect
on SODIMM)
Core and I/O Power 18
Ground 52
Input/Output Reference 2
SPD and Temp sensor Power 1
Termination Voltage 2
8
1
- 6 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
6. Input/Output Functional Description
Symbol Type Function
CK0-CK1
CK0-CK1
CKE0-CKE1 Input
S0-S1 Input
RAS, CAS, WE Input
BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
A0-A9,
A10/AP,
A11
A12/BC
A13-A15
DQ0-DQ63 I/O Data Input/Output pins.
DM0-DM7 Input
DQS0-DQS7
DQS0-DQS7
VDD,V
DDSPD,
V
SS
V
REFDQ,
V
REFCA
SDA I/O
SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.
TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET Input RESET In Active Low This signal resets the DDR3 SDRAM
Input
Input
I/O
Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Supply Reference voltage for SSTL15 inputs.
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1.
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to V
on the system planar to act as a pull up.
DDSPD
- 7 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
7. Function Block Diagram:
7.1 4GB, 512Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
RAS
CASWECK0
CK0
CKE0
ODT0
/BA[0:N]
DQS0
DQS0
DM0
DQ[0:7]
DQS2
DQS2
DM2
DQ[16:23]
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
240
1%
ZQ
D0
CASWECKCKCKE
240
1%
ZQ
D1
CASWECKCKCKE
A[0:N]
ODT
A[0:N]/BA[0:N]
ODT
A[0:N]/BA[0:N]
DQS1
DQS1
DM1
DQ[8:15]
DQS3
DQS3
DM3
DQ[24:31]
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
240
1%
ZQ
D4
CASWECKCKCKE
240
1%
ZQ
D5
CASWECKCKCKE
ODT
A[0:N]/BA[0:N]
ODT
A[0:N]/BA[0:N]
V
DDSPD
V
REFCA
V
REFDQ
ODT1
CKE1
RESET
V
V
CK0
CK0
CK1
CK1
SCL
SA0
SA1
V
DD
SS
S1
SCL
A0
(SPD)
A1
A2
WP
tt
SDA
V
tt
SPD
D0 - D7
D0 - D7
D0 - D7
D0 - D7, SPD
D0 - D7
D0 - D7
Terminated near
card edge
NC
NC
NC
D0 - D7
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
240
1%
ZQ
D2
CASWECKCKCKE
240
1%
ZQ
D3
ODT
A[0:N]/BA[0:N]
DQS5
DQS5
DM5
DQ[40:47]
DQS7
DQS7
DM7
DQ[56:63]
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
240
1%
ZQ
D6
CASWECKCKCKE
240
1%
ZQ
D7
ODT
A[0:N]/BA[0:N]
V
tt
D7D6D5D4
V4V3V2V1
V4V3V2V1
D3D2D1D0
tt
V
Address and Controllines
NOTE :
CS
RAS
CASWECKCKCKE
Vtt
V
DD
ODT
A[0:N]/BA[0:N]
CS
RAS
CASWECKCKCKE
Vtt
ODT
A[0:N]/BA[0:N]
Rank0
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and
are maintained as shown
DQS relationships
- 8 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
7.2 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
DQS3
DQS3
DM3
DQ[24:31]
DQS1
DQS1
DM1
DQ[8:15]
DQS0
DQS0
DM0
DQ[0:7]
S1
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CASWECK1
CK1
CKE1
240
1%
ZQ
D11
CASWECKCKCKE
240
1%
ZQ
D1
CASWECKCKCKE
240
1%
ZQ
D0
ODT1
/BA[0:N]
A[0:N]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
S0
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CK0
CK0
CKE0
240
1%
ZQ
D3
CASWECKCKCKE
240
1%
ZQ
D9
CASWECKCKCKE
240
1%
ZQ
D8
ODT0
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
Rank0
Rank1
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
DQS
DQS
DM
DQ[0:7]
V
DD
240
1%
ZQ
D12
CASWECKCKCKE
240
1%
ZQ
D6
CASWECKCKCKE
240
1%
ZQ
D7
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
Vtt
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:63]
V
DD
Vtt
Vtt
240
DQS
DQS
DM
DQ[0:7]
DQS
DQS
DM
DQ[0:7]
DQS
DQS
DM
DQ[0:7]
D4
CS
RAS
CASWECKCKCKE
D14
CS
RAS
CASWECKCKCKE
D15
1%
ZQ
240
1%
ZQ
240
1%
ZQ
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS2
DQS2
DM2
DQ[16:23]
SCL
SA0
SA1
SCL
A0
A1
A2
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
CASWECKCKCKE
240
1%
ZQ
D2
CASWECKCKCKE
(SPD)
WP
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
SDA
CS
RAS
DQS
DQS
DM
DQ[0:7]
CS
RAS
CASWECKCKCKE
240
1%
ZQ
D10
CASWECKCKCKE
V
tt
V
DDSPD
V
REFCA
V
REFDQ
V
DD
V
SS
CK0
CK1
CK0
CK1
RESET
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
CS
RAS
CASWECKCKCKE
DQS
DQS
DM
DQ[0:7]
D13
CS
RAS
CASWECKCKCKE
V
tt
SPD
D0 - D15
D0 - D15
D0 - D15
D0 - D15, SPD
D0 - D7
D8 - D15
D0 - D7
D8 - D15
D0 - D7
240
1%
ODT
ZQ
ODT
CS
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[0:7]
CS
A[N:0]/BA[N:0]
V3
V3
RAS
CASWECKCKCKE
240
1%
ZQ
D5
RAS
CASWECKCKCKE
V2
V4
V4
V2
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
V1
V9
V5
V1
V5
V
tt
V1
V9
NOTE :
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and
are maintained as shown
DQS5
DQS5
DM5
DQ[40:47]
V8
D6D12D3D9
V7
D7D5D10D8
V6
V6
D15D13D2D0
V7
D14D4D11D1
V8
Address and Controllines
DQS relationships
- 9 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
8. Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
V
DD
Voltage on V
V
DDQ
V
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and V
equal to or less than 300mV.
Voltage on any pin relative to V
IN, VOUT
T
Storage Temperature -55 to +100 C 1, 2
STG
DDQ
8.2 DRAM Component Operating Temperature Range
Symbol Parameter rating Unit NOTE
T
OPER
NOTE :
1. Operating Temperature T
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
Voltage on VDD pin relative to V
pin relative to V
DDQ
must be within 300mV of each other at all times;and V
SS
SS
SS
Operating Temperature Range 0 to 95 C 1, 2, 3
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
OPER
-0.4 V ~ -1.80 V V 1,3
-0.4 V ~ -1.80 V V 1,3
-0.4 V ~ -1.80 V V 1
must be not greater than 0.6 x V
REF
, When VDD and V
DDQ
are less than 500mV; V
DDQ
REF
may be
9. AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions
Symbol Parameter Operation Voltage
V
DD
V
DDQ
NOTE:
1. Under all conditions V
2. V
tracks with VDD. AC parameters are measured with VDD and V
DDQ
& V
3. V
DD
DDQ
Supply Voltage
Supply Voltage for Output
must be less than or equal to VDD.
DDQ
rating are determinied by operation voltage.
1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
DDQ
tied together.
Rating
Min. Typ. Max.
Units NOTE
- 10 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 1 ] Single Ended AC and DC input levels for Command and Address(1.35V)
Symbol Parameter
V
(DC90)
IH.CA
V
(DC90)
IL.CA
V
(AC160)
IH.CA
V
(AC160)
IL.CA
V
(AC135)
IH.CA
V
(AC135)
IL.CA
V
REFCA
NOTE :
1. For input only pins except
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),
VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not
apply when the device is operated in the 1.35 voltage range.
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic lowM Note 2
Reference Voltage for ADD,
(DC)
CMD inputs
RESET, V
REF
= V
REFCA
DDR3L-800/1066/1333/1600 DDR3L-1866
Min. Max. Min. Max.
1.35V
V
(DC)
+ 90 V
REF
V
SS
V
+ 160
REF
V
+135
REF
0.49*V
DD
DD
V
- 90 V
REF
Note 2 - - mV 1,2,5
V
- 160
REF
Note 2
V
-135
REF
0.51*V
DD
V
+ 90 V
REF
SS
- - mV 1,2,5
V
+135
REF
Note 2
V
+ 125
REF
Unit NOTE
DD
V
- 90
REF
mV 1
mV 1
Note 2 mV 1,2,5
V
REF
-135
mV 1,2,5
Note 2 V 3,4
[ Table 2 ] Single-ended AC & DC input levels for Command and Address(1.5V)
Symbol Parameter
DDR3-800/1066/1333/1600 DDR3-1866
Min. Max. Min. Max.
Unit NOTE
1.5V
V
(DC100)
IH.CA
V
(DC100)
IL.CA
V
(AC175)
IH.CA
V
(AC175)
IL.CA
V
(AC150)
IH.CA
V
(AC150)
IL.CA
(DC)
V
REFCA
NOTE :
1. For input only pins except
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is
referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is
used when Vref + 0.125V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is
referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is
used when Vref - 0.125V is referenced.
9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic low Note 2
Reference Voltage for
ADD, CMD inputs
RESET, V
REF
= V
REFCA
(DC)
V
+ 100 V
REF
V
SS
V
+ 175
REF
V
+150
REF
0.49*V
DD
DD
V
- 100
REF
V
SS
- - mV 1,6
V
REF
- 100
mV 1,5
Note 2 - - mV 1,2,7
V
REF
- 175
- - mV 1,2,8
Note 2 - - mV 1,2,7
V
-150 V
REF
0.51*V
DD
REF
Note 2
+ 135
Note 2 mV 1,2,8
- 135
V
REF
V 3,4,9
- 11 -
Rev. 1.1
Unbuffered SODIMM datasheet DDR3L SDRAM
[ Table 3 ] Single Ended AC and DC input levels for DQ and DM(1.35V)
Symbol Parameter
V
(DC90)
IH.DQ
V
(DC90)
IL.DQ
V
(AC160)
IH.DQ
V
(AC160)
IL.DQ
(AC135)
V
IH.DQ
V
(AC135)
IL.DQ
V
REF
DQ
NOTE :
1. For input only pins except
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV.
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/
L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the
device is operated in the 1.35 voltage range.
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic low Note 2
Reference Voltage for DQ,
(DC)
DM inputs
RESET, V
REF
= V
REFDQ
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
Min. Max. Min. Max. Min. Max.
1.35V
V
(DC)
REF
V
REF
V
REF
0.49*V
+ 90 V
V
SS
+ 160
+ 135
DD
DD
V
- 90 V
REF
Note 2 - - - - mV 1,2,5
V
- 160
REF
Note 2
V
- 135
REF
0.51*V
DD
V
+ 90 V
REF
SS
DD
V
- 90 V
REF
V
+ 90 V
REF
SS
- - - - mV 1,2,5
V
+ 135
REF
Note 2
0.49*V
DD
Note 2 - - mV 1,2,5
V
- 135
REF
0.51*V
DD
- - mV 1,2,5
V
+ 130
REF
Unit NOTE
DD
V
- 90
REF
mV 1
mV 1
Note 2 V 3,4
[ Table 4 ] Single-ended AC & DC input levels for DQ and DM (1.5V)
Symbol Parameter
DDR3-800/1066 DDR3-1333/1600 DDR3-1866
Min. Max. Min. Max. Min. Max.
Unit NOTE
1.5V
V
(DC100)
IH.DQ
(DC100)
V
IL.DQ
(AC175)
V
IH.DQ
V
(AC175)
IL.DQ
V
(AC150)
IH.DQ
(AC150)
V
IL.DQ
V
(AC135)
IH.DQ
V
(AC135)
IL.DQ
V
REF
DQ
NOTE :
1. For input only pins except
2. See "Overshoot and Undershoot specifications" on Component Datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,
VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,
VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. VrefDQ(DC) is measured relative to VDD at the same point in time on the same device
10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices
support this option
DC input logic high
DC input logic low
AC input logic high
AC input logic low NOTE 2
AC input logic high
AC input logic low NOTE 2
AC input logic high
AC input logic low NOTE 2
Reference Voltage for DQ,
(DC)
DM inputs
RESET, V
REF
= V
REFDQ
V
V
V
V
(DC)
REF
V
REF
REF
REF
0.49*V
+ 100 V
SS
+ 175
+ 150
+ 135
V
REF
NOTE 2 - - - - mV 1,2,7
V
REF
NOTE 2
V
REF
NOTE 2
V
REF
0.51*V
DD
DD
V
REF
- 100 V
- 175
V
REF
- 150
- 135
DD
NOTE 2
V
REF
NOTE 2
0.49*V
+ 100 V
SS
V
REF
DD
- 100 V
V
+ 100 V
REF
SS
DD
V
- 100
REF
mV 1,5
mV 1,6
- - - - mV 1,2,8
+ 150
+ 135
NOTE 2 - - mV 1,2,7
V
DD
REF
NOTE 2
V
REF
0.51*V
- 150
- 135
DD
- - mV 1,2,8
V
+ 135
REF
NOTE 2
0.49*V
DD
NOTE 2 mV 1,2,7,10
V
- 135
REF
0.51*V
DD
mV 1,2,8,10
V 3,4,9
- 12 -
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