SAMSUNG M470L1714BT0 Technical data

M470L1714BT0

200pin DDR SDRAM SODIMM

128MB DDR SDRAM MODULE

(16Mx64 based on 8Mx16 DDR SDRAM)

200pin SODIMM

64-bit Non-ECC/Parity

Revision 0.1

June. 2001

Rev. 0.1 June. 2001

M470L1714BT0

200pin DDR SDRAM SODIMM

Revision History

Revision 0.0 (Apr. 2001)

1. First release.

Revision 0.1 (June. 2001)

1. Changed module current speificaton

2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).

3. Changed AC parameter table.

Rev. 0.1 June. 2001

M470L1714BT0

200pin DDR SDRAM SODIMM

M470L1714BT0 200pin DDR SDRAM SODIMM

16Mx64 200pin DDR SDRAM SODIMM based on 8Mx16

GENERAL DESCRIPTION

The Samsung M470L1714BT0 is 16M bit x 64 Double Data

FEATURE

• Performance range

Rate SDRAM high density memory modules based on first gen
of 128Mb DDR SDRAM respectively.
The Samsung M470L1714BT0 consists of eight CMOS 8M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP­II(400mil) packages mounted on a 200pin glass-epoxy sub­strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L1714BT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys­tem applications.

M470L1714BT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L1714BT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M470L1714BT0-C(L)A0

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1250 (mil), double sided component

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

1

VREF

67

DQ27

135

3

VSS

69

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

/CK0

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133

VDD
CB0
CB1
VSS

DQS8

CB2
VDD
CB3

DU
VSS
CK2
/CK2
VDD

CKE1

DU(A13)

A12

A9

VSS

A7
A5
A3
A1

VDD

A10/AP

BA0
/WE

/S0

DU
VSS

DQ32
DQ33

VDD

DQS4

137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ34
DQ35

DQ40
DQ41

DQS5
DQ42

DQ43

DQ48
DQ49

DQS6
DQ50

DQ51
DQ56

DQ57
DQS7

DQ58
DQ59

VDDSPD

VDDID

VSS

VDD

VSS

VDD
VDD
VSS
VSS

VDD

VSS

VDD

VSS

VDD
SDA
SCL

2

VREF

68

4

VSS

6

DQ4

8

DQ5

10

VDD

12

DM0

14

DQ6

16

VSS

18

DQ7

20

DQ12

22

VDD

24

DQ13

26

DM1

28

VSS

30

DQ14

32

DQ15

34

VDD

36

VDD

38

VSS

40

VSS

KeyKey

42

DQ20

44

DQ21

46

VDD

48

DM2

50

DQ22

52

VSS

54

DQ23

56

DQ28

58

VDD

60

DQ29

62

DM3

64

VSS

66

DQ30

70
72
74
76
78
80
82
84
86
88
90
92
94
96

98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134

DQ31

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

DU/(RESET)

VSS
VSS
VDD
VDD

CKE0

DU(BA2)

VSS

VDD

BA1
/RAS
/CAS

VSS

DQ36
DQ37

VDD

DM4

A11

A8
A6

A4
A2
A0

/S1
DU

136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

Part No. Max Freq. Interface

SSTL_2

100MHz(10ns@CL=2)

PIN DESCRIPTION

Pin Name Function

DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

/CK1

CK1

VSS
DQ52
DQ53

VDD
DM6

DQ54

VSS
DQ55
DQ60

VDD

DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

DU

A0 ~ A11 Address input (Multiplexed)
BA0 ~ BA1 Bank Select Address
DQ0 ~ DQ63 Data input/output
DQS0 ~ DQS7 Data Strobe input/output
CK0~ CK2,

CK0~ CK2

Clock input

CKE0 Clock enable input
CS0 Chip select input
RAS Row address strobe
CAS Column address strobe
WE Write enable
DM0 ~ DM7 Data - in mask
VDD Power supply (2.5V)
VDDQ Power Supply for DQS(2.5V)
VSS Ground
VREF Power supply for reference
VDDSPD Serial EEPROM Power

Supply (2.3V to 3.6V)

SDA Serial data I/O
SCL Serial clock
SA0 ~ 2 Address in EEPROM
VDDID VDD identification flag
NC No connection

* These pins are not used in this module.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.1 June. 2001

M470L1714BT0

FUNCTIONAL BLOCK DIAGRAM

S1
S0

DQS0
DM0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS1
DM1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

S S

LDQS
LDM
I/0 0
I/0 1

D0

I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

D4

DQS4
DM4

DQS5
DM5

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

200pin DDR SDRAM SODIMM

LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

S S

D2

LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

D6

DQS2
DM2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS3
DM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D7
A0 - A13
RAS
CAS
CKE0
WE WE: SDRAMs D0 - D7

V

DDSPD

VDD/V

DDQ

VREF

V

SS

V

DDID Strap: see Note 4

LDQS
LDM

S S

I/0 0
I/0 1
I/0 2
I/0 3

D1

I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

A0-A13: DDR SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7

SPD
D0 - D7
D0 - D7
D0 - D7

D0 - D7

LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

SCL

WP

D5

Clock

Input

CK0/CK0
CK1/CK1
CK2/CK2

A0

SA0 SA1

DQS6
DM6

DQS7
DM7

Clock Wiring

Serial PD

A1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

SDRAMs

4 SDRAMs
4 SDRAMs

NC

A2

SA2

LDQS
LDM

S S

I/0 0
I/0 1
I/0 2
I/0 3

D3

I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

R=120Ω

± 5%

CK
CK

Card
Edge

*Clock Net Wiring

Notes:

1. DQ-to-I/O wiring is shown as recom­mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.

SDA

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.

LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15

Dram1

Dram2

Dram3

Dram4

D7

Rev. 0.1 June. 2001

M470L1714BT0

200pin DDR SDRAM SODIMM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V
Voltage on VDDQ supply relative to Vss
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 8 W
Short circuit current IOS 50 mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

VDDQ

-0.5 ~ 3.6 V

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter Symbol Min Max Unit Note

Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7
I/O Supply voltage VDDQ 2.3 2.7 V
I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1
I/O Termination voltage(system) V
Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4
Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4
Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V
Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3
Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5
Input leakage current II -2 2 uA
Output leakage current IOZ -5 5 uA
Output High Current(Normal strengh driver)

;V

= VTT + 0.84V

OUT

Output High Current(Normal strengh driver)
;V

= VTT - 0.84V

OUT

Output High Current(Half strengh driver)
;V

= VTT + 0.45V

OUT

Output High Current(Half strengh driver)
;V

= VTT - 0.45V

OUT

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

TT

IOH -16.8 mA

IOL 16.8 mA

IOH -9 mA

OL

I

VREF-0.04 VREF+0.04 V 2

9 mA

Rev. 0.1 June. 2001