SAMSUNG M392B2873GB0 Technical data

- 1 -

M392B2873GB0

M392B5670GB0

Rev. 1.01, Dec. 2010

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

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military or defense application, or any governmental procurement to which special terms or provisions

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datasheet

M392B5673GB0

240pin VLP Registered DIMM

based on 1Gb G-die

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

http://www.BDTIC.com/SAMSUNG

- 2 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First Release Nov. 2010 - S.H.Kim

1.01 - Corrected typo. Dec. 2010 - S.H.Kim

http://www.BDTIC.com/SAMSUNG

- 3 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

Table Of Contents

240pin VLP Registered DIMM based on 1Gb G-die

1. DDR3 VLP Registered DIMM Ordering Information ..................................................................................................... 4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration ..................................................................................................................................................4

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 5

5. Pin Description ............................................................................................................................................................. 6

6. ON DIMM Thermal Sensor ........................................................................................................................................... 6

7. Input/Output Functional Description..............................................................................................................................7

8. Pinout Comparison Based On Module Type................................................................................................................. 8

9. Registering Clock Driver Specification..........................................................................................................................9

9.1 Timing & Capacitance values .................................................................................................................................. 9

9.2 Clock driver Characteristics..................................................................................................................................... 9

10. Function Block Diagram:.............................................................................................................................................10

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 10

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 11

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 12

11. Absolute Maximum Ratings ........................................................................................................................................13

11.1 Absolute Maximum DC Ratings............................................................................................................................. 13

11.2 DRAM Component Operating Temperature Range .............................................................................................. 13

12. AC & DC Operating Conditions...................................................................................................................................13

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................13

13. AC & DC Input Measurement Levels ..........................................................................................................................14

13.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 14

13.2 V

REF

Tolerances.................................................................................................................................................... 15

13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 16

13.3.1. Differential Signals Definition ......................................................................................................................... 16

13.3.2. Differential Swing Requirement for Clock (CK - CK

) and Strobe (DQS - DQS) ............................................. 16

13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 17

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 18

13.4 Slew Rate Definition for Single Ended Input Signals .............................................................................................18

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 18

14. AC & DC Output Measurement Levels ....................................................................................................................... 19

14.1 Single Ended AC and DC Output Levels............................................................................................................... 19

14.2 Differential AC and DC Output Levels ................................................................................................................... 19

14.3 Single-ended Output Slew Rate ............................................................................................................................ 19

14.4 Differential Output Slew Rate ................................................................................................................................ 20

15. DIMM IDD specification definition ...............................................................................................................................21

16. IDD SPEC Table .........................................................................................................................................................23

17. Input/Output Capacitance ...........................................................................................................................................25

18. Electrical Characteristics and AC timing .....................................................................................................................26

18.1 Refresh Parameters by Device Density................................................................................................................. 26

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 26

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 26

18.3.1. Speed Bin Table Notes .................................................................................................................................. 30

19. Timing Parameters by Speed Grade ..........................................................................................................................31

19.1 Jitter Notes ............................................................................................................................................................37

19.2 Timing Parameter Notes........................................................................................................................................ 38

20. Physical Dimensions...................................................................................................................................................39

20.1 128Mbx8 based 128Mx72 Module (1 Rank) - M392B2873GB0 ............................................................................ 39

20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs ................................................................ 39

20.2 128Mbx8 based 256Mx72 Module (2 Ranks) - M392B5673GB0 .......................................................................... 40

20.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs .............................................................. 40

20.3 256Mbx4 based 256Mx72 Module (1 Rank) - M392B5670GB0 ............................................................................ 41

20.3.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs ................................................................ 41

http://www.BDTIC.com/SAMSUNG

- 4 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

1. DDR3 VLP Registered DIMM Ordering Information

NOTE :

1. "##" - F8/H9/K0/MA

2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 / MA - 1866Mbps 13-13-13

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2. Key Features

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

DDQ

= 1.5V ± 0.075V

• 400MHz f

for 800Mb/sec/pin, 533MHz f

for 1066Mb/sec/pin, 667MHz f

for 1333Mb/sec/pin, 800MHz f

for 1600Mb/sec/pin,

900MHz f

for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable

CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted

CAS) : 0, CL - 2, or CL - 1 clock

• Programmable

CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with st

arting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

CASE

85°C, 3.9us at 85°C < T

CASE

≤ 95°C

• Asynchronous Reset

3. Address Configuration

Part Number

Density Organization Component Composition

Number of

Rank

Height

M392B2873GB0-CF8/H9/K0/MA

1GB 128Mx72

128Mx8(K4B1G0846G-BC##

)*9

1 18.75mm

M392B5673GB0-CF8/H9/K0/MA

2GB 256Mx72

128Mx8(K4B1G0846G-BC##

)*18

2 18.75mm

M392B5670GB0-CF8/H9/K0/MA

2GB 256Mx72

256Mx4(K4B1G0446G-BC##

)*18

1 18.75mm

Speed

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Unit

6-6-6 7-7-7 9-9-9 11-11- 11 13-13-13

tCK(min) 2.5 1.875 1.5 1.25 1.07 ns

CAS Latency 6 7 9 11 13 nCK

tRCD(min) 15 13.125 13.5 13.75 13.91 ns

tRP(min) 15 13.125 13.5 13.75 13.91 ns

tRAS(min) 37.5 37.5 36 35 34 ns

tRC(min) 52.5 50.625 49.5 48.75 47.91 ns

Organization Row Address Column Address Bank Address Auto Precharge

256Mx4(1Gb) based Module A0-A13 A0-A9, A11 BA0-BA2 A10/AP

128Mx8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10/AP

http://www.BDTIC.com/SAMSUNG

- 5 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

4. Registered DIMM Pin Configurations (Front side/Back side)

NOTE : NC = No internal Connection

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

REFDQ

121

42 DQS8162

NC,DQS

,TDQS

82 DQ33 202

122 DQ4 43 DQS8 163

203

DM4,DQS13

,TDQS13

3DQ0123DQ544

164 CB6,NC 84 DQS4 204

NC,DQS

,TDQS

4DQ1124

45 CB2,NC 165 CB7,NC 85 DQS4 205

125

DM0,DQS9

,TDQS9

46 CB3,NC 166

206 DQ38

6DQS

0126

NC,DQS

,TDQS

167 NC(TEST) 87 DQ34 207 DQ39

7DQS0127

, NC

168 RESET

88 DQ35 208

128 DQ6

KEY

209 DQ44

9DQ2129DQ749

, NC

169 CKE1, NC 90 DQ40 210 DQ45

10 DQ3 130

50 CKE0 170

91 DQ41 211

131 DQ12 51

171 NC 92

212

DM5,DQS14

,TDQS14

12 DQ8 132 DQ13 52 BA2 172 NC 93 DQS

5 213

NC,DQS

,TDQS

13 DQ9 133

53 Err_Out/NC 173

94 DQS5 214

134

DM1,DQS10

,TDQS10

174 A12/BC 95

215 DQ46

15 DQS

1135

NC,DQS

,TDQS

55 A11 175 A9 96 DQ42 216 DQ47

16 DQS1 136

56 A7 176

97 DQ43 217

137 DQ14 57

177 A8 98

218 DQ52

18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53

19 DQ11 139

59 A4 179

100 DQ49 220

140 DQ20 60

180 A3 101

221

DM6,DQS15

,TDQS15

21 DQ16 141 DQ21 61 A2 181 A1 102 DQS

6 222

NC,DQS

,TDQS

22 DQ17 142

182

103 DQS6 223

143

DM2,DQS11

,TDQS11

63 NC, CK1 183

104

224 DQ54

24 DQS

2144

NC,DQS

,TDQS

64 NC, CK

1 184 CK0 105 DQ50 225 DQ55

25 DQS2 145

185 CK0 106 DQ51 226

146 DQ22 66

186

107

227 DQ60

27 DQ18 147 DQ23 67

REFCA

187 EVENT,NC 108 DQ56 228 DQ61

28 DQ19 148

68 NC/Par_In 188 A0 109 DQ57 229

149 DQ28 69

189

110

230

DM7/DQS16

TDQS16

30 DQ24 150 DQ29 70 A10/AP 190 BA1

111

DQS7

231

DM7,DQS

,TDQS

31 DQ25 151

71 BA0 191

112 DQS7 232

152

DM3,DQS12

,TDQS12

192 RAS 113

233 DQ62

33 DQS

3153

NC,DQS

,TDQS

73 WE

193 S0 114 DQ58 234 DQ63

34 DQS3 154

74 CAS 194

115 DQ59 235

155 DQ30 75

195 ODT0 116

236

DDSPD

36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1

37 DQ27 157

77 ODT1,NC 197

118 SCL 238 SDA

158 CB4,NC 78

198 S3,NC 119 SA2 239

39 CB0,NC 159 CB5,NC 79 S2,NC 199

120

240

40 CB1,NC 160

200 DQ36

161

DM8,DQS17

TDQS17,NC

81 DQ32 201 DQ37

http://www.BDTIC.com/SAMSUNG

- 6 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

5. Pin Description

NOTE :

*The V

and V

DDQ

pins are tied common to a single power-plane on these designs.

6. ON DIMM Thermal Sensor

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.

When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Pin Name Description Number Pin Name Description Number

CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2

CK0

Clock Input, negative line 1 DQ[63:0] Data Input/Output 64

CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8

RAS

Row Address Strobe 1 DQS[8:0] Data strobes 9

CAS

Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9

Write Enable 1

DM[8:0]/

DQS[17:9]

TDQS[17:9]

Data Masks/ Data strobes,

Termination data strobes

[3:0] Chip Selects 4

DQS

[17:9]

TDQS

[17:9]

Data strobes, negative line, Termination data

strobes

A[9:0],A11,

A[15:13]

Address Inputs 2\14 RFU Reserved for Future Use 2

A10/AP Address Input/Autoprecharge 1 EVENT

Reserved for optional hardware temperature

sensing

A12/BC

Address Input/Burst chop 1 TEST

Memory bus test toll (Not Connected and Not

Usable on DIMMs)

BA[2:0] SDRAM Bank Addresses 3 RESET

SCL Serial Presence Detect (SPD) Clock Input 1

Power Supply 22

SDA SPD Data Input/Output 1

Ground 59

SA[2:0] SPD Address Inputs 3

REFDQ

Reference Voltage for DQ 1

Par_In Parity bit for the Address and Control bus 1

REFCA

Reference Voltage for CA 1

Err_Out

Parity error found on the Address and Control

bus

Termination Voltage 4

DDSPD

SPD Power 1

Total 240

Grade Range

Temperature Sensor Accuracy

Units NOTE

Min. Typ . Max.

75 < Ta < 95 - +/- 0.5 +/- 1.0

°C

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 °C /LSB -

SCL

SDA

WP/EVENT

SA0 SA1 SA2

EVENT

0 Ω

http://www.BDTIC.com/SAMSUNG

- 7 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

7. Input/Output Functional Description

Symbol Typ e Polarity Function

CK0 Input

Positive

Edge

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

CK0

Input

Negative

Edge

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CKE[1:0] Input Active High

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers

and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN

and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

[3:0] Input Active Low

Enables the associated SDRAM command decoder when low and disables decoder when high.

When decoder is disabled, new commands are ignored and previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both

inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in

the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-

ister outputs.

ODT[1:0] Input Active High On-Die Termination control signals

AS, CAS, WE Input Active Low

When sampled at the positive rising edge of the clock, CAS

, RAS, and WE define the operation to be exe-

cuted by the SDRAM.

REFDQ

Supply Reference voltage for DQ0-DQ63 and CB0-CB7

REFCA

Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.

BA[2:0] Input

Selects which SDRAM bank of eight is activated.

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank

address also determines mode register is to be accessed during an MRS cycle.

A[15:13,

12/BC,11,

10/AP,9:0]

Input

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/

Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-

ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks

(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8

identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during

Mode Register Set commands.

DQ[63:0],

CB[7:0]

I/O Data and Check Bit Input/Output pins

DM[8:0]

Active High Masks write data when high, issued concurrently with input data.

, V

Supply Power and ground for the DDR SDRAM input buffers and core logic.

Supply Termination Voltage for Address/Command/Control/Clock nets.

DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.

DQS

[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.

TDQS[17:9],

TDQS

[17:9] OUT

TDQS/TDQS

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will

enable the same termination resistance function on TDQS/TDQS

that is applied to DQS/DQS. When dis-

abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.

X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

SA[2:0] IN

These signals are tied at the system planar to either V

or V

DDSPD

to configure the serial SPD EEPROM

address range.

SDA I/O

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be

connected from the SDA bus line to V

DDSPD

on the system planar to act as a pull-up.

SCL IN

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected

from the SCL bus time to V

DDSPD

on the system planar to act as a pull-up.

EVENT

OUT

(open

drain)

Active Low

This signal indicates that a thermal event has been detected in the thermal sensing device.The system

should guarantee the electrical level requirement is met for the EVENT

pin on TS/SPD part.

DDSPD

Supply

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

RESET

The RESET

pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When

low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set

to low level (the Clock Driver will remain synchronized with the input clock)

Par_In IN Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)

Err_Out

OUT

(open

drain)

Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out

bus line to V

on the system planar to act as a pull up.

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

http://www.BDTIC.com/SAMSUNG

- 8 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

8. Pinout Comparison Based On Module Type

NOTE : NC = No internal Connection

RDIMM UDIMM

Signal NOTE Signal NOTE

48, 49

Additional connection for Termination Voltage for

Address/Command/Control/Clock nets.

NC Not used on UDIMMs

120, 240

Termination Voltage for Address/Command/Con-

trol/Clock nets.

Termination Voltage for Address/Command/Con-

trol/Clock nets.

53 Err_Out

Connected to the register on all RDIMMs NC Not

used on UDIMMs

NC NC Not used on UDIMMs

63 NC

Not used on RDIMMs

CK1

Used for 2 rank UDIMMs, not used on single-rank

UDIMMs, but terminated

64 NC CK1

68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs

76 S

1 Connected to the register on all RDIMMs S1

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

77 ODT1, NC

Connected to the register on dual- and quadrank

RDIMMs; NC on single-rank RDIMMs

ODT1,NC

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

79 S

2, NC

Connected to the register on quad-rank

RDIMMs, not connected on single or dual rank

RDIMMs

NC Not used on UDIMMs

167 NC TEST input used only on bus analysis probes NC

TEST input used only on bus analysis

probes

169 CKE1

Connected to the register on dual- and quadrank

RDIMMs; NC on single-rank RDIMMs

CKE1,

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

171 A15

Connected to the register on all RDIMMs

A15, NC Depending on device density, may not be

connected to SDRAMs on UDIMMs. However,

these signals are terminated on

UDIMMs. A15 not routed on some RCs

172 A14 A14

196 A13 A13

198 S

3, NC

Connected to the register on quad-rank

RDIMMs, not connected on single-or dual-rank

RDIMMs

NC Not used on UDIMMs

39, 40, 45, 46,

158, 159, 164,

165

CBn Used on all RDIMMs; (n = 0...7) NC, CBn

Used on x72 UDIMMs, (n = 0...7); not

used on x64 UDIMMs

125, 134, 143,

152, 161, 203,

212, 221, 230

DQSn,

TDQSn

Connected to DQS on x4 SDRAMs,

TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

DMn

Connected to DM on x8 DRAMs, UDM or

LDM on x16 DRAMs on UDIMMs;

(n = 0...8)

126, 135, 144,

153, 162, 204,

213, 222, 231

DQS

TDQS

Connected to DQS

on x4 DRAMs, TDQS on x8

SDRAMs on RDIMMs; (n=9...17)

NC Not used on UDIMMs

187

EVENT

Connected to optional thermal sensing compo-

nent.

NC on Modules without a thermal sensing

component.

NC Not used on UDIMMs

http://www.BDTIC.com/SAMSUNG

- 9 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

9.2 Clock driver Characteristics

Symbol Parameter Conditions

= TBD

= 1.5 ± 0.075V

Units Notes

Min Max

fclock Input Clock Frequency application frequency 300 670 MHz

Pulse duration, CK, CK HIGH or LOW 0.4 -

ACT

Inputs active time4 before RESET is taken HIGH

DCKE0/1 = LOW and

DCS0/1

= HIGH

Setup time Input valid before CK/CK 100 - ps

Hold time

Input to remain Valid after CK/

175 -

PDM

Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns

DIS

output disable time(1/2-Clock pre-launch)

CK/CK

to output float

0.5 -

output disable time(3/4-Clock pre-launch) 0.25 -

output enable time(1/2-Clock pre-launch)

CK/CK

to output driving

-0.5

output enable time(3/4-Clock pre-launch) - 0.25

(DATA)

Data Input Capacitance 1.5 2.5

(CLOCK)

Data Input Capacitance 2 3

(RST)

Reset Input Capacitance - 3

Symbol Parameter Conditions

= TBD

= 1.5 ± 0.075V

Units Notes

Min Max

jit

(cc)

Cycle-to-cycle period jitter 0 40 ps

STAB

Stabilization time -6us

fdyn

Dynamic phase offset -50 50 ps

CKsk

Clock Output skew 50 ps

jit

(per)

Yn Clock Period jitter -40 40 ps

jit

(hper)

Half period jitter -50 50 ps

Qsk1

Qn Output to clock tolerance (Standard 1/2 -Clock

Pre-Launch)

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

Qsk1

Output clock tolerance (3/4 Clock Pre-Launch)

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

dynoff

Maximum re-driven dynamic clock off-set -80 80 ps

http://www.BDTIC.com/SAMSUNG

- 10 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

10. Function Block Diagram:

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

DQS8

DM8/DQS17

DQS

CB[7:0]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCLE0A

RODT0A

A[N:0]A

/BA[N:0]A

DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

Vtt

DQS4

DM4/DQS13

DQS

DQ[39:32]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCLE0B

RODT0B

A[N:0]B

/BA[N:0]B

DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS6

DM6/DQS15

DQS15

DQ[55:48]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

Vtt

D0 - D8

REFCA

DDSPD

Serial PD

1:2

S1*

BA[N:0]

A[N:0]

RAS

CAS

CKE0

CK0

RESET

RST

** : SDRAMs D[8:0]

RS0B-> CS0 : SDRAMs D[7:4]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8

RRASA

-> RAS : SDRAMs D[3:0], D8

RCASA

-> CAS : SDRAMs D[3:0], D8

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

ODT0

PAR_IN

RODT0A -> ODT0 : SDRAMs D[3:0], D8

S0* RS0A-> CS0 : SDRAMs D[3:0], D8

EVENT EVENT

REFDQ

D0 - D8

NOTE :

1. ZQ resistors are 240Ω ± 1% For all other resistor values refer to the appropriate

wiring diagram.

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4]

RRASB

-> RAS : SDRAMs D[7:4]

RCASB

-> CAS : SDRAMs D[7:4]

RWEA

-> WE : SDRAMs D[3:0], D8

RWEB

-> WE : SDRAMs D[7:4]

RCKE0B -> CKE0 : SDRAMs D[7:4]

RODT0B -> ODT0 : SDRAMs D[7:4]

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0A -> CK : SDRAMs D[7:4]

PCK

0A -> CK : SDRAMs D[3:0], D8

PCK

0A -> CK : SDRAMs D[7:4]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)

http://www.BDTIC.com/SAMSUNG

- 11 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

DQS8

DM8/DQS17

DQS17

CB[7:0]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

Vtt

D0 - D17

REFCA

DDSPD

Serial PD

EVENT EVENT

REFDQ

D0 - D17

NOTE :

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. RS0 and RS1 alternate between the back and front sides of the DIMM.

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

wiring diagram.

4. See the wiring diagrams for all resistors associated with the command, address

and control bus.

DQS

TDQS

DQ[7:0]

D17

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS1A

PCK1A

RCKE1A

RODT1A

DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D12

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D11

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D10

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS4

DM4/DQS13

DQS13

DQ[39:32]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCKE0B

RODT0B

A[N:0]B

/BA[N:0]B

Vtt

DQS

TDQS

DQ[7:0]

D13

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS1B

PCK1B

RCKE1B

RODT1B

DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D14

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS6

DM6/DQS15

DQS15

DQ[55:48]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D15

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS

TDQS

DQ[7:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQS

TDQS

DQ[7:0]

D16

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

1:2

S1*

BA[N:0]

A[N:0]

RAS

CAS

CKE0

RESET

RST

** : SDRAMs D[8:0]

RS1B-> CS1 : SDRAMs D[16:13]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RRASA

-> RAS : SDRAMs D[3:0], D[12:8], D17

RCASA

-> CAS : SDRAMs D[3:0], D[12:8], D17

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

PAR_IN

S0* RS0A-> CS0 : SDRAMs D[3:0], D8

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]

RRASB

-> RAS : SDRAMs D[7:4], D[16:13]

RCASB

-> CAS : SDRAMs D[7:4], D[16:13]

RWEA

-> WE : SDRAMs D[3:0], D[12:8], D17

RWEB

-> WE : SDRAMs D[7:4], D[16:13]

RCKE0B -> CKE0 : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17

PCK1B -> CK : SDRAMs D[16:13]

PCK

0A -> CK : SDRAMs D[3:0], D8

PCK

0B -> CK : SDRAMs D[7:4]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

CKE1

RCKE1A -> CKE1 : SDRAMs D[12:9], D17

RCKE1B -> CKE1 : SDRAMs D[16:13]

ODT0

RODT0A -> ODT0 : SDRAMs D[3:0], D8

RODT0B -> ODT0 : SDRAMs D[7:4]

ODT1

RODT1A -> ODT1 : SDRAMs D[12:9], D17

RODT1A -> ODT1 : SDRAMs D[16:13]

CK0

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0B -> CK : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17

PCK

1B -> CK : SDRAMs D[16:13]

0B-> CS0 : SDRAMs D[7:4]

1A-> CS1 : SDRAMs D[12:9], D17

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

http://www.BDTIC.com/SAMSUNG

- 12 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

DQ[27:24]

DQ[19:16]

DQS8

CB[3:0]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

VSS

DQS17

CB[7:4]

DQS

D17

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS3

DQS

DQ[27:24]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQS

DQ[31:28]

DQS

D12

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQ[19:16]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQ[23:20]

DQS

D11

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQ[11:8]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQ[15:12]

DQS

D10

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQS

DQ[3:0]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQS

DQ[7:4]

DQS

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQ[35:32]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCKE0B

RODT0B

A[N:0]B

/BA[N:0]B

VSS

DQS17

DQ[39:36]

DQS

D13

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQS

DQ[43:40]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQS

DQ[47:44]

DQS

D14

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQ[51:48]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQ[55:52]

DQS

D15

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8

DQ[59:56]

DQS

DQ[3:0]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17

DQ[63:60]

DQS

D16

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

Vtt

D0 - D17

REFCA

DDSPD

Serial PD

REFDQ

D0 - D17

NOTE :

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. See the wiring diagrams for all resistors associated with the command, address

and control bus.

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

wiring diagram.

1:2

S1*

BA[N:0]

A[N:0]

RAS

CAS

CKE0

RESET

RST

** : SDRAMs D[17:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RRASA

-> RAS : SDRAMs D[3:0], D[12:8], D17

RCASA

-> CAS : SDRAMs D[3:0], D[12:8], D17

RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17

PAR_IN

S0* RS0A-> CS0 : SDRAMs D[3 :0], D[12:8], D17

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]

RRASB

-> RAS : SDRAMs D[7:4], D[16:13]

RCASB

-> CAS : SDRAMs D[7:4], D[16:13]

RWEA

-> WE : SDRAMs D[3:0], D[12:8], D17

RWEB

-> WE : SDRAMs D[7:4], D[16:13]

RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]

PCK

0A -> CK : SDRAMs D[3:0], D[12:8], D17

PCK

0B -> CK : SDRAMs D[7:4], D[16:13]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

ODT0

RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17

RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]

CK0

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17

PCK0B -> CK : SDRAMs D[7:4], D[16:13]

RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]

(Unused register inputs ODT1 and CKE1 have a 330

Ω

resistor to ground)

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

EVENT EVENT

http://www.BDTIC.com/SAMSUNG

- 17 -

datasheet DDR3 SDRAM

Rev. 1.01

VLP Registered DIMM

11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the cente

r/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. V

and V

DDQ

must be within 300mV of each other at all times; and V

REF

must be not greater than 0.6 x V

DDQ

, When V

and V

DDQ

are less than 500mV; V

REF

may be

equal to or less than 300mV.

11.2 DRAM Component Operating Temperature Range

NOTE :

1. Operating Temperature T

OPER

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

JESD51-2.

2. The Normal Temperature Range specifies the temperatures where al

l DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between 0-85°C u

nder all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C

and 95°C case temperature. Full specifications are guaranteed in this range, but the

following additional conditions apply:

a) Refresh commands must be doubled in frequency, theref

ore reducing the refresh interval tREFI to 3.9us.

b) If Self-Refresh operation is required in the Extended Temperature Rang

e, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions (SSTL-15)

NOTE:

1. Under all conditions V

DDQ

must be less than or equal to V

2. V

DDQ

tracks with V

. AC parameters are measured with V

and V

DDQ

tied together.

Symbol Parameter Rating Units NOTE

Voltage on V

pin relative to V

-0.4 V ~ 1.975 V V 1,3

DDQ

Voltage on V

DDQ

pin relative to V

-0.4 V ~ 1.975 V V 1,3

IN,

OUT

Voltage on any pin relative to V

-0.4 V ~ 1.975 V V 1

STG

Storage Temperature -55 to +100 °C 1, 2

Symbol Parameter rating Unit NOTE

OPER

Operating Temperature Range 0 to 95 °C 1, 2, 3

Symbol Parameter

Rating

Units NOTE

Min. Typ . Max.

Supply Voltage 1.425 1.5 1.575 V 1,2

DDQ

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

http://www.BDTIC.com/SAMSUNG

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