Samsung M391A1K43BB2-CTD User Manual
Rev. 1.1, Apr. 2018
M391A1K43BB1
M391A1K43BB2
M391A2K43BB1
288pin ECC Unbuffered DIMM based on 8Gb B-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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- 1 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
Revision History
Revision No. History Draft Date Remark Editor
0.5 - First SPEC release 15th Nov, 2017 Preliminary J.Y.Bae
- Separate ECC and Non ECC datasheets. J.H.Han
1.0 - Final datasheet. 13th Dec, 2017 Final J.Y.Bae
- Correct typo. J.H.Han
- Correct speed bin table numbering.
- Add DRAM Package Electrical Specifications (x4/x8) table.
1.1 - Correct typo in Key features. 26th Apr, 2018 Final C.M.Kang
- Update Single-ended AC & DC Input Levels for Command and Address
table.
- Update Differential AC and DC Input Levels table.
- Update Cross point voltage for differential input signals (CK) table.
- Update Differential AC and DC Input Levels for DQS table.
- Update Differential Input Level for DQS_t, DQS_c table.
- Update Differential Input Slew Rate for DQS_t, DQS_c table.
- Update Output Driver DC Electrical Characteristics, assuming
RZQ=240ohm; entire operating temperature range; after proper ZQ calibration table.
Rev. 1.1
J.Y.Bae
- Update AC Timing table for 2666Mbps.
1. tDLLK : 854 -> 1024 [nCK].
2. tXPR_GEAR Min. : TBD -> tXPR
3. tXS_GEAR Min. : TBD -> tXS
4. tSYNC_GEAR Min. : TBD -> tMOD + 4tCK
5. tCMD_GEAR Min. : TBD -> tMOD
- Update DRAM DQs In Receive Mode table.
- Update Command, Address, Control Setup and Hold Values table.
- Command, Address, Control Input Voltage Values table.
- 2 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
Table Of Contents
288pin ECC Unbuffered DIMM based on 8Gb B-die
1. DDR4 Unbuffered DIMM ORDERING INFORMATION....................................................................................................................... 5
2. KEY FEATURES ................................................................................................................................................................................. 5
3. ADDRESS CONFIGURATION ............................................................................................................................................................ 5
4. x72 DIMM Pin Configurations (Front side/Back side).......................................................................................................................... 6
5. PIN DESCRIPTION ............................................................................................................................................................................ 7
6. INPUT/OUTPUT FUNCTIONAL DESCRIPTION ................................................................................................................................ 8
6.1 Address Mirroring ...........................................................................................................................................................................10
7. FUNCTION BLOCK DIAGRAM: .......................................................................................................................................................... 11
7.1 8GB, 1Gx72 ECC Module (Populated as 1 rank of x8 DDR4 SDRAMs)........................................................................................11
7.2 16GB, 2Gx72 ECC Module (Populated as 2 ranks of x8 DDR4 SDRAMs) ....................................................................................12
8. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................................... 13
9. AC & DC OPERATING CONDITIONS ................................................................................................................................................ 13
10. AC & DC INPUT MEASUREMENT LEVELS..................................................................................................................................... 14
10.1 AC & DC Logic Input Levels for Single-Ended Signals.................................................................................................................14
10.2 AC and DC Input Measurement Levels: VREF Tolerances..........................................................................................................14
10.3 AC and DC Logic Input Levels for Differential Signals .................................................................................................................15
10.3.1. Differential Signals Definition ................................................................................................................................................15
10.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ....................................................................................................15
10.3.3. Single-ended Requirements for Differential Signals .............................................................................................................16
10.3.4. Address, Command and Control Overshoot and Undershoot specifications........................................................................17
10.3.5. Clock Overshoot and Undershoot Specifications..................................................................................................................18
10.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications......................................................................................19
10.4 Slew Rate Definitions....................................................................................................................................................................20
10.4.1. Slew Rate Definitions for Differential Input Signals (CK) ......................................................................................................20
10.4.2. Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ........................................................................................21
10.5 Differential Input Cross Point Voltage...........................................................................................................................................22
10.6 CMOS rail to rail Input Levels .......................................................................................................................................................23
10.6.1. CMOS rail to rail Input Levels for RESET_n .........................................................................................................................23
10.7 AC and DC Logic Input Levels for DQS Signals...........................................................................................................................24
10.7.1. Differential signal definition ...................................................................................................................................................24
10.7.2. Differential swing requirements for DQS (DQS_t - DQS_c)..................................................................................................24
10.7.3. Peak voltage calculation method .......................................................................................................................................... 25
10.7.4. Differential Input Cross Point Voltage ...................................................................................................................................26
10.7.5. Differential Input Slew Rate Definition ..................................................................................................................................27
11. AC AND DC OUTPUT MEASUREMENT LEVELS ........................................................................................................................... 28
11.1 Output Driver DC Electrical Characteristics..................................................................................................................................28
11.1.1. Alert_n output Drive Characteristic .......................................................................................................................................30
11.1.2. Output Driver Characteristic of Connectivity Test (CT) Mode...............................................................................................31
11.2 Single-ended AC & DC Output Levels..........................................................................................................................................32
11.3 Differential AC & DC Output Levels..............................................................................................................................................32
11.4 Single-ended Output Slew Rate ...................................................................................................................................................33
11.5 Differential Output Slew Rate .......................................................................................................................................................34
11.6 Single-ended AC & DC Output Levels of Connectivity Test Mode ...............................................................................................35
11.7 Test Load for Connectivity Test Mode Timing ..............................................................................................................................36
12. SPEED BIN ....................................................................................................................................................................................... 37
12.1 Speed Bin Table Note...................................................................................................................................................................42
13. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS ................................................................................. 43
13.1 IDD, IPP and IDDQ Measurement Conditions..............................................................................................................................43
14. IDD SPEC TABLE ............................................................................................................................................................................. 58
15. INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 61
16. ELECTRICAL CHARACTERISTICS & AC TIMING .......................................................................................................................... 62
16.1 Reference Load for AC Timing and Output Slew Rate .................................................................................................................62
16.2 tREFI.............................................................................................................................................................................................62
16.3 Clock Specification .......................................................................................................................................................................63
16.3.1. Definition for tCK(abs)...........................................................................................................................................................63
16.3.2. Definition for tCK(avg)...........................................................................................................................................................63
16.3.3. Definition for tCH(avg) and tCL(avg)....................................................................................................................................63
16.3.4. Definition for tERR(nper).......................................................................................................................................................63
17. TIMING PARAMETERS BY SPEED GRADE ................................................................................................................................... 64
17.1 Rounding Algorithms ...................................................................................................................................................................70
17.2 The DQ input receiver compliance mask for voltage and timing ..................................................................................................71
17.3 Command, Control, and Address Setup, Hold, and Derating .......................................................................................................75
17.4 DDR4 Function Matrix ..................................................................................................................................................................77
18. PHYSICAL DIMENSIONS ................................................................................................................................................................. 79
18.1 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB1 .............................................................................................................79
18.2 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB2 .............................................................................................................80
18.3 1Gx8 based 2Gx72 Module (2 Ranks) - M391A2K43BB1............................................................................................................81
Rev. 1.1
- 3 -
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
1. DDR4 Unbuffered DIMM ORDERING INFORMATION
[Table 1] Ordering Information Table
Part Number
M391A1K43BB1-CPB/RC 8GB 1Gx72 1Gx8(K4A8G085WB-BCPB/RC)*9 1 31.25mm
M391A1K43BB2-CTD 8GB 1Gx72 1Gx8(K4A8G085WB-BCTD)*9 1 31.25mm
M391A2K43BB1-CPB/RC/TD 16GB 2Gx72 1Gx8(K4A8G085WB-BC##)*18 2 31.25mm
NOTE :
1) "##" -PB/RC/TD
2) PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)
- DDR4-2666(19-19-19) is backward compatible to lower frequency.
2)
Density Organization
Component Composition
1)
2. KEY FEATURES
[Table 2] Speed Bins
Speed
tCK(min) 1.25 1.071 0.937 0.833 0.75 ns
CAS Latency 11 13 15 17 19 nCK
tRCD(min) 13.75 13.92 14.06 14.16 14.25 ns
tRP(min) 13.75 13.92 14.06 14.16 14.25 ns
tRAS(min) 35 34 33 32 32 ns
tRC(min) 48.75 47.92 47.06 46.16 46.25 ns
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
11-11-11 13-13-13 15-15-15 17-17-17 19-19-19
Number of
Rank
Height
Unit
• JEDEC standard 1.2V ± 0.06V Power Supply
•V
= 1.2V ± 0.06V
DDQ
• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin,1333MHz
for 2666Mb/sec/pin
f
CK
• 16 Banks (4 Bank Groups)
• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20
• Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866), 11,14 (DDR4-2133), 12,16 (DDR4-2400) and 14,18 (DDR4-
2666)
• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
85C, 3.9us at 85C < T
CASE
CASE
95C
3. ADDRESS CONFIGURATION
Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge
512Mx16(8Gb) based Module A0-A15 A0-A9 BG0 BA0-BA1 A10/AP
1Gx8(8Gb) based Module A0-A15 A0-A9 BG0-BG1 BA0-BA1 A10/AP
- 4 -
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
4. x72 DIMM Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 1.2V,NC 145 1.2V,NC 39 VSS 183 DQ25 77 VTT 221 VTT 114 VSS 258 DQ47
2 VSS 146 VREFCA 40
3 DQ4 147 VSS 41
4 VSS 148 DQ5 42 VSS 186 DQS3_t 79 A0 223 VDD 117 DQ52 261 VSS
5 DQ0 149 VSS 43 DQ30 187 VSS 80 VDD 224 BA1 118 VSS 262 DQ53
6 VSS 150 DQ1 44 VSS 188 DQ31 81 BA0 225 A10/AP 119 DQ48 263 VSS
TDQS9_t,DQS
7
9_t,DM0_n,DB
I0_n,NC
TDQS9_c,DQ
8
S9_c,NC
9 VSS 153 DQS0_t 47 CB4,NC 191 VSS 84 CS0_n 228 WE_n/A14 122
10 DQ6 154 VSS 48 VSS 192 CB5,NC 85 VDD 229 VDD 123 VSS 267 DQS6_t
11 VSS 155 DQ7 49 CB0,NC 193 VSS 86 CAS_n/A15 230 NC,SAVE_n 124 DQ54 268 VSS
12 DQ2 156 VSS 50 VSS 194 CB1,NC 87 ODT0 231 VDD 125 VSS 269 DQ55
13 VSS 157 DQ3 51
14 DQ12 158 VSS 52
15 VSS 159 DQ13 53 VSS 197 DQS8_t 90 VDD 234 NC,A17 128 DQ60 272 VSS
16 DQ8 160 VSS 54 CB6,NC 198 VSS 91 ODT1 235 NC,C2 129 VSS 273 DQ61
17 VSS 161 DQ9 55 VSS 199 CB7,NC 92 VDD 236 VDD 130 DQ56 274 VSS
TDQS10_t,DQ
18
S10_t,DM1_n,
DBI1_n,NC
TDQS10_c,DQ
19
S10_c,NC
20 VSS 164 DQS1_t 58 RESET_n 202 VSS 95 DQ36 239 VSS 133
21 DQ14 165 VSS 59 VDD 203 CKE1 96 VSS 240 DQ37 134 VSS 278 DQS7_t
22 VSS 166 DQ15 60 CKE0 204 VDD 97 DQ32 241 VSS 135 DQ62 279 VSS
23 DQ10 167 VSS 61 VDD 205 RFU 98 VSS 242 DQ33 136 VSS 280 DQ63
24 VSS 168 DQ11 62 ACT_n 206 VDD 99
25 DQ20 169 VSS 63 BG0 207 BG1 100
26 VSS 170 DQ21 64 VDD 208 ALERT_n 101 VSS 245 DQS4_t 139 SA0 283 VSS
27 DQ16 171 VSS 65 A12/BC_n 209 VDD 102 DQ38 246 VSS 140 SA1 284 VDDSPD
28 VSS 172 DQ17 66 A9 210 A11 103 VSS 247 DQ39 141 SCL 285 SDA
TDQS11_t,DQ
29
S11_t,DM2_n,
DBI2_n,NC
TDQS11_t,DQ
30
S11_t,NC
31 VSS 175 DQS2_t 69 A6 213 A5 106 DQ44 250 VSS 144 RFU 288 VPP
32 DQ22 176 VSS 70 VDD 214 A4 107 VSS 251 DQ45
33 VSS 177 DQ23 71 A3 215 VDD 108 DQ40 252 VSS
34 DQ18 178 VSS 72 A1 216 A2 109 VSS 253 DQ41
35 VSS 179 DQ19 73 VDD 217 VDD 110
36 DQ28 180 VSS 74 CK0_t 218 CK1_t 111
37 VSS 181 DQ29 75 CK0_c 219 CK1_c 112 VSS 256 DQS5_t
38 DQ24 182 VSS 76 VDD 220 VDD 113 DQ46 257 VSS
151 VSS 45 DQ26 189 VSS 82 RAS_n/A16 226 VDD 120 VSS 264 DQ49
152 DQS0_c 46 VSS 190 DQ27 83 VDD 227 RFU 121
162 VSS 56 CB2,NC 200 VSS 93 C0,CS2_n,NC 237 NC,CS3_n,C1 131 VSS 275 DQ57
163 DQS1_c 57 VSS 201 CB3,NC 94 VSS 238 SA2 132
173 VSS 67 VDD 211 A7 104 DQ34 248 VSS 142 VPP 286 VPP
174 DQS2_c 68 A8 212 VDD 105 VSS 249 DQ35 143 VPP 287 VPP
TDQS12_t,DQ
S12_t,DM3_n,
DBI3_n,NC
TDQS12_c,D
QS12_c,NC
TDQS17_t,DQ
S17_t,DM8_n,
DBI8_n,NC
TDQS17_c,D
QS17_c,NC
184 VSS KEY 115 DQ42 259 VSS
185 DQS3_c 78 EVENT_n 222 PARITY 116 VSS 260 DQ43
TDQS15_t,DQ
S15_t,DM6_n,
DBI6_n,NC
TDQS15_c,D
QS15_c,NC
195 VSS 88 VDD 232 A13 126 DQ50 270 VSS
196 DQS8_c 89 CS1_n 233 VDD 127 VSS 271 DQ51
TDQS16_t,DQ
S16_t,DM7_n,
DBI7_n,NC
TDQS16_c,D
QS16_c,NC
TDQS13_t,DQ
S13_t,DM4_n,
DBI4_n,NC
TDQS13_c,D
QS13_c,NC
TDQS14_t,DQ
S14_t,DM5_n,
DBI5_n,NC
TDQS14_c,D
QS14_c,NC
243 VSS 137 DQ58 281 VSS
244 DQS4_c 138 VSS 282 DQ59
NOTE :
1) Light colored text indicates functions
that are not applicable for UDIMM wiring. An example is the A17 for pin 234
254 VSS
255 DQS5_c
because UDIMMs defined by this specification will never have DIMM wiring for
this pin.
265 VSS
266 DQS6_c
276 VSS
277 DQS7_c
- 5 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
5. PIN DESCRIPTION
Pin Name Description Pin Name Description
1)
A0–A17
BA0, BA1 SDRAM bank select SDA
BG0, BG1 SDRAM bank group select SA0–SA2
2)
RAS_n
3)
CAS_n
4)
WE_n
CS0_n, CS1_n
CKE0, CKE1 SDRAM clock enable lines VSS Power supply return (ground)
ODT0, ODT1 SDRAM on-die termination control lines VDDSPD Serial SPD-TSE positive power supply
ACT_n SDRAM activate ALERT_n SDRAM ALERT_n
DQ0–DQ63 DIMM memory data bus VPP SDRAM Supply
CB0–CB7 DIMM ECC check bits
TDQS0_t-TDQS8_t
TDQS0_c-TDQS8_c
DQS0_t–DQS8_t
DQS0_c–DQS8_c
DM0_n–DM8_n,
DBI0_n-DBI8_n
CK0_t, CK1_t
CK0_c, CK1_c
SDRAM address bus SCL
SDRAM row address strobe PARITY SDRAM parity input
SDRAM column address strobe VDD SDRAM I/O and core power supply
SDRAM write enable 12 V
DIMM Rank Select Lines VREFCA
RESET_n
Dummy loads for mixed populations of x4
based and x8 based RDIMMs.
Not used on UDIMMs.
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/data bus inversion
(x8-based x64 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
EVENT_n SPD signals a thermal event has occurred
VTT
RFU Reserved for future use
2
I
C serial bus clock for SPD-TSE
2
C serial bus data line for SPD-TSE
I
2
C slave address select for SPD-TSE
I
Optional power Supply on socket but not
used on UDIMM
Set DRAMs to a Known State
SDRAM I/O termination supply
Rev. 1.1
NOTE :
1) Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs this connection pin is NC.
2) RAS_n is a multiplexed function with A16.
3) CAS_n is a multiplexed function with A15.
4) WE_n is a multiplexed function with A14.
[Table 3] Temperature Sensor Characteristics
Grade Range
75 < Ta < 95 - +/- 0.5 +/- 1.0
B
40 < Ta < 125 - +/- 1.0 +/- 2.0 -
-20 < Ta < 125 - +/- 2.0 +/- 3.0 -
Resolution 0.25 C /LSB -
Temperature Sensor Accuracy
Min. Typ. Max.
Units NOTE
-
C
- 6 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
6. INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol Type Function
CK_t, CK_c
CKE, (CKE1) Input
CS_n (CS1_n)
C0, C1, C2 Input
ODT (ODT1) Input
ACT_n Input
RAS_n/A16,
CAS_n/A15,
WE_n/A14
DM_n/DBI_n/
TDQS_t,
(DMU_n/ DBIU_n),
(DML_n/ DBIL_n)
BG0 - BG1 Input
BA0 - BA1 Input
A0 - A17 Input
A10 / AP Input
A12 / BC_n Input
RESET_n
DQ
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
Input
Input
Input
Input/
Output
CMOS
Input
Input/
Output
Input/
Output
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and
output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal
DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input
buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection
on systems with multiple Ranks. CS_n is considered part of the command code. CS2_n and CS3_n are not used on
UDIMMs
Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID
is considered part of the command code. Not used on UDIMMs.
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4
SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t, NU/TDQS_c
(When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT
is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be
ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into
RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14.
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered.
Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and
A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other
command defined in command truth table.
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when
DM_n is sampled LOW coincident with that input data during a Write access. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion
inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in x8 SDRAM configurations.
TDQS is not valid for UDIMMs.
Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being
applied. BG0 also determines which mode register is to be accessed during a MRS cycle. x4/x8 SDRAM
configurations have BG0 and BG1. x16 based SDRAMs only have BG0.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines which mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16,
CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code
during Mode Register Set commands. A17 is only defined for the x4 SDRAM configuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be
performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW)
or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be
performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH.
RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end
of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4
A4=High. Refer to vendor specific data sheets to determine which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c,
respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports
differential data strobe only and does not support single-ended.
Rev. 1.1
- 7 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
Symbol Type Function
TDQS_t,
TDQS_c
PAR Input
ALERT_n
TEN
NC No Connect: No on DIMM electrical connection is present.
VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ Supply DQ Ground
VDD
VSS Supply Ground
VPP Supply DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)
12 V Supply 12 V supply not used on UDIMMs.
VDDSPD Supply Power supply used to power the I2C bus on the SPD-TSE 2.5V or 3.3V.
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
Output
Output
Input
Supply Power Supply: 1.2 V +/- 0.06 V
Termination Data Strobe: TDQS_t/TDQS_c are not valid for UDIMMs.
Command and Address Parity Input: DDR4 Supports Even Parity check in DRAMs with MR setting. Once it’s
enabled via Register in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0BG1, BA0-BA1, A16-A0. LOW Command and address inputs shall have parity check performed when commands
are latched via the rising edge of CK_t and when CS_n is low.
Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there
is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in
Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM internal
recovery transaction is complete. During Connectivity Test mode this pin functions as an input. Using this signal or
not is dependent on the system.
Connectivity Test Mode Enable : Required on X16 devices and optional input on x4/x8 with densities equal
to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It
is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is
dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to
VSS
Rev. 1.1
NOTE :
1) Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.
- 8 -
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
6.1 Address Mirroring
DDR4 two rank UDIMMs will use address mirroring. DRAMs for even ranks will be placed on the front side of the module. DRAMs for odd ranks will be
placed on the back side of the module. Wiring of the address bus will be as defined in Table 4.
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are
limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to
know if the rank is mirrored or not. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or
not. See the DDR4 SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when
accessing the odd ranks.
[Table 4] DIMM Wiring Definition for Address Mirroring
Signal Name DRAM Ball Lable
Connector Even Rank Odd Rank
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A9 A9 A9
A10/AP A10/AP A10/AP
A11 A11 A13
A12/BC_n A12/BC_n A12/BC_n
A13 A13 A11
A14/WE_n A14/WE_n A14/WE_n
A15/CAS_n A15/CAS_n A15/CAS_n
A16/RAS_n A16/RAS_n A16/RAS_n
A17 A17 A17 Not valid for x8 and x16 DRAM components up to 16Gb.
BA0 BA0 BA1
BA1 BA1 BA0
BG0 BG0 BG1
BG1 BG1 BG0
BG1 is not valid for x16 DRAM components. For x16 DRAM components
signal BG0 will be wired to DRAM ball BG0 for both ranks.
BG1 is not valid for x16 DRAM components. For x16 DRAM components
signal BG0 will be wired to DRAM ball BG0 for both ranks.
Comment
- 9 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
7. FUNCTION BLOCK DIAGRAM:
7.1 8GB, 1Gx72 ECC Module (Populated as 1 rank of x8 DDR4 SDRAMs)
Rev. 1.1
CK0_t,CK0_c
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
CS0_n
ODT0
CKE0
DQS0_t
DQS0_c
DQ[7:0]
DM0_n/DBI0_n
DQS1_t
DQS1_c
DQ[15:8]
DBI1_n/DM1_n
DQS2_t
DQS2_c
DQ[23:16]
DBI2_n/DM2_n
CKE
ODT
D0
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CKE
ODT
D1
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CKE
ODT
D2
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CS_n
CS_n
CS_n
CK
ZQ
Address
CK
ZQ
Address
CK
ZQ
Address
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
VSS
VSS
VSS
CK0_t,CK0_c
CS0_n
ODT0
CKE0
DQS4_t
DQS4_c
DQ[39:32]
DBI4_n/DM4_n
DQS5_t
DQS5_c
DQ[47:40]
DBI5_n/DM5_n
DQS6_t
DQS6_c
DQ[55:48]
DBI6_n/DM6_n
CKE
ODT
D4
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CKE
ODT
D5
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CKE
ODT
D6
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CS_n
CS_n
CS_n
CK
ZQ
Address
CK
ZQ
Address
CK
ZQ
Address
VSS
VSS
VSS
ODT
D3
ODT
D8
CS_n
CS_n
CK
ZQ
Address
CK
ZQ
Address
VSS
VSS
DQS7_t
DQS7_c
DQ[63:56]
DBI7_n/DM7_n
DQS3_t
DQS3_c
DQ[31:24]
DBI3_n/DM3_n
DQS8_t
DQS8_c
DQ[71:64]
DBI8_n/DM8_n
D0
CKE
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
CKE
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
D1 D2 D3 D8 D4 D5 D6 D7
Address, Command and Control lines
NOTE :
1) Unless otherwise noted, resistor values are 15 5%.
2) ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram.
3) For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 of 2.
4) EVENT_n is used for SPD with TS. Option Resistor for it should be placed.
ODT
CS_n
Address
D7
EVENT_nEVENT_n
SA0 SA1 SA2
SA0 SA1 SA2
CK
CKE
DQS_t
DQS_c
DQ[7:0]
DBI_n/DM_n
SCL
Serial PD with Thermal sensor
V
DDSPD
V
PP
V
DD
V
TT
V
REFCA
V
SS
ZQ
VSS
SDA
Serial PD
D0 - D8
D0 - D8
D0 - D8
D0 - D8
- 10 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
7.2 16GB, 2Gx72 ECC Module (Populated as 2 ranks of x8 DDR4 SDRAMs)
A[16:0],BA[1:0],BG[1:0]
ACT_n, PARITY,
CK0_t,CK0_c
CS0_n
ODT0
CKE0
CK1_t,CK1_c
CS1_n
ODT1
CKE1
Rev. 1.1
DQS0_t
DQS0_c
DQ [7:0]
DM0_n/DBI0_n
DQS1_t
DQS1_c
DQ [15:8]
DM1_n/DBI1_n
DQS2_t
DQS2_c
DQ [23:16]
DM2_n/DBI2_n
DQS3_t
DQS3_c
DQ [31:24]
DM3_n/DBI3_n
DQS8_t
DQS8_c
CB [7:0]
DM8_n/DBI8_n
CKE
DQS_t
DQS_c
D1
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D2
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D3
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D4
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D5
DQ [7:0]
DM_n/DBI_n
ODT
ODT
ODT
ODT
ODT
CS_n
CS_n
CS_n
CS_n
CS_n
CK
CK
CK
CK
CK
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
VSS
VSS
VSS
VSS
VSS
CKE
DQS_t
DQS_c
D11
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D12
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D13
DQ [7:0]
DM_n/DBI_n
CKE
CKE
DQS_t
DQS_t
DQS_c
DQS_c
D0
D14
DQ [7:0]
DQ [7:0]
DM_n/DBI_n
DM_n/DBI_n
CKE
DQS_t
DQS_c
D15
DQ [7:0]
DM_n/DBI_n
ODT
ODT
ODT
ODT
ODT
ODT
CS_n
CS_n
CS_n
CS_n
CS_n
CS_n
CK
CK
CK
CK
CK
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
ZQ
A,BA,BG,Par
A,BA,BG,Par
ZQ
A,BA,BG,Par
VSS
DQS4_t
DQS4_c
DQ [39:32]
DM4_n/DBI4_n
VSS
DQS5_t
DQS5_c
DQ [47:40]
DM5_n/DBI5_n
VSS
DQS6_t
DQS6_c
DQ [55:48]
DM6_n/DBI6_n
VSS
VSS
DQS7_t
DQS7_c
DQ [63:56]
DM7_n/DBI7_n
VSS
CKE
DQS_t
DQS_c
D6
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D7
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D8
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
D9
DQ [7:0]
DM_n/DBI_n
CK
ZQ
ODT
ODT
ODT
ODT
CS_n
CS_n
CS_n
CS_n
CK
CK
CK
A,BA,BG,Par
A,BA,BG,Par
A,BA,BG,Par
A,BA,BG,Par
ZQ
ZQ
ZQ
VSS
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
Serial PD with Thermal sensor
CKE
ODT
D16
CKE
ODT
D17
CKE
ODT
D18
CKE
ODT
D19
CS_n
CS_n
CS_n
CS_n
CK
CK
CK
CK
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
ZQ
A,BA,BG,Par
VSS
VSS
VSS
VSS
Front
D1 D2 D3 D4 D6 D7 D8 D9
D5
Back
D11 D12 D13 D14 D16 D17 D18 D19
D15
Address, Command and Control lines
NOTE :
1) Unless otherwise noted, resistor values are 15 ± 5%.
2) ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.
SCL
EVENT_n
V
VREFCA
DDSPD
V
V
V
V
DD
EVENT_n
SA0 SA1 SA2
SA0 SA1
PP
TT
SS
SDA
SA2
Serial PD
D0-D19
D0-D19
D0-D19
D0-D19
- 11 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
8. ABSOLUTE MAXIMUM RATINGS
[Table 5] Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3
VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4
Rev. 1.1
V
NOTE :
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3) VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA
may be equal to or less than 300mV
4) VPP must be equal or greater than VDD/VDDQ at all times.
5) Overshoot area above 1.5 V is specified in 10.3.4, 10.3.5 and 10.3.6.
Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5
IN, VOUT
T
Storage Temperature -55 to +100 °C 1,2
STG
9. AC & DC OPERATING CONDITIONS
[Table 6] Recommended DC Operating Conditions
Symbol Parameter
VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3
VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3
VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3
NOTE :
1) Under all conditions V
tracks with VDD. AC parameters are measured with VDD and V
2) V
DDQ
3) DC bandwidth is limited to 20MHz.
must be less than or equal to VDD.
DDQ
Min. Typ. Max.
tied together.
DDQ
Rating
Unit NOTE
- 13 -
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
10. AC & DC INPUT MEASUREMENT LEVELS
10.1 AC & DC Logic Input Levels for Single-Ended Signals
[Table 7] Single-ended AC & DC Input Levels for Command and Address
Symbol Parameter
VIH.CA(DC75)
VIH.CA(DC65) - -
VIL.CA(DC75)
VIL.CA(DC65) - - VSS
VIH.CA(AC100)
VIH.CA(AC90) - -
VIL.CA(AC100)
VIL.CA(AC90) - - Note 2
VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 2,3
NOTE :
1) See “Overshoot and Undershoot Specifications” on section10.3.
2) The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)
3) For reference : approx. VDD/2 ± 12mV.
DC input logic high
DC input logic low
AC input logic high
AC input logic low
DDR4-1600/1866/2133/2400 DDR4-2666
Min. Max. Min. Max.
V
REFCA
VSS
V
REF
Note 2
+ 0.075
+ 0.1
VDD - -
V
+ 0.065
REFCA
-0.075
V
REFCA
Note 2 - -
- 0.1
V
REF
--
V
+ 0.09
REF
--
Unit NOTE
VDD
-0.065
V
REFCA
Note 2 1
V
- 0.09
REF
V
V
V
V
1
10.2 AC and DC Input Measurement Levels: V
The DC-tolerance limits and ac-noise limits for the reference voltages V
function of time. (V
(DC) is the linear average of V
V
REF
Furthermore V
stands for V
REF
(t) may temporarily deviate from V
REF
voltage
).
REFCA
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7.
REF
Figure 1. Illustration of V
(DC) by no more than ± 1% VDD.
REF
(DC) tolerance and V
REF
is illustrated in Figure 1. It shows a valid reference voltage V
REFCA
Tolerances.
REF
AC-noise limits
REF
(t) as a
REF
V
DD
V
SS
time
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V
" shall be understood as V
"V
REF
This clarifies, that DC-variations of V
which setup and hold is measured. System timing and voltage budgets need to account for V
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
and voltage effects due to AC-noise on V
(DC), as defined in Figure 1.
REF
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
REF
(DC) deviations from the optimum position within the
REF
up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
REF
- 14 -
REF
.
AC-noise. Timing
REF
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
.DIFF.MIN
V
IH
0.0
(CK_t - CK_c)
V
.DIFF.AC.MAX
V
IL
.DIFF.MAX
IL
half cycle
Rev. 1.1
Differential Input Voltage (CK-CK)
Figure 2. Definition of differential ac-swing and “time above ac-level” t
NOTE:
1) Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2) Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
10.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)
[Table 8] Differential AC and DC Input Levels
Symbol Parameter
V
IHdiff
V
ILdiff
V
(AC)
IHdiff
V
(AC)
ILdiff
NOTE :
1) Used to define a differential signal slew-rate.
2) for CK_t - CK_c use V
3) These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V
as well as the limitations for overshoot and undershoot.
differential input high +0.150 NOTE 3 0.135 NOTE 3 V 1
differential input low NOTE 3 -0.150 NOTE 3 -0.135 V 1
differential input high ac
2 x (VIH(AC) - V
differential input low ac NOTE 3
IH.CA/VIL.CA
(AC) of ADD/CMD and V
DDR4 -1600/1866/2133 DDR4 -2400/2666
min max min max
REFCA
)
REF
NOTE 3
2 x (VIL(AC) - V
;
2 x (VIH(AC) - V
)
REF
tDVAC
NOTE 3
IH.CA
time
DVAC
)
REF
2 x (VIL(AC) - V
(DC) max, V
unit NOTE
NOTE 3 V 2
)
V2
REF
(DC)min) for single-ended signals
IL.CA
[Table 9] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c
Slew Rate [V/ns]
> 4.0 120 -
4.0 115 -
3.0 110 -
2.0 105 -
1.8 100 -
1.6 95 -
1.4 90 -
1.2 85 -
1.0 80 -
< 1.0 80 -
tDVAC [ps] @ |V
(AC)| = 200mV
IH/Ldiff
min max
- 15 -
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC)) for ADD/CMD
signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used
for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c.
V
DD
VDD or V
/2 or V
V
SEH
DDQ
min
DDQ
V
SEH
/2
CK
max
V
SEL
V
VSS or V
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with
respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
SSQ
Figure 3. Single-ended requirement for differential signals.
SEL
time
[Table 10] Single-ended Levels for CK_t, CK_c
Symbol Parameter
V
V
NOTE :
1) For CK_t - CK_c use V
2) V
IH
3) These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V
signals as well as the limitations for overshoot and undershoot.
Single-ended high-level for CK_t, CK_c (VDD/2)+0.100 NOTE3 (VDD/2)+0.95 NOTE3 V 1, 2
SEH
Single-ended low-level for CK_t, CK_c NOTE3 (VDD/2)-0.100 NOTE3 (VDD/2)-0.95 V 1, 2
SEL
(AC)/VIL(AC) for ADD/CMD is based on V
IH.CA/VIL.CA
(AC) of ADD/CMD;
REFCA
;
DDR4-1600/1866/2133 DDR4-2400/2666
Min Max Min Max
(DC) max, V
IH.CA
Unit NOTE
(DC)min) for single-ended
IL.CA
- 16 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.3.4 Address, Command and Control Overshoot and Undershoot specifications
[Table 11] AC overshoot/undershoot specification for Address, Command and Control pins
Rev. 1.1
Parameter Symbol
Maximum peak amplitude above VAOS VAOSP 0.06 TBD V
Upper boundary of overshoot area AAOS1 VAOS VDD +0.24 TBD V 1
Maximum peak amplitude allowed for undershoot
Maximum overshoot area per 1 tCK above VAOS AAOS2 0.0083 0.0071 0.0062 0.0055 TBD V-ns
Maximum overshoot area per 1 tCK between VDD and VAOS AAOS1 0.2550 0.2185 0.1914 0.1699 TBD V-ns
Maximum undershoot area per 1 tCK below VSS AAUS 0.2644 0.2265 0.1984 0.1762 TBD V-ns
(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
NOTE :
1) The value of VAOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC
Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 5.
V
AOSP
V
AOS
V
Volts
DD
VAUS 0.30 TBD V
(V)
V
SS
V
AUS
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
A
AOS2
1 tCK
Specification
A
AOS1
A
AUS
Unit NOTE
Figure 4. Address, Command and Control Overshoot and Undershoot Definition
- 17 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.3.5 Clock Overshoot and Undershoot Specifications
[Table 12] AC overshoot/undershoot specification for Clock
Rev. 1.1
COS2
Specification
A
COS1
A
CUS
Unit NOTE
Parameter Symbol
Maximum peak amplitude above VCOS VCOSP 0.06 TBD V
Upper boundary of overshoot area ADOS1 VCOS VDD +0.24 TBD V 1
Maximum peak amplitude allowed for undershoot VCUS 0.30 TBD V
Maximum overshoot area per 1 UI above VCOS
Maximum overshoot area per 1 UI between VDD and VDOS ACOS1 0.1125 0.0964 0.0844 0.0750 TBD V-ns
Maximum undershoot area per 1 UI below VSS ACUS 0.1144 0.0980 0.0858 0.0762 TBD V-ns
NOTE :
1) The value of VCOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC
Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 5.
V
COSP
V
COS
V
Volts
DD
ACOS2 0.0038 0.0032 0.0028 0.0025 TBD V-ns
(V)
V
SS
V
CUS
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
(CK_t, CK_c)
A
1 UI
Figure 5. Clock Overshoot and Undershoot Definition
- 18 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications
[Table 13] AC overshoot/undershoot specification for Data, Strobe and Mask
Rev. 1.1
A
DUS2
Specification
A
DOS1
A
DUS1
Unit NOTE
Parameter Symbol
Maximum peak amplitude above VDOS VDOSP 0.16 0.16 0.16 0.16 TBD V
Upper boundary of overshoot area ADOS1 VDOS VDDQ + 0.24 TBD V 1
Lower boundary of undershoot area ADUS1 VDUS 0.30 0.30 0.30 0.30 TBD V 2
Maximum peak amplitude below VDUS VDUSP 0.10 0.10 0.10 0.10 TBD V
Maximum overshoot area per 1 UI above VDOS ADOS2 0.0150 0.0129 0.0113 0.0100 TBD V-ns
Maximum overshoot area per 1 UI between
VDDQ and VDOS
Maximum undershoot area per 1 UI between
VSSQ and VDUS1
Maximum undershoot area per 1 UI below VDUS ADUS2 0.0150 0.0129 0.0113 0.0100 TBD V-ns
NOTE :
1) The value of VDOS matches (VIN, VOUT) max as defined in Table 5 Absolute Maximum DC Ratings if VDDQ equals VDDQ max as defined in Table 6 Recommended DC
Operating Conditions. If VDDQ is above the recommended operating conditions, VDOS remains at (VIN, VOUT) max as defined in Table 5.
2) The value of VDUS matches (VIN, VOUT) min as defined in Table 5 Absolute Maximum DC Ratings
V
DOSP
V
DOS
V
Volts
DDQ
ADOS1 0.1050 0.0900 0.0788 0.0700 TBD V-ns
ADUS1 0.1050 0.0900 0.0788 0.0700 TBD V-ns
(V)
V
SSQ
V
DUSP
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
A
DOS2
1 UI
Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition
- 19 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.4 Slew Rate Definitions
10.4.1 Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.
[Table 14] Differential Input Slew Rate Definition
Description
Differential input slew rate for rising edge (CK_t - CK_c)
Differential input slew rate for falling edge (CK_t - CK_c)
NOTE :
1) The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Measured
from to
V
ILdiffmax
V
IHdiffmin
Delta TRdiff
V
IHdiffmin
V
ILdiffmax
[V
[V
IHdiffmin
IHdiffmin
Defined by
- V
ILdiffmax
- V
ILdiffmax
Rev. 1.1
] / DeltaTRdiff
] / DeltaTFdiff
Differential Input Voltage(i,e, CK_t - CK_c)
Figure 7. Differential Input Slew Rate Definition for CK_t, CK_c
Delta TFdiff
V
IHdiffmin
0
V
ILdiffmax
- 20 -
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.4.2 Slew Rate Definition for Single-ended Input Signals (CMD/ADD)
Delta TRsingle
V
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
ILCA(AC) Max
Rev. 1.1
Delta TFsingle
Figure 8. Single-ended Input Slew Rate definition for CMD and ADD
NOTE :
1) Single-ended input slew rate for rising edge = {VIHCA(AC)Min - VILCA(DC)Max} / Delta TR single.
2) Single-ended input slew rate for falling edge = {VIHCA(DC)Min - VILCA(AC)Max} / Delta TF single.
3) Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4) Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.
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Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals
(CK_t, CK_c) must meet the requirements in Table 15. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
VSEH
Figure 9. Vix Definition (CK)
[Table 15] Cross Point Voltage for Differential Input Signals (CK)
Symbol Parameter
- Area of VSEH, VSEL
VlX(CK)
Symbol Parameter
- Area of VSEH, VSEL
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
VSEL < VDD/2 -
145mV
-120mV
VSEL <
VDD/2 - 145 mV
-120mV
CK_c
VSEL
VSS
DDR4-1600/1866/2133
min max
VDD/2 - 145mV =<
VSEL =< VDD/2 -
100mV
-(VDD/2 - VSEL) +
25mV
min max
VDD/2 - 145 mV
=< VSEL =<
VDD/2 - 100 mV
- (VDD/2 - VSEL) +
25 mV
VDD/2 + 100mV =<
VSEH =< VDD/2 +
145mV
(VSEH - VDD/2) -
25mV
DDR4-2400
VDD/2 + 100 mV
=< VSEH =<
VDD/2 + 145 mV
(VSEH - VDD/2) -
25 mV
VDD/2 + 145mV <
VSEH
120mV
VDD/2 + 145 mV <
VSEH
120mV
Symbol Parameter
- Area of VSEH, VSEL
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
VSEL <
VDD/2 - 145 mV
-110 mV
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DDR4-2666
min max
VDD/2 - 145 mV
=< VSEL =<
VDD/2 - 100 mV
- (VDD/2 - VSEL)
+ 30 mV
VDD/2 + 100 mV
=< VSEH =<
VDD/2 + 145 mV
(VSEH - VDD/2)
- 30 mV
VDD/2 + 145 mV
< VSEH
110mV
Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.6 CMOS rail to rail Input Levels
10.6.1 CMOS rail to rail Input Levels for RESET_n
[Table 16] CMOS rail to rail Input Levels for RESET_n
Parameter Symbol Min Max Unit NOTE
AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6
DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2
DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1
AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7
Rising time TR_RESET - 1.0 us 4
RESET pulse width tPW_RESET 1.0 - us 3,5
NOTE :
1) After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset.
2) Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset
asserting RESET_n signal LOW.
3) RESET is destructive to data contents.
4) No slope reversal(ringback) requirement during its level transition from Low to High.
5) This definition is applied only “Reset Procedure at Power Stable”.
6) Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7) Undershoot might occur. It should be limited by Absolute Maximum DC Ratings.
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
tPW_RESET
TR_RESET
Figure 10. RESET_n Input Slew Rate Definition
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datasheet DDR4 SDRAMECC Unbuffered DIMM
10.7 AC and DC Logic Input Levels for DQS Signals
10.7.1 Differential signal definition
Rev. 1.1
Figure 11. Definition of differential DQS Signal AC-swing Level
10.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)
[Table 17] Differential AC and DC Input Levels for DQS
Symbol Parameter
VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 160 Note2 150 Note2 mV 1
VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 Note2 -160 Note2 -150 mV 1
NOTE :
1) Used to define a differential signal slew-rate.
2) These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended
signals.
DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666
Min Max Min Max Min Max
Unit Note
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Rev. 1.1
datasheet DDR4 SDRAMECC Unbuffered DIMM
10.7.3 Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
The Max(f(t)) or Min(f(t)) used to determine the midpoint which to reference the +/-35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all ui’s.
DQS_t
Max(f(t))
DQS_c
Single Ended Input Voltage : DQS_t and DQS_c
Figure 12. Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling
Min(f(t))
Time
+35%
+35%
+50%
+50%
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