Samsung M391A1K43BB2-CTD User Manual

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Page 1

Rev. 1.1, Apr. 2018

M391A1K43BB1 M391A1K43BB2 M391A2K43BB1

288pin ECC Unbuffered DIMM based on 8Gb B-die

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

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Page 2

datasheet DDR4 SDRAMECC Unbuffered DIMM

Revision History

Revision No. History Draft Date Remark Editor

0.5 - First SPEC release 15th Nov, 2017 Preliminary J.Y.Bae

- Separate ECC and Non ECC datasheets. J.H.Han

1.0 - Final datasheet. 13th Dec, 2017 Final J.Y.Bae

- Correct typo. J.H.Han

- Correct speed bin table numbering.

- Add DRAM Package Electrical Specifications (x4/x8) table.

1.1 - Correct typo in Key features. 26th Apr, 2018 Final C.M.Kang

- Update Single-ended AC & DC Input Levels for Command and Address table.

- Update Differential AC and DC Input Levels table.

- Update Cross point voltage for differential input signals (CK) table.

- Update Differential AC and DC Input Levels for DQS table.

- Update Differential Input Level for DQS_t, DQS_c table.

- Update Differential Input Slew Rate for DQS_t, DQS_c table.

- Update Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range; after proper ZQ calibration table.

Rev. 1.1

J.Y.Bae

- Update AC Timing table for 2666Mbps.

1. tDLLK : 854 -> 1024 [nCK].

2. tXPR_GEAR Min. : TBD -> tXPR

3. tXS_GEAR Min. : TBD -> tXS

4. tSYNC_GEAR Min. : TBD -> tMOD + 4tCK

5. tCMD_GEAR Min. : TBD -> tMOD

- Update DRAM DQs In Receive Mode table.

- Update Command, Address, Control Setup and Hold Values table.

- Command, Address, Control Input Voltage Values table.

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Page 3

datasheet DDR4 SDRAMECC Unbuffered DIMM

Table Of Contents

288pin ECC Unbuffered DIMM based on 8Gb B-die

1. DDR4 Unbuffered DIMM ORDERING INFORMATION....................................................................................................................... 5

2. KEY FEATURES ................................................................................................................................................................................. 5

3. ADDRESS CONFIGURATION ............................................................................................................................................................ 5

4. x72 DIMM Pin Configurations (Front side/Back side).......................................................................................................................... 6

5. PIN DESCRIPTION ............................................................................................................................................................................ 7

6. INPUT/OUTPUT FUNCTIONAL DESCRIPTION ................................................................................................................................ 8

6.1 Address Mirroring ...........................................................................................................................................................................10

7. FUNCTION BLOCK DIAGRAM: .......................................................................................................................................................... 11

7.1 8GB, 1Gx72 ECC Module (Populated as 1 rank of x8 DDR4 SDRAMs)........................................................................................11

7.2 16GB, 2Gx72 ECC Module (Populated as 2 ranks of x8 DDR4 SDRAMs) ....................................................................................12

8. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................................... 13

9. AC & DC OPERATING CONDITIONS ................................................................................................................................................ 13

10. AC & DC INPUT MEASUREMENT LEVELS..................................................................................................................................... 14

10.1 AC & DC Logic Input Levels for Single-Ended Signals.................................................................................................................14

10.2 AC and DC Input Measurement Levels: VREF Tolerances..........................................................................................................14

10.3 AC and DC Logic Input Levels for Differential Signals .................................................................................................................15

10.3.1. Differential Signals Definition ................................................................................................................................................15

10.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ....................................................................................................15

10.3.3. Single-ended Requirements for Differential Signals .............................................................................................................16

10.3.4. Address, Command and Control Overshoot and Undershoot specifications........................................................................17

10.3.5. Clock Overshoot and Undershoot Specifications..................................................................................................................18

10.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications......................................................................................19

10.4 Slew Rate Definitions....................................................................................................................................................................20

10.4.1. Slew Rate Definitions for Differential Input Signals (CK) ......................................................................................................20

10.4.2. Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ........................................................................................21

10.5 Differential Input Cross Point Voltage...........................................................................................................................................22

10.6 CMOS rail to rail Input Levels .......................................................................................................................................................23

10.6.1. CMOS rail to rail Input Levels for RESET_n .........................................................................................................................23

10.7 AC and DC Logic Input Levels for DQS Signals...........................................................................................................................24

10.7.1. Differential signal definition ...................................................................................................................................................24

10.7.2. Differential swing requirements for DQS (DQS_t - DQS_c)..................................................................................................24

10.7.3. Peak voltage calculation method .......................................................................................................................................... 25

10.7.4. Differential Input Cross Point Voltage ...................................................................................................................................26

10.7.5. Differential Input Slew Rate Definition ..................................................................................................................................27

11. AC AND DC OUTPUT MEASUREMENT LEVELS ........................................................................................................................... 28

11.1 Output Driver DC Electrical Characteristics..................................................................................................................................28

11.1.1. Alert_n output Drive Characteristic .......................................................................................................................................30

11.1.2. Output Driver Characteristic of Connectivity Test (CT) Mode...............................................................................................31

11.2 Single-ended AC & DC Output Levels..........................................................................................................................................32

11.3 Differential AC & DC Output Levels..............................................................................................................................................32

11.4 Single-ended Output Slew Rate ...................................................................................................................................................33

11.5 Differential Output Slew Rate .......................................................................................................................................................34

11.6 Single-ended AC & DC Output Levels of Connectivity Test Mode ...............................................................................................35

11.7 Test Load for Connectivity Test Mode Timing ..............................................................................................................................36

12. SPEED BIN ....................................................................................................................................................................................... 37

12.1 Speed Bin Table Note...................................................................................................................................................................42

13. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS ................................................................................. 43

13.1 IDD, IPP and IDDQ Measurement Conditions..............................................................................................................................43

14. IDD SPEC TABLE ............................................................................................................................................................................. 58

15. INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 61

16. ELECTRICAL CHARACTERISTICS & AC TIMING .......................................................................................................................... 62

16.1 Reference Load for AC Timing and Output Slew Rate .................................................................................................................62

16.2 tREFI.............................................................................................................................................................................................62

16.3 Clock Specification .......................................................................................................................................................................63

16.3.1. Definition for tCK(abs)...........................................................................................................................................................63

16.3.2. Definition for tCK(avg)...........................................................................................................................................................63

16.3.3. Definition for tCH(avg) and tCL(avg)....................................................................................................................................63

16.3.4. Definition for tERR(nper).......................................................................................................................................................63

17. TIMING PARAMETERS BY SPEED GRADE ................................................................................................................................... 64

17.1 Rounding Algorithms ...................................................................................................................................................................70

17.2 The DQ input receiver compliance mask for voltage and timing ..................................................................................................71

17.3 Command, Control, and Address Setup, Hold, and Derating .......................................................................................................75

17.4 DDR4 Function Matrix ..................................................................................................................................................................77

18. PHYSICAL DIMENSIONS ................................................................................................................................................................. 79

18.1 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB1 .............................................................................................................79

18.2 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB2 .............................................................................................................80

18.3 1Gx8 based 2Gx72 Module (2 Ranks) - M391A2K43BB1............................................................................................................81

Rev. 1.1

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Page 4

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

1. DDR4 Unbuffered DIMM ORDERING INFORMATION

[Table 1] Ordering Information Table

Part Number

M391A1K43BB1-CPB/RC 8GB 1Gx72 1Gx8(K4A8G085WB-BCPB/RC)*9 1 31.25mm

M391A1K43BB2-CTD 8GB 1Gx72 1Gx8(K4A8G085WB-BCTD)*9 1 31.25mm

M391A2K43BB1-CPB/RC/TD 16GB 2Gx72 1Gx8(K4A8G085WB-BC##)*18 2 31.25mm

NOTE :

1) "##" -PB/RC/TD

2) PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)

- DDR4-2666(19-19-19) is backward compatible to lower frequency.

Density Organization

Component Composition

2. KEY FEATURES

[Table 2] Speed Bins

Speed

tCK(min) 1.25 1.071 0.937 0.833 0.75 ns

CAS Latency 11 13 15 17 19 nCK

tRCD(min) 13.75 13.92 14.06 14.16 14.25 ns

tRP(min) 13.75 13.92 14.06 14.16 14.25 ns

tRAS(min) 35 34 33 32 32 ns

tRC(min) 48.75 47.92 47.06 46.16 46.25 ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

11-11-11 13-13-13 15-15-15 17-17-17 19-19-19

Number of

Rank

Height

Unit

• JEDEC standard 1.2V ± 0.06V Power Supply

•V

= 1.2V ± 0.06V

DDQ

• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin,1333MHz for 2666Mb/sec/pin

• 16 Banks (4 Bank Groups)

• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20

• Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866), 11,14 (DDR4-2133), 12,16 (DDR4-2400) and 14,18 (DDR4-

2666)

• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

85C, 3.9us at 85C < T

CASE

95C

3. ADDRESS CONFIGURATION

Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge

512Mx16(8Gb) based Module A0-A15 A0-A9 BG0 BA0-BA1 A10/AP

1Gx8(8Gb) based Module A0-A15 A0-A9 BG0-BG1 BA0-BA1 A10/AP

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

4. x72 DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 1.2V,NC 145 1.2V,NC 39 VSS 183 DQ25 77 VTT 221 VTT 114 VSS 258 DQ47

2 VSS 146 VREFCA 40

3 DQ4 147 VSS 41

4 VSS 148 DQ5 42 VSS 186 DQS3_t 79 A0 223 VDD 117 DQ52 261 VSS

5 DQ0 149 VSS 43 DQ30 187 VSS 80 VDD 224 BA1 118 VSS 262 DQ53

6 VSS 150 DQ1 44 VSS 188 DQ31 81 BA0 225 A10/AP 119 DQ48 263 VSS

TDQS9_t,DQS

9_t,DM0_n,DB

I0_n,NC

TDQS9_c,DQ

S9_c,NC

9 VSS 153 DQS0_t 47 CB4,NC 191 VSS 84 CS0_n 228 WE_n/A14 122

10 DQ6 154 VSS 48 VSS 192 CB5,NC 85 VDD 229 VDD 123 VSS 267 DQS6_t

11 VSS 155 DQ7 49 CB0,NC 193 VSS 86 CAS_n/A15 230 NC,SAVE_n 124 DQ54 268 VSS

12 DQ2 156 VSS 50 VSS 194 CB1,NC 87 ODT0 231 VDD 125 VSS 269 DQ55

13 VSS 157 DQ3 51

14 DQ12 158 VSS 52

15 VSS 159 DQ13 53 VSS 197 DQS8_t 90 VDD 234 NC,A17 128 DQ60 272 VSS

16 DQ8 160 VSS 54 CB6,NC 198 VSS 91 ODT1 235 NC,C2 129 VSS 273 DQ61

17 VSS 161 DQ9 55 VSS 199 CB7,NC 92 VDD 236 VDD 130 DQ56 274 VSS

TDQS10_t,DQ

S10_t,DM1_n,

DBI1_n,NC

TDQS10_c,DQ

S10_c,NC

20 VSS 164 DQS1_t 58 RESET_n 202 VSS 95 DQ36 239 VSS 133

21 DQ14 165 VSS 59 VDD 203 CKE1 96 VSS 240 DQ37 134 VSS 278 DQS7_t

22 VSS 166 DQ15 60 CKE0 204 VDD 97 DQ32 241 VSS 135 DQ62 279 VSS

23 DQ10 167 VSS 61 VDD 205 RFU 98 VSS 242 DQ33 136 VSS 280 DQ63

24 VSS 168 DQ11 62 ACT_n 206 VDD 99

25 DQ20 169 VSS 63 BG0 207 BG1 100

26 VSS 170 DQ21 64 VDD 208 ALERT_n 101 VSS 245 DQS4_t 139 SA0 283 VSS

27 DQ16 171 VSS 65 A12/BC_n 209 VDD 102 DQ38 246 VSS 140 SA1 284 VDDSPD

28 VSS 172 DQ17 66 A9 210 A11 103 VSS 247 DQ39 141 SCL 285 SDA

TDQS11_t,DQ

S11_t,DM2_n,

DBI2_n,NC

TDQS11_t,DQ

S11_t,NC

31 VSS 175 DQS2_t 69 A6 213 A5 106 DQ44 250 VSS 144 RFU 288 VPP

32 DQ22 176 VSS 70 VDD 214 A4 107 VSS 251 DQ45

33 VSS 177 DQ23 71 A3 215 VDD 108 DQ40 252 VSS

34 DQ18 178 VSS 72 A1 216 A2 109 VSS 253 DQ41

35 VSS 179 DQ19 73 VDD 217 VDD 110

36 DQ28 180 VSS 74 CK0_t 218 CK1_t 111

37 VSS 181 DQ29 75 CK0_c 219 CK1_c 112 VSS 256 DQS5_t

38 DQ24 182 VSS 76 VDD 220 VDD 113 DQ46 257 VSS

151 VSS 45 DQ26 189 VSS 82 RAS_n/A16 226 VDD 120 VSS 264 DQ49

152 DQS0_c 46 VSS 190 DQ27 83 VDD 227 RFU 121

162 VSS 56 CB2,NC 200 VSS 93 C0,CS2_n,NC 237 NC,CS3_n,C1 131 VSS 275 DQ57

163 DQS1_c 57 VSS 201 CB3,NC 94 VSS 238 SA2 132

173 VSS 67 VDD 211 A7 104 DQ34 248 VSS 142 VPP 286 VPP

174 DQS2_c 68 A8 212 VDD 105 VSS 249 DQ35 143 VPP 287 VPP

TDQS12_t,DQ S12_t,DM3_n,

DBI3_n,NC

TDQS12_c,D

QS12_c,NC

TDQS17_t,DQ S17_t,DM8_n,

DBI8_n,NC

TDQS17_c,D

QS17_c,NC

184 VSS KEY 115 DQ42 259 VSS

185 DQS3_c 78 EVENT_n 222 PARITY 116 VSS 260 DQ43

TDQS15_t,DQ S15_t,DM6_n,

DBI6_n,NC

TDQS15_c,D

QS15_c,NC

195 VSS 88 VDD 232 A13 126 DQ50 270 VSS

196 DQS8_c 89 CS1_n 233 VDD 127 VSS 271 DQ51

TDQS16_t,DQ S16_t,DM7_n,

DBI7_n,NC

TDQS16_c,D

QS16_c,NC

TDQS13_t,DQ S13_t,DM4_n,

DBI4_n,NC

TDQS13_c,D

QS13_c,NC

TDQS14_t,DQ S14_t,DM5_n,

DBI5_n,NC

TDQS14_c,D

QS14_c,NC

243 VSS 137 DQ58 281 VSS

244 DQS4_c 138 VSS 282 DQ59

NOTE :

1) Light colored text indicates functions that are not applicable for UDIMM wiring. An example is the A17 for pin 234

254 VSS

255 DQS5_c

because UDIMMs defined by this specification will never have DIMM wiring for this pin.

265 VSS

266 DQS6_c

276 VSS

277 DQS7_c

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datasheet DDR4 SDRAMECC Unbuffered DIMM

5. PIN DESCRIPTION

Pin Name Description Pin Name Description

A0–A17

BA0, BA1 SDRAM bank select SDA

BG0, BG1 SDRAM bank group select SA0–SA2

RAS_n

CAS_n

WE_n

CS0_n, CS1_n

CKE0, CKE1 SDRAM clock enable lines VSS Power supply return (ground)

ODT0, ODT1 SDRAM on-die termination control lines VDDSPD Serial SPD-TSE positive power supply

ACT_n SDRAM activate ALERT_n SDRAM ALERT_n

DQ0–DQ63 DIMM memory data bus VPP SDRAM Supply

CB0–CB7 DIMM ECC check bits

TDQS0_t-TDQS8_t

TDQS0_c-TDQS8_c

DQS0_t–DQS8_t

DQS0_c–DQS8_c

DM0_n–DM8_n,

DBI0_n-DBI8_n

CK0_t, CK1_t

CK0_c, CK1_c

SDRAM address bus SCL

SDRAM row address strobe PARITY SDRAM parity input

SDRAM column address strobe VDD SDRAM I/O and core power supply

SDRAM write enable 12 V

DIMM Rank Select Lines VREFCA

RESET_n

Dummy loads for mixed populations of x4 based and x8 based RDIMMs. Not used on UDIMMs.

SDRAM data strobes (positive line of differential pair)

SDRAM data strobes (negative line of differential pair)

SDRAM data masks/data bus inversion (x8-based x64 DIMMs)

SDRAM clocks (positive line of differential pair)

SDRAM clocks (negative line of differential pair)

EVENT_n SPD signals a thermal event has occurred

VTT

RFU Reserved for future use

C serial bus clock for SPD-TSE

C serial bus data line for SPD-TSE

C slave address select for SPD-TSE

Optional power Supply on socket but not used on UDIMM

Set DRAMs to a Known State

SDRAM I/O termination supply

Rev. 1.1

NOTE :

1) Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs this connection pin is NC.

2) RAS_n is a multiplexed function with A16.

3) CAS_n is a multiplexed function with A15.

4) WE_n is a multiplexed function with A14.

[Table 3] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

Temperature Sensor Accuracy

Min. Typ. Max.

Units NOTE

C

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Page 7

datasheet DDR4 SDRAMECC Unbuffered DIMM

6. INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol Type Function

CK_t, CK_c

CKE, (CKE1) Input

CS_n (CS1_n)

C0, C1, C2 Input

ODT (ODT1) Input

ACT_n Input

RAS_n/A16, CAS_n/A15,

WE_n/A14

DM_n/DBI_n/

TDQS_t,

(DMU_n/ DBIU_n),

(DML_n/ DBIL_n)

BG0 - BG1 Input

BA0 - BA1 Input

A0 - A17 Input

A10 / AP Input

A12 / BC_n Input

RESET_n

DQS_t, DQS_c,

DQSU_t, DQSU_c,

DQSL_t, DQSL_c

Input

Input/

Output

CMOS

Input

Input/

Output

Input/

Output

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code. CS2_n and CS3_n are not used on UDIMMs

Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code. Not used on UDIMMs.

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14.

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command defined in command truth table.

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a Write access. DBI_n is an input/output identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in x8 SDRAM configurations. TDQS is not valid for UDIMMs.

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. x4/x8 SDRAM configurations have BG0 and BG1. x16 based SDRAMs only have BG0.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for the x4 SDRAM configuration.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used.

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.

Rev. 1.1

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Page 8

datasheet DDR4 SDRAMECC Unbuffered DIMM

Symbol Type Function

TDQS_t,

TDQS_c

PAR Input

ALERT_n

TEN

NC No Connect: No on DIMM electrical connection is present.

VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V

VSSQ Supply DQ Ground

VDD

VSS Supply Ground

VPP Supply DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)

12 V Supply 12 V supply not used on UDIMMs.

VDDSPD Supply Power supply used to power the I2C bus on the SPD-TSE 2.5V or 3.3V.

VREFCA Supply Reference voltage for CA

ZQ Supply Reference Pin for ZQ calibration

Output

Input

Supply Power Supply: 1.2 V +/- 0.06 V

Termination Data Strobe: TDQS_t/TDQS_c are not valid for UDIMMs.

Command and Address Parity Input: DDR4 Supports Even Parity check in DRAMs with MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0BG1, BA0-BA1, A16-A0. LOW Command and address inputs shall have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is low.

Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM internal recovery transaction is complete. During Connectivity Test mode this pin functions as an input. Using this signal or not is dependent on the system.

Connectivity Test Mode Enable : Required on X16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to VSS

Rev. 1.1

NOTE :

1) Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.

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Page 9

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

6.1 Address Mirroring

DDR4 two rank UDIMMs will use address mirroring. DRAMs for even ranks will be placed on the front side of the module. DRAMs for odd ranks will be placed on the back side of the module. Wiring of the address bus will be as defined in Table 4. Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR4 SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the odd ranks.

[Table 4] DIMM Wiring Definition for Address Mirroring

Signal Name DRAM Ball Lable

Connector Even Rank Odd Rank

A0 A0 A0

A1 A1 A1

A2 A2 A2

A3 A3 A4

A4 A4 A3

A5 A5 A6

A6 A6 A5

A7 A7 A8

A8 A8 A7

A9 A9 A9

A10/AP A10/AP A10/AP

A11 A11 A13

A12/BC_n A12/BC_n A12/BC_n

A13 A13 A11

A14/WE_n A14/WE_n A14/WE_n

A15/CAS_n A15/CAS_n A15/CAS_n

A16/RAS_n A16/RAS_n A16/RAS_n

A17 A17 A17 Not valid for x8 and x16 DRAM components up to 16Gb.

BA0 BA0 BA1

BA1 BA1 BA0

BG0 BG0 BG1

BG1 BG1 BG0

BG1 is not valid for x16 DRAM components. For x16 DRAM components signal BG0 will be wired to DRAM ball BG0 for both ranks.

Comment

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datasheet DDR4 SDRAMECC Unbuffered DIMM

7. FUNCTION BLOCK DIAGRAM:

7.1 8GB, 1Gx72 ECC Module (Populated as 1 rank of x8 DDR4 SDRAMs)

Rev. 1.1

CK0_t,CK0_c

A[16:0],BA[1:0],

ACT_n,PARITY,BG[1:0]

CS0_n

ODT0 CKE0

DQS0_t

DQS0_c

DQ[7:0]

DM0_n/DBI0_n

DQS1_t

DQS1_c

DQ[15:8]

DBI1_n/DM1_n

DQS2_t

DQS2_c

DQ[23:16]

DBI2_n/DM2_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CS_n

Address

A[16:0],BA[1:0],

ACT_n,PARITY,BG[1:0]

VSS

CK0_t,CK0_c

CS0_n

ODT0 CKE0

DQS4_t

DQS4_c

DQ[39:32]

DBI4_n/DM4_n

DQS5_t

DQS5_c

DQ[47:40]

DBI5_n/DM5_n

DQS6_t

DQS6_c

DQ[55:48]

DBI6_n/DM6_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CKE

ODT

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CS_n

Address

VSS

ODT

CS_n

Address

VSS

DQS7_t

DQS7_c

DQ[63:56]

DBI7_n/DM7_n

DQS3_t

DQS3_c

DQ[31:24]

DBI3_n/DM3_n

DQS8_t

DQS8_c

DQ[71:64]

DBI8_n/DM8_n

CKE

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

CKE

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

D1 D2 D3 D8 D4 D5 D6 D7

Address, Command and Control lines

NOTE :

1) Unless otherwise noted, resistor values are 15 5%.

2) ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram.

3) For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 of 2.

4) EVENT_n is used for SPD with TS. Option Resistor for it should be placed.

ODT

CS_n

Address

EVENT_nEVENT_n

SA0 SA1 SA2

CKE

DQS_t DQS_c DQ[7:0] DBI_n/DM_n

SCL

Serial PD with Thermal sensor

DDSPD

REFCA

VSS

SDA

Serial PD

D0 - D8

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Page 11

datasheet DDR4 SDRAMECC Unbuffered DIMM

7.2 16GB, 2Gx72 ECC Module (Populated as 2 ranks of x8 DDR4 SDRAMs)

A[16:0],BA[1:0],BG[1:0]

ACT_n, PARITY,

CK0_t,CK0_c

CS0_n

ODT0 CKE0

CK1_t,CK1_c

CS1_n

ODT1 CKE1

Rev. 1.1

DQS0_t DQS0_c

DQ [7:0]

DM0_n/DBI0_n

DQS1_t DQS1_c

DQ [15:8]

DM1_n/DBI1_n

DQS2_t DQS2_c

DQ [23:16]

DM2_n/DBI2_n

DQS3_t DQS3_c

DQ [31:24]

DM3_n/DBI3_n

DQS8_t DQS8_c

CB [7:0]

DM8_n/DBI8_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

ODT

CS_n

A,BA,BG,Par

VSS

CKE

DQS_t DQS_c

D11

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

D12

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

D13

DQ [7:0] DM_n/DBI_n

CKE

DQS_t

DQS_t DQS_c

DQS_c

D14

DQ [7:0]

DQ [7:0] DM_n/DBI_n

DM_n/DBI_n

CKE

DQS_t DQS_c

D15

DQ [7:0] DM_n/DBI_n

ODT

CS_n

A,BA,BG,Par

VSS

DQS4_t DQS4_c

DQ [39:32]

DM4_n/DBI4_n

VSS

DQS5_t DQS5_c

DQ [47:40]

DM5_n/DBI5_n

VSS

DQS6_t DQS6_c

DQ [55:48]

DM6_n/DBI6_n

VSS

DQS7_t DQS7_c

DQ [63:56]

DM7_n/DBI7_n

VSS

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

CKE

DQS_t DQS_c

DQ [7:0] DM_n/DBI_n

ODT

CS_n

A,BA,BG,Par

VSS

DQS_t DQS_c DQ [7:0] DM_n/DBI_n

VSS

DQS_t DQS_c DQ [7:0] DM_n/DBI_n

VSS

DQS_t DQS_c DQ [7:0] DM_n/DBI_n

VSS

DQS_t DQS_c DQ [7:0] DM_n/DBI_n

Serial PD with Thermal sensor

CKE

ODT

D16

CKE

ODT

D17

CKE

ODT

D18

CKE

ODT

D19

CS_n

A,BA,BG,Par

VSS

Front

D1 D2 D3 D4 D6 D7 D8 D9

Back

D11 D12 D13 D14 D16 D17 D18 D19

D15

Address, Command and Control lines

NOTE :

1) Unless otherwise noted, resistor values are 15 ± 5%.

2) ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.

SCL

EVENT_n

VREFCA

DDSPD

EVENT_n

SA0 SA1 SA2

SA0 SA1

SDA

SA2

Serial PD

D0-D19

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datasheet DDR4 SDRAMECC Unbuffered DIMM

8. ABSOLUTE MAXIMUM RATINGS

[Table 5] Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3

VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3

VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4

Rev. 1.1

NOTE :

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3) VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA may be equal to or less than 300mV

4) VPP must be equal or greater than VDD/VDDQ at all times.

5) Overshoot area above 1.5 V is specified in 10.3.4, 10.3.5 and 10.3.6.

Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5

IN, VOUT

Storage Temperature -55 to +100 °C 1,2

STG

9. AC & DC OPERATING CONDITIONS

[Table 6] Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3

NOTE :

1) Under all conditions V

tracks with VDD. AC parameters are measured with VDD and V

2) V

DDQ

3) DC bandwidth is limited to 20MHz.

must be less than or equal to VDD.

DDQ

Min. Typ. Max.

tied together.

DDQ

Rating

Unit NOTE

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10. AC & DC INPUT MEASUREMENT LEVELS

10.1 AC & DC Logic Input Levels for Single-Ended Signals

[Table 7] Single-ended AC & DC Input Levels for Command and Address

Symbol Parameter

VIH.CA(DC75)

VIH.CA(DC65) - -

VIL.CA(DC75)

VIL.CA(DC65) - - VSS

VIH.CA(AC100)

VIH.CA(AC90) - -

VIL.CA(AC100)

VIL.CA(AC90) - - Note 2

VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 2,3

NOTE :

1) See “Overshoot and Undershoot Specifications” on section10.3.

2) The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3) For reference : approx. VDD/2 ± 12mV.

DC input logic high

DC input logic low

AC input logic high

AC input logic low

DDR4-1600/1866/2133/2400 DDR4-2666

Min. Max. Min. Max.

REFCA

VSS

REF

Note 2

+ 0.075

+ 0.1

VDD - -

+ 0.065

REFCA

-0.075

REFCA

Note 2 - -

- 0.1

REF

+ 0.09

REF

Unit NOTE

VDD

-0.065

REFCA

Note 2 1

- 0.09

REF

10.2 AC and DC Input Measurement Levels: V

The DC-tolerance limits and ac-noise limits for the reference voltages V

function of time. (V

(DC) is the linear average of V

REF

Furthermore V

stands for V

REF

(t) may temporarily deviate from V

REF

voltage

REFCA

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7.

REF

Figure 1. Illustration of V

(DC) by no more than ± 1% VDD.

REF

(DC) tolerance and V

REF

is illustrated in Figure 1. It shows a valid reference voltage V

REFCA

Tolerances.

REF

AC-noise limits

REF

(t) as a

REF

time

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that DC-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

and voltage effects due to AC-noise on V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

- 14 -

REF

AC-noise. Timing

REF

Page 14

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MIN

0.0

(CK_t - CK_c)

.DIFF.AC.MAX

.DIFF.MAX

half cycle

Rev. 1.1

Differential Input Voltage (CK-CK)

Figure 2. Definition of differential ac-swing and “time above ac-level” t

NOTE:

1) Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2) Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

10.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)

[Table 8] Differential AC and DC Input Levels

Symbol Parameter

IHdiff

ILdiff

(AC)

IHdiff

(AC)

ILdiff

NOTE :

1) Used to define a differential signal slew-rate.

2) for CK_t - CK_c use V

3) These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

as well as the limitations for overshoot and undershoot.

differential input high +0.150 NOTE 3 0.135 NOTE 3 V 1

differential input low NOTE 3 -0.150 NOTE 3 -0.135 V 1

differential input high ac

2 x (VIH(AC) - V

differential input low ac NOTE 3

IH.CA/VIL.CA

(AC) of ADD/CMD and V

DDR4 -1600/1866/2133 DDR4 -2400/2666

min max min max

REFCA

)

REF

NOTE 3

2 x (VIL(AC) - V

;

2 x (VIH(AC) - V

)

REF

tDVAC

NOTE 3

IH.CA

time

DVAC

)

REF

2 x (VIL(AC) - V

(DC) max, V

unit NOTE

NOTE 3 V 2

)

REF

(DC)min) for single-ended signals

IL.CA

[Table 9] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c

Slew Rate [V/ns]

> 4.0 120 -

4.0 115 -

3.0 110 -

2.0 105 -

1.8 100 -

1.6 95 -

1.4 90 -

1.2 85 -

1.0 80 -

< 1.0 80 -

tDVAC [ps] @ |V

(AC)| = 200mV

IH/Ldiff

min max

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC)) for ADD/CMD signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c.

VDD or V

/2 or V

SEH

DDQ

min

DDQ

SEH

max

SEL

VSS or V

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

SSQ

Figure 3. Single-ended requirement for differential signals.

SEL

time

[Table 10] Single-ended Levels for CK_t, CK_c

Symbol Parameter

NOTE :

1) For CK_t - CK_c use V

2) V

3) These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V

signals as well as the limitations for overshoot and undershoot.

Single-ended high-level for CK_t, CK_c (VDD/2)+0.100 NOTE3 (VDD/2)+0.95 NOTE3 V 1, 2

SEH

Single-ended low-level for CK_t, CK_c NOTE3 (VDD/2)-0.100 NOTE3 (VDD/2)-0.95 V 1, 2

SEL

(AC)/VIL(AC) for ADD/CMD is based on V

IH.CA/VIL.CA

(AC) of ADD/CMD;

REFCA

;

DDR4-1600/1866/2133 DDR4-2400/2666

Min Max Min Max

(DC) max, V

IH.CA

Unit NOTE

(DC)min) for single-ended

IL.CA

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.3.4 Address, Command and Control Overshoot and Undershoot specifications

[Table 11] AC overshoot/undershoot specification for Address, Command and Control pins

Rev. 1.1

Parameter Symbol

Maximum peak amplitude above VAOS VAOSP 0.06 TBD V

Upper boundary of overshoot area AAOS1 VAOS VDD +0.24 TBD V 1

Maximum peak amplitude allowed for undershoot

Maximum overshoot area per 1 tCK above VAOS AAOS2 0.0083 0.0071 0.0062 0.0055 TBD V-ns

Maximum overshoot area per 1 tCK between VDD and VAOS AAOS1 0.2550 0.2185 0.1914 0.1699 TBD V-ns

Maximum undershoot area per 1 tCK below VSS AAUS 0.2644 0.2265 0.1984 0.1762 TBD V-ns

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

NOTE :

1) The value of VAOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 5.

AOSP

AOS

Volts

VAUS 0.30 TBD V

(V)

AUS

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

AOS2

1 tCK

Specification

AOS1

AUS

Unit NOTE

Figure 4. Address, Command and Control Overshoot and Undershoot Definition

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.3.5 Clock Overshoot and Undershoot Specifications

[Table 12] AC overshoot/undershoot specification for Clock

Rev. 1.1

COS2

Specification

COS1

CUS

Unit NOTE

Parameter Symbol

Maximum peak amplitude above VCOS VCOSP 0.06 TBD V

Upper boundary of overshoot area ADOS1 VCOS VDD +0.24 TBD V 1

Maximum peak amplitude allowed for undershoot VCUS 0.30 TBD V

Maximum overshoot area per 1 UI above VCOS

Maximum overshoot area per 1 UI between VDD and VDOS ACOS1 0.1125 0.0964 0.0844 0.0750 TBD V-ns

Maximum undershoot area per 1 UI below VSS ACUS 0.1144 0.0980 0.0858 0.0762 TBD V-ns

NOTE :

1) The value of VCOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 5.

COSP

COS

Volts

ACOS2 0.0038 0.0032 0.0028 0.0025 TBD V-ns

(V)

CUS

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

(CK_t, CK_c)

1 UI

Figure 5. Clock Overshoot and Undershoot Definition

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications

[Table 13] AC overshoot/undershoot specification for Data, Strobe and Mask

Rev. 1.1

DUS2

Specification

DOS1

DUS1

Unit NOTE

Parameter Symbol

Maximum peak amplitude above VDOS VDOSP 0.16 0.16 0.16 0.16 TBD V

Upper boundary of overshoot area ADOS1 VDOS VDDQ + 0.24 TBD V 1

Lower boundary of undershoot area ADUS1 VDUS 0.30 0.30 0.30 0.30 TBD V 2

Maximum peak amplitude below VDUS VDUSP 0.10 0.10 0.10 0.10 TBD V

Maximum overshoot area per 1 UI above VDOS ADOS2 0.0150 0.0129 0.0113 0.0100 TBD V-ns

Maximum overshoot area per 1 UI between VDDQ and VDOS

Maximum undershoot area per 1 UI between VSSQ and VDUS1

Maximum undershoot area per 1 UI below VDUS ADUS2 0.0150 0.0129 0.0113 0.0100 TBD V-ns

NOTE :

1) The value of VDOS matches (VIN, VOUT) max as defined in Table 5 Absolute Maximum DC Ratings if VDDQ equals VDDQ max as defined in Table 6 Recommended DC

Operating Conditions. If VDDQ is above the recommended operating conditions, VDOS remains at (VIN, VOUT) max as defined in Table 5.

2) The value of VDUS matches (VIN, VOUT) min as defined in Table 5 Absolute Maximum DC Ratings

DOSP

DOS

Volts

DDQ

ADOS1 0.1050 0.0900 0.0788 0.0700 TBD V-ns

ADUS1 0.1050 0.0900 0.0788 0.0700 TBD V-ns

(V)

SSQ

DUSP

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

DOS2

1 UI

Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.4 Slew Rate Definitions

10.4.1 Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.

[Table 14] Differential Input Slew Rate Definition

Description

Differential input slew rate for rising edge (CK_t - CK_c)

Differential input slew rate for falling edge (CK_t - CK_c)

NOTE :

1) The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

Measured

from to

ILdiffmax

IHdiffmin

Delta TRdiff

IHdiffmin

ILdiffmax

IHdiffmin

Defined by

- V

ILdiffmax

- V

ILdiffmax

Rev. 1.1

] / DeltaTRdiff

] / DeltaTFdiff

Differential Input Voltage(i,e, CK_t - CK_c)

Figure 7. Differential Input Slew Rate Definition for CK_t, CK_c

Delta TFdiff

IHdiffmin

ILdiffmax

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.4.2 Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

Delta TRsingle

IHCA(AC) Min

IHCA(DC) Min

VREFCA(DC)

ILCA(DC) Max

ILCA(AC) Max

Rev. 1.1

Delta TFsingle

Figure 8. Single-ended Input Slew Rate definition for CMD and ADD

NOTE :

1) Single-ended input slew rate for rising edge = {VIHCA(AC)Min - VILCA(DC)Max} / Delta TR single.

2) Single-ended input slew rate for falling edge = {VIHCA(DC)Min - VILCA(AC)Max} / Delta TF single.

3) Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4) Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.5 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table 15. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

VDD

CK_t

Vix

VDD/2

Vix

VSEH

Figure 9. Vix Definition (CK)

[Table 15] Cross Point Voltage for Differential Input Signals (CK)

Symbol Parameter

- Area of VSEH, VSEL

VlX(CK)

Symbol Parameter

- Area of VSEH, VSEL

VlX(CK)

Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c

VSEL < VDD/2 -

145mV

-120mV

VSEL <

VDD/2 - 145 mV

-120mV

CK_c

VSEL

VSS

DDR4-1600/1866/2133

min max

VDD/2 - 145mV =<

VSEL =< VDD/2 -

100mV

-(VDD/2 - VSEL) + 25mV

min max

VDD/2 - 145 mV

=< VSEL =<

VDD/2 - 100 mV

- (VDD/2 - VSEL) + 25 mV

VDD/2 + 100mV =<

VSEH =< VDD/2 +

145mV

(VSEH - VDD/2) -

25mV

DDR4-2400

VDD/2 + 100 mV

=< VSEH =<

VDD/2 + 145 mV

(VSEH - VDD/2) -

25 mV

VDD/2 + 145mV <

VSEH

120mV

VDD/2 + 145 mV <

VSEH

120mV

Symbol Parameter

- Area of VSEH, VSEL

VlX(CK)

Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c

VSEL <

VDD/2 - 145 mV

-110 mV

- 22 -

DDR4-2666

min max

VDD/2 - 145 mV

=< VSEL =<

VDD/2 - 100 mV

- (VDD/2 - VSEL) + 30 mV

VDD/2 + 100 mV

=< VSEH =<

VDD/2 + 145 mV

(VSEH - VDD/2)

- 30 mV

VDD/2 + 145 mV

< VSEH

110mV

Page 22

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.6 CMOS rail to rail Input Levels

10.6.1 CMOS rail to rail Input Levels for RESET_n

[Table 16] CMOS rail to rail Input Levels for RESET_n

Parameter Symbol Min Max Unit NOTE

AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6

DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2

DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1

AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7

Rising time TR_RESET - 1.0 us 4

RESET pulse width tPW_RESET 1.0 - us 3,5

NOTE :

1) After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset.

2) Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset asserting RESET_n signal LOW.

3) RESET is destructive to data contents.

4) No slope reversal(ringback) requirement during its level transition from Low to High.

5) This definition is applied only “Reset Procedure at Power Stable”.

6) Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.

7) Undershoot might occur. It should be limited by Absolute Maximum DC Ratings.

0.8*VDD

0.7*VDD

0.3*VDD

0.2*VDD

tPW_RESET

TR_RESET

Figure 10. RESET_n Input Slew Rate Definition

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.7 AC and DC Logic Input Levels for DQS Signals

10.7.1 Differential signal definition

Rev. 1.1

Figure 11. Definition of differential DQS Signal AC-swing Level

10.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)

[Table 17] Differential AC and DC Input Levels for DQS

Symbol Parameter

VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 160 Note2 150 Note2 mV 1

VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 Note2 -160 Note2 -150 mV 1

NOTE :

1) Used to define a differential signal slew-rate.

2) These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended signals.

DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666

Min Max Min Max Min Max

Unit Note

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.7.3 Peak voltage calculation method

The peak voltage of Differential DQS signals are calculated in a following equation.

VIH.DIFF.Peak Voltage = Max(f(t))

VIL.DIFF.Peak Voltage = Min(f(t))

f(t) = VDQS_t - VDQS_c

The Max(f(t)) or Min(f(t)) used to determine the midpoint which to reference the +/-35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all ui’s.

DQS_t

Max(f(t))

DQS_c

Single Ended Input Voltage : DQS_t and DQS_c

Figure 12. Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling

Min(f(t))

Time

+35%

+50%

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

10.7.4 Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Table 18. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid of the DQS_t and DQS_c signals. VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals. A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within +/- 35% of the midpoint of either VIH.DIFF.Peak Voltage (DQS_t rising) or VIL.DIFF.Peak Voltage (DQS_c rising), refer to Figure 12. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is derived from its negative slope to zero slope transition (point A in Figure 13) and a ring-back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure 13) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point C in Figure 13) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in Figure 13) is not a valid horizontal tangent

Lowest horizontal tangent above VDQSmid of the transitioning signals

DQS_t

VIX_DQS,RF

VDQS_trans

VDQSmid

VIX_DQS,FR

VIX_DQS,RF

VIX_DQS,FR

DQS_c

VDQS_trans/2

Highest horizontal tanget below VDQSmid of the transitioning signals

SSQ

DQS_t,DQS_c : Single-ended Input Voltages

Figure 13. Vix Definition (DQS)

[Table 18] Cross point voltage for DQS differential input signals

Symbol Parameter

Vix_DQS_ratio

VDQSmid_to_Vcent VDQSmid offset relative to Vcent_DQ(midpoint) -

NOTE :

1) Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.

2) VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs drivers and paths are matched.

3) The maximum limit shall not exceed the smaller of VIHdiff minimum limit or 50mV.

4) VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and high-z states are not applicable conditions.

5) The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a system.

DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings

DDR4-1600/1866/2133/ DDR4-2666

Min Max Min Max

- 25 - 25 % 1, 2

min

(VIHdiff,50)

min

(VIHdiff,50)

Unit Note

mV 3, 4, 5

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datasheet DDR4 SDRAMECC Unbuffered DIMM

10.7.5 Differential Input Slew Rate Definition

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure 13 and Figure 14.

Rev. 1.1

NOTE :

1) Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.

2) Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.

[Table 19] Differential Input Slew Rate Definition for DQS_t, DQS_c

Description

Differential input slew rate for rising edge (DQS_t - DQS_c) VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff

Differential input slew rate for falling edge (DQS_t - DQS_c) VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff

[Table 20] Differential Input Level for DQS_t, DQS_c

Symbol Parameter

VIHDiff_DQS Differential Input High 136 - 130 - mV

VILDiff_DQS Differential Input Low - -136 - -130 mV

[Table 21] Differential Input Slew Rate for DQS_t, DQS_c

Symbol Parameter

Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c

Measured

From To

DDR4-1600/1866/2133 DDR4-2400/2666

Min Max Min Max

DDR4-1600/1866/2133/2400 DDR4-2666

Min Max Min Max

Defined by

Unit NOTE

SRIdiff Differential Input Slew Rate 3 18 2.5 18 V/ns

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11. AC AND DC OUTPUT MEASUREMENT LEVELS

11.1 Output Driver DC Electrical Characteristics

The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:

The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:

Rev. 1.1

RONPu =

RONPd =

VDDQ -Vout

I out

Vout

I out

under the condition that RONPd is off

under the condition that RONPu is off

Chip In Drive Mode

Output Drive

other circuity like RCV, ...

RON

Figure 15. Output driver

VDDQ

out

VSSQ

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 22] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range; after proper ZQ calibration

Mismatch DQ-DQ within byte vari-

NOTE :

1) The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity (TBD).

2) Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8 * VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.5 * VDDQ and 1.1 * VDDQ.

3) Measurement definition for mismatch between pull-up and pull-down, MMPuPd : Measure RONPu and RONPD both at 0.8*VDD separately; Ronnom is the nominal Ron value

RON

Mismatch between pull-up and

NOM

34

48

pull-down, MMPuPd

ation pull-up, MMPudd

ation pull-dn, MMPddd

Resistor Vout Min Nom Max Unit NOTE

RON34Pd

RON34Pu

RON48Pd

RON48Pu

VOLdc= 0.5*VDDQ 0.73 1 1.1 RZQ/7 1,2

VOMdc= 0.8* VDDQ 0.83 1 1.1 RZQ/7 1,2

VOHdc= 1.1* VDDQ 0.83 1 1.25 RZQ/7 1,2

VOLdc= 0.5* VDDQ 0.9 1 1.25 RZQ/7 1,2

VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/7 1,2

VOHdc= 1.1* VDDQ 0.8 1 1.1 RZQ/7 1,2

VOLdc= 0.5*VDDQ 0.73 1 1.1 RZQ/5 1,2

VOMdc= 0.8* VDDQ 0.83 1 1.1 RZQ/5 1,2

VOHdc= 1.1* VDDQ 0.83 1 1.25 RZQ/5 1,2

VOLdc= 0.5* VDDQ 0.9 1 1.25 RZQ/5 1,2

VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/5 1,2

VOHdc= 1.1* VDDQ 0.8 1 1.1 RZQ/5 1,2

VOMdc= 0.8* VDDQ -10 - 17 % 1,2,3,4

VOMdc= 0.8* VDDQ - - 10 % 1,2,4

RONPu -RONPd

MMPuPd =

4) RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c.

RONNOM

*100

RONPuMax -RONPuMin

MMPudd =

RONNOM

*100

RONPdMax -RONPdMin

MMPddd =

5) This parameter of x16 device is specified for Uper byte and Lower byte.

RONNOM

*100

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11.1.1 Alert_n output Drive Characteristic

A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:

Vout

RONPd =

DRAM

l Iout l

under the condition that RONPu is off

Alert Driver

Alert

RON

out

VSSQ

out

Rev. 1.1

Resistor Vout Min Max Unit NOTE

VOLdc= 0.1* VDDQ 0.3 1.2 34Ω 1

OMdc

OHdc

= 0.8* VDDQ

= 1.1* VDDQ

RON

NOTE:

1) VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD.

0.4 1.2 34Ω 1

0.4 1.4 34Ω 1

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11.1.2 Output Driver Characteristic of Connectivity Test (CT) Mode

Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test (CT) Mode. The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:

RON

Pu_CT

Pd_CT

DDQ-VOUT

l Iout l

OUT

l Iout l

Chip In Driver Mode

Output Driver

Pu_CT

other

circuity

RCV,...

RON

Pd_CT

Pu_CT

Pd_CT

Iout

DDQ

Vout

SSQ

Rev. 1.1

Figure 16. Output Driver

RON

NOM_CT

34

NOTE :

1) Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down is defined

Resistor Vout Max Units NOTE

RON

Pd_CT

Pu_CT

VOBdc = 0.2 x V

VOLdc = 0.5 x V

= 0.8 x V

VOM

= 1.1 x V

VOH

VOBdc = 0.2 x V

VOL

= 0.5 x V

= 0.8 x V

VOM

VOHdc = 1.1 x V

DDQ

1.9 34 1

2.0 34 1

2.2 34 1

2.5 34 1

2.2 34 1

2.0 34 1

1.9 34 1

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

11.2 Single-ended AC & DC Output Levels

[Table 23] Single-ended AC & DC Output Levels

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Units NOTE

VOH(DC)

VOH(AC)

NOTE :

1) The swing of ± 0.15 × V

load of 50

DC output high measurement level (for IV curve linearity)

(DC)

DC output mid measurement level (for IV curve linearity)

(DC)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

(AC)

AC output low measurement level (for output SR)

is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test

Ω to V

DDQ

= V

DDQ

11.3 Differential AC & DC Output Levels

[Table 24] Differential AC & DC Output Levels

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Units NOTE

(AC)

OHdiff

(AC)

OLdiff

NOTE :

1) The swing of ± 0.3 × V

Ω to V

of 50

AC differential output high measurement level (for output SR)

AC differential output low measurement level (for output SR)

is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load

DDQ

= V

at each of the differential outputs.

DDQ

1.1 x V

DDQ

0.8 x V

DDQ

0.5 x V

DDQ

(0.7 + 0.15) x V

(0.7 - 0.15) x V

+0.3 x V

DDQ

-0.3 x V

DDQ

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11.4 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V single ended signals as shown in Table 25 and Figure 17.

[Table 25] Single-ended Output Slew Rate Definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE :

1) Output slew rate is verified by design and characterization, and may not be subject to production test.

VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse

Measured

From To

(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse

OH(AC)

VTT

Defined by

OL(AC)

and V

Rev. 1.1

for

OH(AC)

OL(AC)

delta TRsedelta TFse

Figure 17. Single-ended Output Slew Rate Definition

[Table 26] Single-ended Output Slew Rate

Parameter Symbol

Single ended output slew rate SRQse 4949494949 V/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting

NOTE :

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are static (i.e. they stay at either high or low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Min Max Min Max Min Max Min Max Min Max

Units

- 33 -

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

11.5 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 27 and Figure 18.

[Table 27] Differential Output Slew Rate Definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE:

1) Output slew rate is verified by design and characterization, and may not be subject to production test.

OLdiff

OHdiff

Measured

From To

(AC) V

OHdiff

OLdiff

(AC) [V

(AC)

OHdiff

VTT

OHdiff

(AC)-V

Defined by

(AC)] / Delta TRdiff

OLdiff

(AC)] / Delta TFdiff

OLdiff

(AC)

OLdiff

delta TRdiffdelta TFdiff

Figure 18. Differential Output Slew Rate Definition

[Table 28] Differential Output Slew Rate

Parameter Symbol

Differential output slew rate SRQdiff 8 18 8 18 8 18 8 18 8 18 V/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals

For Ron = RZQ/7 setting

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Min Max Min Max Min Max Min Max Min Max

Units

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11.6 Single-ended AC & DC Output Levels of Connectivity Test Mode

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.

[Table 29] Single-ended AC & DC Output Levels of Connectivity Test Mode

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Unit Notes

OH(DC)

OM(DC)

OL(DC)

OB(DC)

OH(AC)

OL(AC)

NOTE :

1) The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V

DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V

DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V

AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1

AC output below measurement level (for output SR) VTT - (0.1 x VDDQ) V 1

VOH(AC)

1.1 x VDDQ V

Rev. 1.1

VTT

VOL(AC)

TF_output_CT

Figure 19. Output Slew Rate Definition of Connectivity Test Mode

[Table 30] Single-ended Output Slew Rate of Connectivity Test Mode

Parameter Symbol

Output signal Falling time TF_output_CT - 10 ns/V

Output signal Rising time TR_output_CT - 10 ns/V

TR_output_CT

DDR4-1600/1866/2133/2400/2666

Min Max

0.5 * VDDQ

Unit Notes

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datasheet DDR4 SDRAMECC Unbuffered DIMM

11.7 Test Load for Connectivity Test Mode Timing

The reference load for ODT timings is defined in Figure 20.

DDQ

DQ, DM DQSL_t, DQSL_c DQSU_t, DQSU_c

CT_INPUTS

Figure 20. Connectivity Test Mode Timing Reference Load

DUT

SSQ

Timing Reference Points

DQS_t, DQS_c

Rterm = 50 ohm

Rev. 1.1

0.5*VDDQ

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datasheet DDR4 SDRAMECC Unbuffered DIMM

12. SPEED BIN

[Table 31] DDR4-1600 Speed Bins and Operations

Speed Bin DDR4-1600

Unit NOTECL-nRCD-nRP 11-11-11

Parameter Symbol min max

13)

Internal read command to first data tAA

Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 35 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

Supported CL Settings (9),11,12 nCK 12,13

Supported CL Settings with read DBI (11),13,14 nCK 12

Supported CWL Settings 9,11 nCK

CL = 9

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3

CL = 11

(Optional)

tCK(AVG)

13.75

(13.50)

13.75

(13.50)

13.75

(13.50)

48.75

(48.50)

1.5

(Optional)

5),10)

5),10

18.00 ns 11

- ns 11

1.6 ns 1,2,3,4,10,13

Rev. 1.1

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datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 32] DDR4-1866 Speed Bins and Operations

Speed Bin DDR4-1866

Unit NOTECL-nRCD-nRP 13-13-13

Parameter Symbol min max

13)

Internal read command to first data tAA

Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 34 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

Supported CL Settings 9,11,12,13,14 nCK 12,13

Supported CL Settings with read DBI 11,13,14,15,16 nCK 12

Supported CWL Settings 9,10,11,12 nCK

CL = 9

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6

CL = 12 CL = 14 tCK(AVG) Reserved ns 1,2,3,4

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3

CL = 11

(Optional)

tCK(AVG)

13.92

5),11)

(13.50)

13.92

5),11)

(13.50)

13.92

5),11)

(13.50)

47.92

5),11)

(47.50)

1.5

(Optional)

5),11)

1.25 <1.5

(Optional)

18.00 ns 11

- ns 11

1.6 ns 1,2,3,4,10,13

5),11)

ns 1,2,3,4,6

Rev. 1.1

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datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 33] DDR4-2133 Speed Bins and Operations

Speed Bin DDR4-2133

Unit NOTECL-nRCD-nRP 15-15-15

Parameter Symbol min max

13)

Internal read command to first data tAA

Internal read command to first data with read DBI enabled

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 33 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

Supported CL Settings (9),(11), 12,(13),14,15,16 nCK 12,13

Supported CL Settings with read DBI (11),(13),14,(15),16,18,19 nCK

Supported CWL Settings 9,10,11,12,14 nCK

CL = 9

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,10

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7

CL = 14 CL = 17 tCK(AVG) Reserved ns 1,2,3,4

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3

CL = 11

(Optional)

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

tCK(AVG)

14.06

5),11)

(13.50)

14.06

5),11)

(13.50)

14.06

5),11)

(13.50)

47.06

5),11)

(46.50)

1.5

(Optional)

5),11)

1.25 <1.5

(Optional)

1.071 <1.25

(Optional)

5),11)

18.00 ns 11

- ns 11

1.6 ns 1,2,3,4,10,13

ns 1,2,3,4,7

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 34] DDR4-2400 Speed Bins and Operations

Speed Bin DDR4-2400

Unit NOTECL-nRCD-nRP 17-17-17

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI enabled

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

CWL = 12,16

Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 12

Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK

Supported CWL Settings 9,10,11,12,14,16 nCK

CL = 9

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,8

CL = 15 CL = 18 tCK(AVG) Reserved ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

CL = 11

(Optional)

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

tCK(AVG) Reserved ns 1,2,3,4,10

14.16

5),11)

(13.75)

14.16

5),11)

(13.75)

14.16

5),11)

(13.75)

46.16

5),11)

(45.75)

1.25 <1.5

(Optional)

1.071 <1.25

(Optional)

0.937 <1.071

(Optional)

5),11)

18.00 ns 11

- ns 11

ns 1,2,3,4,8

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 35] DDR4-2666 Speed Bins and Operations

Speed Bin DDR4-2666

Unit NOTECL-nRCD-nRP 19-19-19

Parameter Symbol min max

13)

Internal read command to first data tAA

Internal read command to first data with read DBI enabled

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

CWL = 12,16

CWL = 14.18

Supported CL Settings 10,(11),12,(13),14,(15),16,(17),18,19,20 nCK 12

Supported CL Settings with read DBI 12,(13),14,(15),17,(18),19,(20),21,22,23 nCK

Supported CWL Settings 9,10,11,12,14,16,18 nCK

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9

CL = 15 CL = 18 tCK(AVG) Reserved ns 4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,9

CL = 17 CL = 20 tCK(AVG)

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

CL = 17 CL = 20 tCK(AVG) Reserved ns 1,2,3,4

CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

14.25

5),11)

(13.75)

14.25

5),11)

(13.75)

13)

14.25

5),11)

(13.75)

46.25

5),11)

(45.75)

1.25 <1.5

(Optional)

1.071 <1.25

(Optional)

0.937 <1.071

(Optional)

0.833 <0.937

(Optional)

5),11)

18.00 ns 11

- ns 11

ns 1,2,3,4,9

1,2,3,4,9

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

12.1 Speed Bin Table Note

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133, 2400 and 2666 Speed Bin Tables are valid only when Geardown Mode is disabled.

1) The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

2) tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in Section 13.5.

3) tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071ns or

0.937ns or 0.833ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4) ‘Reserved’ settings are not allowed. User must program a different value.

5) 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.

6) Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization.

7) Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization.

8) Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization.

9) Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization.

10) DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

11) Parameters apply from tCK(avg) min to tCK(avg) max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

12) CL number in parentheses, it means that these numbers are optional.

13) DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

14) Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

13. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS

13.1 IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure 21 shows the setup and test load for IDD, IPP and IDDQ measurements.

• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 22. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

• “0” and “LOW” is defined as VIN <= VILAC(max).

• “1” and “HIGH” is defined as VIN >= VIHAC(min).

• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.

• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 36.

• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 38.

• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 39 through Table 46.

• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; Qoff = 0B (Output Buffer enabled) in MR1;

TDQS_t disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR5; Gear down mode disabled in MR3 Read/Write DBI disabled in MR5; DM disabled in MR5

• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n} := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed.

• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n} := {HIGH, HIGH, HIGH, HIGH, HIGH} ;apply invert of BG/BA changes when directed above.

- 43 -

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

RESET CK_t/CK_c

CKE CS

ACT,RAS,CAS,WE

A,BG,BA

ODT ZQ

Figure 21. Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements

NOTE :

1) DIMM level Output test load condition may be different from above.

Application specific

memory channel

environment

DDR4 SDRAM

DQS_t/DQS_c

SSQ

DDQ

DQ DM

IDDQ

Test Load

Channel

IO Power

Simulation

IDDQ

Simulation

IDDQ

Measurement

Correlation

Channel IO Power

Number

Figure 22. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.

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datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 36] Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns

Symbol

tCK 1.25 1.071 0.937 0.833 0.75 ns

CL 11 13 15 17 19 nCK

CWL 11 12 14 16 18 nCK

nRCD 11 13 15 17 19 nCK

nRC 39 45 51 56 62 nCK

nRAS 28 32 36 39 43 nCK

nRP 11 13 15 17 19 nCK

nFAW

nRRDS

nRRDL

tCCD_S 4 4 4 4 4 nCK

tCCD_L 5 5 6 6 7 nCK

tWTR_S 2 3 3 3 4 nCK

tWTR_L 6 7 8 9 10 nCK

nRFC 2Gb 128 150 171 193 214 nCK

nRFC 4Gb 208 243 278 313 347 nCK

nRFC 8Gb 280 327 374 421 467 nCK

nRFC 16Gb 440 514 587 661 734 nCK

x4 16 16 16 16 16 nCK

x8 20 22 23 26 28 nCK

x4 4 4 4 4 4 nCK

x8 4 4 4 4 4 nCK

x4 5 5 6 6 7 nCK

x8 5 5 6 6 7 nCK

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

11-11-11 13-13-13 15-15-15 17-17-17 19-19-19

Rev. 1.1

Unit

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datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 37] Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

Operating One Bank Active-Precharge Current (AL=0)

IDD0

IDD0A

IPP0

IDD1

IDD1A

IPP1

IDD2N

IDD2NA

IPP2N

IDD2NT

IDDQ2NT (Optional)

IDD2NL

IDD2NG

IDD2ND

IDD2N_par

IDD2P

IPP2P

IDD2Q

IDD3N

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 36; BL: 8 Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 38; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 38); Output Buffer and RTT: Enabled in Mode Regis-

ters2); ODT Signal: stable at 0; Pattern Details: see Table 38

Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0

Operating One Bank Active-Precharge IPP Current Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 36; BL: 8 Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling according to Table 39; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 39); Output Buffer and RTT: Enabled in Mode Regis-

; ODT Signal: stable at 0; Pattern Details: see Table 39

ters

Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1

Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1

Precharge Standby Current (AL=0)

CKE: High; External clock: On; tCK, CL: see Table 36; BL: 8 Bank Address Inputs: partially toggling according to Table 40; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Out-

put Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 40

Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N

Precharge Standby IPP Current Same condition with IDD2N

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 36; BL: 8 Bank Address Inputs: partially toggling according to Table 41; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Out-

put Buffer and RTT: Enabled in Mode Registers

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

Same definition like for IDD2N, CAL enabled

Precharge Standby Current with Gear Down mode enabled

Same definition like for IDD2N, Gear Down mode enabled

Precharge Standby Current with DLL disabled

Same definition like for IDD2N, DLL disabled

Precharge Standby Current with CA parity enabled

Same definition like for IDD2N, CA parity enabled

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 36; BL: 81); AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers

Precharge Power-Down IPP Current Same condition with IDD2P

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 36; BL: 81); AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0

Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 36; BL: 81); AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 40; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 40

; ODT Signal: toggling according to Table 41; Pattern Details: see Table 41

; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address,

3),5)

; ODT Signal: stable at 0

Rev. 1.1

; AL: 0; CS_n: High between ACT and PRE; Command,

; AL: 0; CS_n: High between ACT, RD and PRE;

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datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 37] Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

IDD3NA

IPP3N

IDD3P

IPP3P

IDD4R

IDD4RA

IDD4RB

IPP4R

IDDQ4R

(Optional)

IDDQ4RB (Optional)

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4W_par

IPP4W

IDD5B

IPP5B

IDD5F2

IPP5F2

IDD5F4

IPP5F4

Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N

Active Standby IPP Current Same condition with IDD3N

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 36; BL: 81); AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0

Active Power-Down IPP Current Same condition with IDD3P

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 36; BL: 82); AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 42; Data IO: seamless read data burst with different data between

one burst and the next one according to Table 42; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 42); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 42

Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R

Operating Burst Read Current with Read DBI Read DBI enabled3), Other conditions: see IDD4R

Operating Burst Read IPP Current Same condition with IDD4R

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 36; BL: 81); AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 43; Data IO: seamless write data burst with different data between

one burst and the next one according to Table 43; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 43); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 43

Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W

Operating Burst Write Current with Write DBI Write DBI enabled3), Other conditions: see IDD4W

Operating Burst Write Current with Write CRC Write CRC enabled3), Other conditions: see IDD4W

Operating Burst Write Current with CA Parity CA Parity enabled3), Other conditions: see IDD4W

Operating Burst Write IPP Current Same condition with IDD4W

Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: see Table 36; BL: 81); AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 45; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF

command every nRFC (see Table 45); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 45

Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B

Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2

Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4

Rev. 1.1

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Page 47

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 37] Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

Self Refresh Current: Normal Temperature Range

: 0 - 85°C; Low Power Auto Self Refresh (LP ASR) : Normal4); CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

IDD6N

IPP6N

IDD6E

IPP6E

IDD6R

IPP6R

IDD6A

IPP6A

IDD7

IPP7

IDD8

IPP8

CASE

Table 36; BL: 81); AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL

Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N

Self-Refresh Current: Extended Temperature Range

: 0 - 95°C; Low Power Auto Self Refresh (LP ASR) : Extended4); CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL: see

CASE

)

Table 36; BL: 81); AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank

Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL

Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E

Self-Refresh Current: Reduced Temperature Range

: 0 - 45°C; Low Power Auto Self Refresh (LP ASR) : Reduced4); CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

CASE

Table 36; BL: 81); AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL

Self Refresh IPP Current: Reduced Temperature Range Same condition with IDD6R

Auto Self-Refresh Current

: 0 - 95°C; Low Power Auto Self Refresh (LP ASR) : Auto4);CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

CASE

Table 36; BL: 81); AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL

Auto Self-Refresh IPP Current Same condition with IDD6A

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 36; BL: 81); AL: CL-1; CS_n: High between ACT

and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 46; Data IO: read data bursts with different data between one burst and the next one according to Table 46; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 46; Output Buffer and RTT: Enabled in Mode Registers2); ODT

Signal: stable at 0; Pattern Details: see Table 46

Operating Bank Interleave Read IPP Current Same condition with IDD7

Maximum Power Down Current TBD

Maximum Power Down IPP Current Same condition with IDD8

Rev. 1.1

NOTE:

1) Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2) Output Buffer Enable

- set MR1 [A12 = 0]: Qoff = Output buffer enabled

- set MR1 [A2:1 = 00]: Output Driver Impedance Control = RZQ/7

RTT_Nom enable

- set MR1 [A10:8 = 011]: RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01]: RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3) CAL enabled: set MR4 [A8:6 = 001]: 1600MT/s

010]: 1866MT/s, 2133MT/s 011]: 2400MT/s, 2666MT/s Gear Down mode enabled: set MR3 [A3 = 1]: 1/4 Rate DLL disabled: set MR1 [A0 = 0] CA parity enabled: set MR5 [A2:0 = 001]: 1600MT/s,1866MT/s, 2133MT/s 010]: 2400MT/s, 2666MT/s Read DBI enabled: set MR5 [A12 = 1] Write DBI enabled: set MR5 [A11 = 1]

4) Low Power Array Self Refresh (LP ASR): set MR2 [A7:6 = 00]: Normal

01]: Reduced Temperature range 10]: Extended Temperature range 11]: Auto Self Refresh

5) IDD2NG should be measured after sync pules (NOP) input.

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Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 38] IDD0, IDD0A and IPP0 Measurement-Loop Pattern

CKE

CK_t /CK_c

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

0 ACT 000000000000000 -

1,2 D, D 100000000000000 -

3,4 D_#, D_# 1 1 1 1 1 0 0

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 0 1 0 1 0 0 000000000 -

... repeat pattern 1...4 until nRC - 1, truncate if necessary

1 1*nRC

2 2*nRC

3 3*nRC

4 4*nRC

5 5*nRC

6 6*nRC

toggling

Static High

7 7*nRC

8 8*nRC

9 9*nRC

10 10*nRC

11 11*nRC

12 12*nRC

13 13*nRC

14 14*nRC

15 15*nRC

NOTE :

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device

3) C[2:0] are used only for 3DS device

4) DQ signals are VDDQ.

repeat Sub-Loop 0, use BG[1:0]

ODT

WE_n/ A14

CAS_n/ A15

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

C[2:0]

A[9:7]

BA[1:0]

BG[1:0]

A12/BC_n

30007F0 -

A[17,13,11]

A[10]/AP

A[6:3]

A[2:0]

For x4 and

Data

x8 only

- 49 -

Page 49

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BG[1:0]

BA[1:0]

[Table 39] IDD1, IDD1A and IPP1 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

CS_n

0 ACT 0000000000000 0 0 -

1, 2 D, D 1000000000000 0 0 -

3, 4 D#, D# 11111 00

30007 F0 -

... repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary

nRCD -AL RD 0110100000000 0 0

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 01010 000000000 0 -

... repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC + 0 ACT 0001 100110000 0 0 -

1*nRC + 1, 2 D, D 100000000000 0 00 -

1*nRC + 3, 4 D#, D# 1111100

30007 F0 -

... repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary

1*nRC + nRCD - AL RD 0110100110000 00

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

toggling

Static High

NOTE :

1) DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

1*nRC + nRAS PRE 0101001100000 0 0 -

... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary

2 2*nRC

3 3*nRC

4 4*nRC

5 5*nRC

6 6*nRC

8 7*nRC

9 9*nRC

10 10*nRC

11 11*nRC

12 12*nRC

13 13*nRC

14 14*nRC

15 15*nRC

16 16*nRC

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

A12/BC_n

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

A[2:0]

Data

D0=00, D1=FF

D2=FF, D3=00 D4=FF, D5=00

D6=00, D7=FF

D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF

D6=FF, D7=00

For x4 and x8 only

- 50 -

Page 50

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 40] IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

0 D, D 1000000000000000

1 D, D 1000000000000000

2 D#, D# 1111100

3 D#, D# 1111100

1 4-7

2 8-11

3 12-15

4 16-19

5 20-23

6 24-27

toggling

7 28-31

Static High

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) DQ signals are VDDQ.

repeat Sub-Loop 0, use BG[1:0]

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

) = 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

3 0007F00

A[2:0]

Data

- 51 -

Page 51

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 41] IDD2NT and IDDQ2NT Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

CS_n

0 D, D 1000 00000000000-

1 D, D 1000 00000000000-

2 D#, D# 1111 100

3 D#, D# 1111 100

1 4-7

2 8-11

3 12-15

4 16-19

5 20-23

6 24-27

toggling

7 28-31

Static High

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) DQ signals are VDDQ.

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2) = 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2) = 2, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2) = 3, BA[1:0] = 0 instead

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

3 0007F0-

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

Data

A[2:0]

For x4 and x8

only

- 52 -

Page 52

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 42] IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern

CKE

CK_t, CK_c

Cycle

Sub-Loop

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

0 RD 011010000000000

1 D 100000000000000-

2,3 D#, D# 1 1 1 1 1 0 0

4 RD 0110100110007F0

5 D 100000000000000-

6,7 D#, D# 1 1 1 1 1 0 0

2 8-11

3 12-15

4 16-19

toggling

5 20-23

Static High

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1) DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) Burst Sequence driven on each DQ signal by Read Command.

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]2) = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

Data

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

A[2:0]

D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

3 0007F0-

D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

3 0007F0-

For x4 and x8 only

- 53 -

Page 53

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 43] IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern

CKE

CK_t, CK_c

Cycle

Sub-Loop

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BG[1:0]

0 WR 011001000000000

1 D 100001000000000-

2,3 D#, D# 1111110

4 WR 0110010110007F0

5 D 100001000000000-

6,7 D#, D# 1111110

2 8-11

3 12-15

4 16-19

toggling

5 20-23

Static High

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1) DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

= 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]2) = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

Data

BA[1:0]

A12/BC_n

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

A[2:0]

D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

3 000 7F0-

D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

3 000 7F0-

For x4 and x8 only

- 54 -

Page 54

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 44] IDD4WC Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

0 WR 011001000000000

1,2 D, D 100001000000000-

3,4 D#, D# 1111110

5 WR 0110010110007F0

6,7 D, D 100001000000000-

8,9 D#, D# 1111110

2 10-14

3 15-19

toggling

4 20-24

Static High

5 25-29

6 30-34

7 35-39

8 40-44

9 45-49

10 50-54

11 55-59

12 60-64

13 65-69

14 70-74

15 75-79

NOTE :

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2) = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2) = 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2) = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BA[1:0]

BG[1:0]

3 0007F0-

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

A12/BC_n

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

A[2:0]

D0=00, D1=FF

D2=FF, D3=00 D4=FF, D5=00

D6=00, D7=FF

D8=CRC

D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF

D6=FF, D7=00

D8=CRC

For x4 and x8 only

Data

- 55 -

Page 55

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 45] IDD5B Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

00 REF 100000000000000-

1 D 100000000000000-

2 D 100000000000000-

3 D#, D# 1111100

4 D#, D# 1111100

toggling

Static High

4-7

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

repeat pattern 1...4, use BG[1:0]2) = 1, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]

repeat pattern 1...4, use BG[1:0]2) = 3, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]

2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary

NOTE :

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) DQ signals are VDDQ.

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

ODT

WE_n/A14

C[2:0]

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

3 0007F0-

A[17,13,11]

A[10]/AP

A[2:0]

For x4 and x8 only

Data

- 56 -

Page 56

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 46] IDD7 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

0 ACT 000000000000000 -

1 RDA 011010 00001000

2 D 100000000000000-

3 D# 1111100

... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

nRRD ACT 000000011000000 -

nRRD + 1 RDA 011010 11001000

... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary

2 2*nRRD

3 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2) = 0, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

= 1, BA[1:0] = 3 instead

ODT

WE_n/A14

C[2:0]

Data

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

A[10]/AP

A[2:0]

D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

3 0007F0-

D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

= 0, BA[1:0] = 1 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

toggling

Static High

5nFAW

6 nFAW + nRRD

7 nFAW + 2*nRRD

8 nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2) = 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

9 nFAW + 4*nRRD repeat Sub-Loop 4

10 2*nFAW

11 2*nFAW + nRRD

12 2*nFAW + 2*nRRD

13 2*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2) = 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

14 2*nFAW + 4*nRRD repeat Sub-Loop 4

15 3*nFAW

16 3*nFAW + nRRD

17 3*nFAW + 2*nRRD

18 3*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2) = 2, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 3, BA[1:0] = 0 instead

19 3*nFAW + 4*nRRD repeat Sub-Loop 4

20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary

NOTE:

1) DQS_t, DQS_c are VDDQ.

2) BG1 is don’t care for x16 device.

3) C[2:0] are used only for 3DS device.

4) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

For x4 and x8 only

- 57 -

Page 57

datasheet DDR4 SDRAMECC Unbuffered DIMM

14. IDD SPEC TABLE

IDD and IPP values are for typical operating range of voltage and temperature unless otherwise noted.

Rev. 1.1

[ Table 47 ] IDD and I

Specification for M391A1K43BB1 and M391A1K43BB2

DDQ

M391A1K43BB1:

8GB(1Gx72) Module

DDR4-2133 DDR4-2400 DDR4-2666

Symbol

15-15-15 17-17-17 19-19-19

VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V

IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max.

DD0

DD0A

DD1

DD1A

DD2N

DD2NA

DD2NT

DD2NL

DD2NG

DD2ND

DD2N_par

DD2P

DD2Q

DD3N

DD3NA

DD3P

DD4R

DD4RA

DD4RB

DD4W

DD4WA

DD4WB

DD4WC

DD4W_par

DD5B

DD5F2

DD5F4

DD6N

DD6E

DD6R

DD6A

DD7

DD8

NOTE :

1) DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 49.

2) IDD current measure method and detail patterns are described on DDR4 component datasheet.

3) VDD and VDDQ are merged on module PCB (IDDQ values are not considered by Qoff condition)

4) DIMM IDD Values are calculated based on the component IDD spec and Register power.

279 36 279 36

288 36 306 36

396 36 405 36

423 36 432 36

198 27 207 27

225 27 234 27

135 27 153 27

198 27 207 27

180 27 189 27

207 27 216 27

144 27 144 27

180 27 189 27

324 27 324 27

342 27 342 27

189 27 198 27

909 27 963 27

945 27 999 27

918 27 981 27

756 27 801 27

792 27 846 27

756 27 810 27

666 27 747 27

828 27 891 27

1791 162 1791 162

1242 135 1251 135

1044 126 1053 126

207 36 207 36

306 45 306 45

144 32 144 32

198 36 198 36

1278 72 1287 77

99 27 99 27

M391A1K43BB2:

8GB(1Gx72) Module

288 36

315 36

405 36

459 36

207 27

234 27

153 27

207 27

189 27

216 27

144 27

189 27

324 27

342 27

198 27

1116 27

1170 27

1125 27

909 27

954 27

918 27

846 27

1008 27

1944 162

1350 135

1134 126

216 36

324 54

144 36

198 36

1395 81

99 27

Unit NOTE

- 58 -

Page 58

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[ Table 48 ] IDD and I

Specification for M391A2K43BB1

DDQ

M391A2K43BB1:

16GB(2Gx72) Module

DDR4-2133 DDR4-2400 DDR4-2666

Symbol

15-15-15 17-17-17 19-19-19

VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V

IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max.

DD0

DD0A

DD1

DD1A

DD2N

DD2NA

DD2NT

DD2NL

DD2NG

DD2ND

DD2N_par

DD2P

DD2Q

DD3N

DD3NA

DD3P

DD4R

DD4RA

DD4RB

DD4W

DD4WA

DD4WB

DD4WC

DD4W_par

DD5B

DD5F2

DD5F4

DD6N

DD6E

DD6R

DD6A

DD7

DD8

NOTE :

1) DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 49.

2) IDD current measure method and detail patterns are described on DDR4 component datasheet.

3) VDD and VDDQ are merged on module PCB (IDDQ values are not considered by Qoff condition)

4) DIMM IDD Values are calculated based on the component IDD spec and Register power.

477 63 486 63

486 63 513 63

594 63 612 63

621 63 639 63

396 54 414 54

450 54 468 54

270 54 306 54

396 54 414 54

360 54 378 54

414 54 432 54

288 54 288 54

360 54 378 54

648 54 648 54

684 54 684 54

378 54 396 54

1107 54 1170 54

1143 54 1206 54

1116 54 1188 54

954 54 1008 54

990 54 1053 54

954 54 1017 54

864 54 954 54

1026 54 1098 54

1989 189 1998 189

1440 162 1458 162

1242 153 1260 153

414 72 414 72

612 90 612 90

288 63 288 63

396 72 396 72

1476 99 1494 104

198 54 198 54

495 63

522 63

612 63

666 63

414 54

468 54

306 54

414 54

378 54

432 54

288 54

378 54

648 54

684 54

396 54

1323 54

1377 54

1332 54

1116 54

1161 54

1125 54

1053 54

1215 54

2151 189

1557 162

1341 153

432 72

648 108

288 72

396 72

1602 108

198 54

Unit NOTE

- 59 -

Page 59

[ Table 49 ] DIMM Rank Status

SEC DIMM Operating Rank The other Rank

DD0

DD1

DD2P

DD2N

DD2Q

DD3P

DD3N

DD4R

DD4W

DD5B

DD6

DD7

DD8

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

DD0

DD1

DD2P

DD2N

DD2Q

DD3P

DD3N

DD4R

DD4W

DD5B

DD6

DD7

DD8

DD2N

DD2P

DD2N

DD2Q

DD3P

DD3N

DD2N

DD6

DD2N

DD8

- 60 -

Page 60

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

15. INPUT/OUTPUT CAPACITANCE

[Table 50] Silicon Pad I/O Capacitance

Symbol Parameter

CIO

DIO

DDQS

CCK

DCK

DI_ CTRL

DI_ ADD_CMD

ALERT

TEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13

NOTE :

1) This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd.

2) DQ, DM_n, DQS_T, DQS_c, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS

3) This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4) Absolute value CK_T-CK_C

5) Absolute value of CIO(DQS_T)-CIO (DQS_c)

6) CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.

7) CDI CTRL applies to ODT, CS_n and CKE

8) CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))

9) CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.

10) CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))

11) CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_c))

12) Maximum external load capacitance on ZQ pin: tbd pF.

13) TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case C specific information.

Input/output capacitance 0.55 1.4 0.55 1.15 pF 1,2,3

Input/output capacitance delta -0.1 0.1 -0.1 0.1 pF 1,2,3,11

Input/output capacitance delta DQS_t and DQS_c

Input capacitance, CK_t and CK_c 0.2 0.8 0.2 0.7 pF 1,3

Input capacitance delta CK_t and CK_c - 0.05 - 0.05 pF 1,3,4

Input capacitance (CTRL, ADD, CMD pins only)

Input capacitance delta (All CTRL pins only) -0.1 0.1 -0.1 0.1 pF 1,3,7,8

Input capacitance delta (All ADD/CMD pins only)

Input/output capacitance of ALERT 0.5 1.5 0.5 1.5 pF 1,3

Input/output capacitance of ZQ - 2.3 - 2.3 pF 1,3,12

DDR4-1600/1866/2133 DDR4-2400/2666

min max min max

- 0.05 - 0.05 pF 1,2,3,5

0.2 0.8 0.2 0.7 pF 1,3,6

-0.1 0.1 -0.1 0.1 pF 1,2,9,10

TEN might not be valid and system shall verify TEN signal with Vendor

Unit NOTE

- 61 -

Page 61

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

16. ELECTRICAL CHARACTERISTICS & AC TIMING

16.1 Reference Load for AC Timing and Output Slew Rate

Figure 23 represents the effective reference load of 50 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.

Ron nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC timing parameter values of the device.

The maximum DC High level of Output signal = 1.0 * VDDQ,

The minimum DC Low level of Output signal = {34 /(34 + 50)} *VDDQ = 0.4* VDDQ

The nominal reference level of an Output signal can be approximated by the following:

The center of maximum DC High and minimum DC Low = {(1 + 0.4) / 2} * VDDQ = 0.7 * VDDQ

The actual reference level of Output signal might vary with driver Ron and reference load tolerances. Thus, the actual reference level or midpoint of an output signal is at the widest part of the output signal’s eye. Prior to measuring AC parameters, the reference level of the verification tool should be set to an appropriate level.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

VDDQ

CK_t, CK_c

Timing Reference Point

Figure 23. Reference Load for AC Timing and Output Slew Rate

DUT

DQ DQS_t

DQS_c

Timing Reference Point

50 Ohm

VTT = VDDQ

16.2 tREFI

Average periodic Refresh interval (tREFI) of DDR4 SDRAM is defined as shown in the table.

[Table 51] tREFI by device density

Parameter Symbol 2Gb 4Gb 8Gb 16Gb Units NOTE

All Bank Refresh to active/refresh cmd time tRFC 160 260 350 550 ns

0CT

Average periodic refresh interval tREFI

NOTE :

1) Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material.

2) Supported only for Industrial Temperature.

-40CT

85CT

CASE

 85C

 95C

7.8 7.8 7.8 7.8 s

7.8 7.8 7.8 7.8 s 2

3.9 3.9 3.9 3.9

s 1

- 62 -

Page 62

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

16.3 Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR4 SDRAM device.

16.3.1 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject t o production test.

16.3.2 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge.

tCK avg tCK absj

 





j 1=

N=

N 200=

16.3.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.

tCH avg tCHj

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.

tCL avg tCLj







j 1=

 





j 1=



N tCK avg=

NtCKavg=

N 200=

16.3.4 Definition for tERR(nper)

tERR is defined as the cumulative error across n consecutive cycles of n x tCK(avg). tERR is not subject to production test.

- 63 -

Page 63

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

17. TIMING PARAMETERS BY SPEED GRADE

[Table 52] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period tCK(avg) 1.25 <1.5 1.071 <1.25 0.937 <1.071 0.833 <0.937 0.750 <0.833 ns 35,36

Average high pulse width tCH(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg)

Average low pulse width tCL(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg)

Absolute Clock Period tCK(abs)

Absolute clock HIGH pulse width tCH(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 23

Absolute clock LOW pulse width tCL(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 24

Clock Period Jitter- total JIT(per)_tot -63 63 -54 54 -47 47 -42 42 -38 38 ps 23

Clock Period Jitter- deterministic JIT(per)_dj -31 31 -27 27 -23 23 -21 21 -19 19 ps 26

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter tJIT(cc) - 125 - 107 - 94 - 83 - 75 ps

Cycle to Cycle Period Jitter during DLL locking period

Duty Cycle Jitter tJIT(duty) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ps

Cumulative error across 2 cycles tERR(2per) -92 92 -79 79 -69 69 -61 61 -55 55 ps

Cumulative error across 3 cycles tERR(3per) -109 109 -94 94 -82 82 -73 73 -66 66 ps

Cumulative error across 4 cycles tERR(4per) -121 121 -104 104 -91 91 -81 81 -73 73 ps

Cumulative error across 5 cycles tERR(5per) -131 131 -112 112 -98 98 -87 87 -78 78 ps

Cumulative error across 6 cycles tERR(6per) -139 139 -119 119 -104 104 -92 92 -83 83 ps

Cumulative error across 7 cycles tERR(7per) -145 145 -124 124 -109 109 -97 97 -87 87 ps

Cumulative error across 8 cycles tERR(8per) -151 151 -129 129 -113 113 -101 101 -91 91 ps

Cumulative error across 9 cycles tERR(9per) -156 156 -134 134 -117 117 -104 104 -94 94 ps

Cumulative error across 10 cycles tERR(10per) -160 160 -137 137 -120 120 -107 107 -96 96 ps

Cumulative error across 11 cycles tERR(11per) -164 164 -141 141 -123 123 -110 110 -99 99 ps

Cumulative error across 12 cycles tERR(12per) -168 168 -144 144 -126 126 -112 112 -101 101 ps

Cumulative error across 13 cycles tERR(13per) -172 172 -147 147 -129 129 -114 114 -103 103 ps

Cumulative error across 14 cycles tERR(14per) -175 175 -150 150 -131 131 -116 116 -104 104 ps

Cumulative error across 15 cycles tERR(15per) -178 178 -152 152 -133 133 -118 118 -106 106 ps

Cumulative error across 16 cycles tERR(16per) -180 189 -155 155 -135 135 -120 120 -108 108 ps

Cumulative error across 17 cycles tERR(17per) -183 183 -157 157 -137 137 -122 122 -110 110 ps

Cumulative error across 18 cycles tERR(18per) -185 185 -159 159 -139 139 -124 124 -112 112 ps

Cumulative error across n = 13, 14 . . . 49, 50 cycles

Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels

Command and Address setup time to CK_t, CK_c referenced to Vref levels

Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels

Command and Address hold time to CK_t, CK_c referenced to Vref levels

Control and Address Input pulse width for each input

Command and Address Timing

CAS_n to CAS_n command delay for same bank group

CAS_n to CAS_n command delay for different bank group

ACTIVATE to ACTIVATE Command delay

to different bank group for 2KB page size

ACTIVATE to ACTIVATE Command delay

to different bank group for 2KB page size

ACTIVATE to ACTIVATE Command delay

to different bank group for 1/2KB page size

ACTIVATE to ACTIVATE Command delay

to same bank group for 2KB page size

ACTIVATE to ACTIVATE Command delay

to same bank group for 1KB page size

tCK (DLL_OFF) 8 20 8 20 8 20 8 20 8 20 ns

MIN : tCK(avg)min + tJIT(per)min_tot

MAX : tCK(avg)max + tJIT(per)max_tot

tJIT(per, lck) -50 50 -43 43 -38 38 -33 33 -30 30 ps

tJIT(cc, lck) - 100 - 86 - 75 - 67 - 60 ps

tERR(nper)

tIS(base) 115 - 100 - 80 - 62 - 55 - ps

tIS(Vref) 215 - 200 - 180 - 162 - 145 - ps

tIH(base) 140 - 125 - 105 - 87 - 80 - ps

tIH(Vref) 215 - 200 - 180 - 162 - 145 - ps

tIPW 600 - 525 - 460 - 410 - 385 - ps

tCCD_L

tCCD_S 4 - 4 - 4 - 4 - 4 - nCK 34

tRRD_S(2K)

tRRD_S(1K)

tRRD_S(1/2K)

tRRD_L(2K)

tRRD_L(1K)

max(5 nCK,

6.250 ns)

Max(4nCK,6

ns)

Max(4nCK,5

ns)

Max(4nCK,5

ns)

Max(4nCK,7

.5ns)

Max(4nCK,6

ns)

MIN : tERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min)

MAX : tERR(nper)max = ((1 + 0.68ln(n)) *

max(5 nCK,

5.355 ns)

Max(4nCK,5

.3ns)

Max(4nCK,4

.2ns)

Max(4nCK,4

.2ns)

Max(4nCK,6

.4ns)

Max(4nCK,5

.3ns)

max(5 nCK,

5.355 ns)

Max(4nCK,5

.3ns)

Max(4nCK,3

.7ns)

Max(4nCK,3

.7ns)

Max(4nCK,6

.4ns)

Max(4nCK,5

.3ns)

JIT(per)_total max)

max(5 nCK,

Max(4nCK,5

Max(4nCK,3

Max(4nCK,6

Max(4nCK,4

5 ns)

.3ns)

.4ns)

.9ns)

max(5 nCK,

5 ns)

Max(4nCK,5

.3ns)

Max(4nCK,3

ns)

Max(4nCK,3

ns)

Max(4nCK,6

.4ns)

Max(4nCK,4

.9ns)

Units NOTE

tCK(avg)

- nCK 34

- 64 -

Page 64

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 52] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

ACTIVATE to ACTIVATE Command delay

to same bank group for 1/2KB page size

Four activate window for 2KB page size tFAW_2K

Four activate window for 1KB page size tFAW_1K

Four activate window for 1/2KB page size tFAW_1/2K

Delay from start of internal write transaction to internal read command for different bank group

Delay from start of internal write transaction to internal read command for same bank group

Internal READ Command to PRECHARGE Command delay

WRITE recovery time tWR 15 - 15 - 15 - 15 - 15 - ns 1

Write recovery time when CRC and DM are enabled

Delay from start of internal write transaction to internal read command for different bank group with both CRC and DM enabled

Delay from start of internal write transaction to internal read command for same bank group with both CRC and DM enabled

DLL locking time tDLLK 597 - 597 - 768 - 768 - 1024 - nCK

Mode Register Set command cycle time tMRD 8 - 8 - 8 - 8 - 8 - nCK

Mode Register Set command update delay

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - 1 - nCK 33

Multi Purpose Register Write Recovery Time

Auto precharge write recovery + precharge time

DQ0 or DQL0 driven to 0 set-up time to first DQS rising edge

DQ0 or DQL0 driven to 0 hold time from last DQS falling edge

CS_n to Command Address Latency

CS_n to Command Address Latency tCAL

Mode Register Set command cycle time in CAL mode

Mode Register Set update delay in CAL mode

DRAM Data Timing

DQS_t, DQS_c to DQ skew, per group, per access

DQ output hold time per group, per access from DQS_t, DQS_c

Data Valid Window per device, per UI: (tQH - tDQSQ) of each UI on a given DRAM

Data Valid Window, per pin, per UI: (tQH tDQSQ) each UI on a pin of a given DRAM

DQ low impedance time from CK_t, CK_c tLZ(DQ) -450 225 -390 195 -360 180 -330 175 -310 170 ps 39

DQ high impedance time from CK_t, CK_c tHZ(DQ) - 225 - 195 - 180 - 175 - 170 ps 39

Data Strobe Timing

DQS_t, DQS_c differential READ Pre-amble (1 clock preamble)

DQS_t, DQS_c differential READ Preamble (2 clock preamble)

DQS_t, DQS_c differential READ Postamble

DQS_t, DQS_c differential output high time

DQS_t, DQS_c differential output low time tQSL 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 20

tRRD_L(1/2K)

tWTR_S

tWTR_L

tWR_CRC _DM

tWTR_S_C

RC_DM

tWTR_L_C

RC_DM

tWR_MPR

tDAL(min) Programmed WR + roundup (tRP / tCK(avg)) nCK

tPDA_S 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 45,47

tPDA_H 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 46,47

tMRD_tCAL tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - nCK

tMOD_tCAL tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - nCK

tRPRE2 NA NA NA NA NA NA 1.8 NOTE 44 1.8 NOTE 44 tCK 41

Max(4nCK,6

ns)

Max(28nCK,

35ns)

Max(20nCK,

25ns)

Max(16nCK,

20ns)

max(2nCK,2

.5ns)

max(4nCK,7

.5ns)

max(4nCK,7

tRTP

tMOD

tDQSQ - 0.16 - 0.16 - 0.16 - 0.17 - 0.18 tCK(avg)/2

tQH 0.76 - 0.76 - 0.76 - 0.74 - 0.74 - tCK(avg)/2

tDVWd 0.63 - 0.63 - 0.64 - 0.64 - TBD - UI

tDVWp 0.66 - 0.66 - 0.69 - 0.72 - 0.72 - UI

tRPRE 0.9 NOTE44 0.9 NOTE44 0.9 NOTE44 0.9 NOTE 44 0.9 NOTE 44 tCK 40

tRPST 0.33 NOTE 45 0.33 NOTE 45 0.33 NOTE 45 0.33 NOTE 45 0.33 NOTE 45 tCK

tQSH 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 21

.5ns)

tWR+max

(4nCK,3.75ns)-

tWTR_S+ma

(4nCK,3.75n

tWTR_L+ma

(4nCK,3.75n

max(24nCK,

15ns)

tMOD (min)

+ AL + PL

max(3 nCK,

3.748 ns)

Max(4nCK,5

Max(28nCK,

Max(20nCK,

Max(16nCK,

max(2nCK,2

max(4nCK,7

(5nCK,3.75ns)-

tWTR_S+ma

(5nCK,3.75n

tWTR_L+ma

(5nCK,3.75n

max(24nCK,

tMOD (min)

max(3 nCK,

.3ns)

30ns)

23ns)

17ns)

.5ns)

tWR+max

15ns)

+ AL + PL

3.748 ns)

Max(4nCK,5

Max(28nCK,

Max(20nCK,

Max(16nCK,

max(2nCK,2

max(4nCK,7

(5nCK,3.75ns)-

tWTR_S+ma

(5nCK,3.75n

tWTR_L+ma

(5nCK,3.75n

max(24nCK,

tMOD (min)

max(3 nCK,

.3ns)

30ns)

21ns)

15ns)

.5ns)

tWR+max

15ns)

+ AL + PL

3.748 ns)

Max(4nCK,4

Max(28nCK,

Max(20nCK,

Max(16nCK,

Max (2nCK,

(4nCK,7.5ns)-

(5nCK,3.75ns)-

tWTR_S+ma

(5nCK,3.75n

tWTR_L+ma

(5nCK,3.75n

max(24nCK,

tMOD (min)

max(3 nCK,

.9ns)

30ns)

21ns)

13ns)

2.5ns)

max

tWR+max

15ns)

+ AL + PL

3.748 ns)

Max(4nCK,4

.9ns)

Max(28nCK,

30ns)

Max(20nCK,

21ns)

Max(16nCK,

12ns)

Max (2nCK,

2.5ns)

max

(4nCK,7.5ns)- 1,34

max

(4nCK,7.5ns)-

tWR+max

(5nCK,3.75ns)- ns 1, 28

tWTR_S+ma

(5nCK,3.75n

tWTR_L+ma

(5nCK,3.75n

max(24nCK,

15ns)

tMOD (min)

+ AL + PL

max(3 nCK,

3.748 ns)

Units NOTE

- nCK 34

-ns34

- ns 1,2,e,34

- ns 2, 29, 34

- ns 3,30, 34

- nCK 50

- nCK

13,18,39

,49

13,17,18

,39,49

17,18,39

,49

17,18,39

,49

- 65 -

Page 65

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 52] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

DQS_t, DQS_c differential WRITE Preamble (1 clock preamble)

DQS_t, DQS_c differential WRITE Preamble (2 clock preamble)

DQS_t, DQS_c differential WRITE Postamble

DQS_t and DQS_c low-impedance time (Referenced from RL-1)

DQS_t and DQS_c high-impedance time (Referenced from RL+BL/2)

DQS_t, DQS_c differential input low pulse width

DQS_t, DQS_c differential input high pulse width

DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (1 clock preamble)

DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (2 clock preamble)

DQS_t, DQS_c falling edge setup time to CK_t, CK_c rising edge

DQS_t, DQS_c falling edge hold time from CK_t, CK_c rising edge

DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c with DLL On mode

DQS_t, DQS_c rising edge output variance window per DRAM

MPSM Timing

Command path disable delay upon MPSM entry

Valid clock requirement after MPSM entry tCKMPE

Valid clock requirement before MPSM exit tCKMPX

Exit MPSM to commands not requiring a locked DLL

Exit MPSM to commands requiring a locked DLL

CS setup time to CKE tMPX_S

CS_n High hold time to CKE rising edge tMPX_HH tXP(min) - tXP(min) - tXP(min) - tXP(min) - tXP(min) -

CS_n Low hold time to CKE rising edge tMPX_LH 12

Calibration Timing

Power-up and RESET calibration time tZQinit 1024 - 1024 - 1024 - 1024 - 1024 - nCK

Normal operation Full calibration time tZQoper 512 - 512 - 512 - 512 - 512 - nCK

Normal operation Short calibration time tZQCS 128 - 128 - 128 - 128 - 128 - nCK

Reset/Self Refresh Timing

Exit Reset from CKE HIGH to a valid command

Exit Self Refresh to commands not requiring a locked DLL

SRX to commands not requiring a locked DLL in Self Refresh ABORT

Exit Self Refresh to ZQCL,ZQCS and MRS (CL,CWL,WR,RTP and Gear Down)

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Minimum CKE low width for Self refresh entry to exit timing with CA Parity enabled

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE)

tWPRE 0.9 - 0.9 - 0.9 - 0.9 - 0.9 - tCK 42

tWPRE2 NA NA NA 1.8 - 1.8 - tCK 43

tWPST 0.33 - 0.33 - 0.33 - 0.33 - 0.33 - tCK

tLZ(DQS) -450 225 -390 195 -360 180 -330 175 -310 170 ps

tHZ(DQS) - 225 - 195 - 180 - 175 - 170 ps

tDQSL 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK

tDQSH 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK

tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK 42

tDQSS2 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A tCK 43

tDSS 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK

tDSH 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK

tDQSCK (DLL On)

tDQSCKI (DLL On)

tMPED

tXMP tXS(min) - tXS(min) - tXS(min) - tXS(min) - tXS(min) -

tXMPDLL

tXPR

tXS

tX-

S_ABORT(min)

tXS_FAST

(min)

tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK

tCKESR

tCKESR_ PAR

tCKSRE

-225 225 -195 195 -180 180 -175 175 -170 170 ps 37,38,39

- 370 - 330 - 310 - 290 - 270 ps 37,38,39

tMOD(min) +

tCP-

DED(min)

tMOD(min)

+tCP-

DED(min)

tCKSRX(min

)

tXMP(min) + tXSDLL(min)

tIS(min) +

tIH(min)

max

(5nCK,tRFC

(min)+

10ns)

tRFC(min)+1

0ns

tRFC4(min)+

10ns

tRFC4(min)+

10ns

tCKE(min)+1

nCK

tCKE(min)+

1nCK+PL

max(5nCK,1

0ns)

tXMP-

10ns

tMOD(min) +

tCP-

DED(min)

tMOD(min) +

tCP-

DED(min)

tCKSRX(min

)

tXMP(min) + tXSDLL(min)

tIS(min) +

tIH(min)

max

(5nCK,tRFC

(min)+

10ns)

tRFC(min)+1

0ns

tRFC4(min)+

10ns

tRFC4(min)+

10ns

tCKE(min)+1

nCK

tCKE(min)+

1nCK+PL

max(5nCK,1

0ns)

tXMP-

10ns

tMOD(min) +

tCP-

DED(min)

tMOD(min) +

tCP-

DED(min)

tCKSRX(min

)

tXMP(min)

+tXS-

DLL(min)

tIS(min) +

tIH(min)

max

(5nCK,tRFC

(min)+

10ns)

tRFC(min)+1

0ns

tRFC4(min)+

10ns

tRFC4(min)+

10ns

tCKE(min)+1

nCK

tCKE(min)+

1nCK+PL

max(5nCK,1

0ns)

tXMP-

10ns

tMOD(min) +

tCP-

DED(min)

tMOD(min) +

tCP-

DED(min)

tCKSRX(min

)

tXMP(min) +

tXSDLL(min)

tIS(min) +

tIH(min)

max

(5nCK,tRFC

(min)+10ns)

tRFC(min)+1

0ns

tRFC4(min)+

10ns

tRFC4(min)+

10ns

tCKE(min)+1

nCK

tCKE(min)+

1nCK+PL

max

(5nCK,10ns)

tXMP-

10ns

tMOD(min) +

tCP-

DED(min)

tMOD(min) +

tCP-

DED(min)

tCKSRX(min

)

tXMP(min) +

tXSDLL(min)

tIS(min) +

tIH(min)

max

(5nCK,tRFC (min)+10ns)

tRFC(min)+1

0ns

tRFC4(min)+

10ns

tRFC4(min)+

10ns

tCKE(min)+1

nCK

tCKE(min)+

1nCK+PL

max

(5nCK,10ns)

tXMP-

10ns

- nCK

Rev. 1.1

Units NOTE

ns 51

- 66 -

Page 66

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 52] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down when CA Parity is enabled

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit

Power Down Timing

Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 4 - 4 - 4 - 4 - 4 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI nCK 6

Timing of ACT command to Power Down entry

Timing of PRE or PREA command to Power Down entry

Timing of RD/RDA command to Power Down entry

Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry (BC4MRS)

Timing of WRA command to Power Down entry (BC4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

PDA Timing

Mode Register Set command cycle time in PDA mode

Mode Register Set command update delay in PDA mode

ODT Timing

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.28 0.72 tCK(avg)

Write Leveling Timing

First DQS_t/DQS_c rising edge after write leveling mode is programmed

DQS_t/DQS_c delay after write leveling mode is programmed

Write leveling setup time from rising CK_t, CK_c crossing to rising DQS_t/DQS_c crossing

Write leveling hold time from rising DQS_t/ DQS_c crossing to rising CK_t, CK_c crossing

Write leveling output delay

Write leveling output error tWLOE 0 2 0 2 0 2 0 2 0 2 ns

CA Parity Timing

Commands not guaranteed to be executed during this time

Delay from errant command to ALERT_n assertion

Pulse width of ALERT_n signal when asserted

Time from when Alert is asserted till controller must start providing DES commands in Persistent CA parity mode

Parity Latency

CRC Error Reporting

CRC error to ALERT_n latency

CRC ALERT_n pulse width

tCKSRE_PAR

tCKSRX

tXP

tACTPDEN 1 - 1 - 2 - 2 - 2 - nCK 7

tPRPDEN 1 - 1 - 2 - 2 - 2 - nCK 7

tRDPDEN RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - nCK

tWRPDEN

tWRAPDEN

tWRPBC4DEN

tWRAP-

BC4DEN

tREFPDEN 1 - 1 - 2 - 2 - 2 - nCK 7

tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) -

tMRD_PDA

tMOD_PDA tMOD tMOD tMOD tMOD tMOD

tAONAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns

tAOFAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns

tWLMRD 40 - 40 - 40 - 40 - 40 - nCK 12

tWLDQSEN 25 - 25 - 25 - 25 - 25 - nCK 12

tWLS 0.13 - 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg)

tWLH 0.13 - 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg)

tWLO 0 9.5 0 9.5 0 9.5 0 9.5 0 9.5 ns

tPAR_UN-

KNOWN

tPAR_ALERT_

RSP

PL 4 4 4 5 5 nCK

tCRC_ALERT 3 13 3 13 3 13 3 13 3 13 ns

CRC_ALERT_

max

(5nCK,10ns)

+PL

max(5nCK,1

0ns)

max

(4nCK,6ns)

max (3nCK,

5ns)

WL+4+(tWR

/tCK(avg))

WL+4+WR+

WL+2+(tWR

/tCK(avg))

WL+2+WR+

max(16nCK,

10ns)

- PL - PL - PL - PL -PL

- PL+6ns - PL+6ns - PL+6ns - PL+6ns - PL+6ns

48 96 56 112 64 128 72 144 80 160 nCK

- 43 - 50 - 57 - 64 - 71 nCK

6 10 6 10 6 10 6 10 6 10 nCK

max

(5nCK,10ns)

+PL

max(5nCK,1

0ns)

max

(4nCK,6ns)

max (3nCK,

5ns)

WL+4+(tWR

/tCK(avg))

WL+4+WR+

WL+2+(tWR

/tCK(avg))

WL+2+WR+

max(16nCK,

10ns)

max

(5nCK,10ns)

+PL

max(5nCK,1

0ns)

max

(4nCK,6ns)

max (3nCK,

5ns)

WL+4+(tWR

/tCK(avg))

WL+4+WR+

WL+2+(tWR

/tCK(avg))

WL+2+WR+

max(16nCK,

10ns)

max

(5nCK,10ns)

+PL

max

(5nCK,10ns)

max

(4nCK,6ns)

max

(3nCK, 5ns)

WL+4+(tWR

/tCK(avg))

WL+4+WR+

WL+2+(tWR

/tCK(avg))

WL+2+WR+

max(16nCK,

10ns)

max

(5nCK,10ns)

+PL

max

(5nCK,10ns)

max

(4nCK,6ns)

max

(3nCK, 5ns)

WL+4+(tWR

/tCK(avg))

WL+4+WR+

WL+2+(tWR

/tCK(avg))

WL+2+WR+

max(16nCK,

10ns)

Units NOTE

- nCK

- nCK 31,32

- nCK 4

- nCK 5

- nCK 4

- nCK 5

- nCK

- 67 -

Page 67

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 52] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Geardown timing

Exit RESET from CKE HIGH to a valid MRS geardown (T2/Reset)

CKE High Assert to Gear Down Enable time(T2/CKE)

MRS command to Sync pulse time(T3) tSYNC_GEA R - - - - - - - -

Sync pulse to First valid command(T4)

Geardown setup time

Geardown hold time

tREFI

tRFC1 (min)

tRFC2 (min)

tRFC4 (min)

tXPR_GEAR - - - - - - - - tXPR

tXS_GEAR - - - - - - - - tXS -

tCMD_GEAR - - - - - - - - tMOD - 27

tGEAR_setup - - - - - - - -2- nCK

tGEAR_hold - - - - - - - -2- nCK

2Gb 160 - 160 - 160 - 160 - 160

4Gb 260 - 260 - 260 - 260 - 260

8Gb 350 - 350 - 350 - 350 - 350

16Gb 550 - 550 - 550 - 550 - 550

2Gb110-110-110-110-110

4Gb 160 - 160 - 160 - 160 - 160

8Gb 260 - 260 - 260 - 260 - 260

16Gb 350 - 350 - 350 - 350 - 350

2Gb 90 - 90 - 90 - 90 - 90

4Gb110-110-110-110-110

8Gb 160 - 160 - 160 - 160 - 160

16Gb 260 - 260 - 260 - 260 - 260 - ns 34

tMOD +

4tCK

Rev. 1.1

Units NOTE

- 27

-ns34

- 68 -

Page 68

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

NOTE :

1) Start of internal write transaction is defined as follows : For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.

2) A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled

3) Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

4) tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK following rounding algorithm defined in "17.1 Rounding Algorithms".

5) WR in clock cycles as programmed in MR0.

6) tREFI depends on TOPER.

7) CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations.

8) For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter specifications are satisfied.

9) When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

10) When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

11) When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

12) The max values are system dependent.

13) DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are tbd.

14) The deterministic component of the total timing. Measurement method tbd.

15) DQ to DQ static offset relative to strobe per group. Measurement method tbd.

16) This parameter will be characterized and guaranteed by design.

17) When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the SDRAM input clock). Example tbd.

18) DRAM DBI mode is off.

19) DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only.

20) tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

21) tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

22) There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI

23) tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge

24) tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge

25) Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd.

26) The deterministic jitter component out of the total jitter. This parameter is characterized and guaranteed by design.

27) This parameter has to be even number of clocks

28) When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

29) When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

30) When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

31) After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification (Low pulse width).

32) After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification (HIGH pulse width).

33) Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

34) Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

35) This parameter must keep consistency with Speed-Bin Tables shown in section 10.

36) DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. UI=tCK(avg).min/2.

37) applied when DRAM is in DLL ON mode.

38) Assume no jitter on input clock signals to the DRAM.

39) Value is only valid for RONNOM = 34 ohms.

40) 1tCK toggle mode with setting MR4:A11 to 0.

41) 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400 and 2666 speed grade.

42) 1tCK mode with setting MR4:A12 to 0.

43) 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400 and 2666 speed grade.

44) The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See Figure “Clock to Data Strobe Relationship” in Operation datasheet. Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated in “Read Preamble” section.

45) DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point

46) last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High

47) VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode.

48) The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See Figure “Clock to Data Strobe Relationship” in Operation datasheet.

49) Reference level of DQ output signal is specified with a midpoint as a widest part of Output signal eye which should be approximately 0.7 * VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ.

50) For MR7 commands, the minimum delay to a subsequent non-MRS command is 5nCK.

51) tMPX_LH(max) is defined with respect to actual tXMP in system as opposed to tXMP(min).

- 69 -

Page 69

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

17.1 Rounding Algorithms

Software algorithms for calculation of timing parameters are subject to rounding errors from many sources. For example, a system may use a memory clock with a nominal frequency of 933.33... MHz, or a clock period of 1.0714... ns. Similarly, a system with a memory clock frequency of 1066.66... MHz yields mathematically a clock period of 0.9375... ns. In most cases, it is impossible to express all digits after the decimal point exactly, and rounding must be done because the DDR4 SDRAM specification establishes a minimum granularity for timing parameters of 1 ps.

Rules for rounding must be defined to allow optimization of device performance without violating device parameters. These algorithms rely on results that are within correction factors on device testing and specification to avoid losing performance due to rounding errors.

These rules are:

•Clock periods such as tCKAVGmin are defined to 1 ps of accuracy; for example, 0.9375... ns is defined as 937 ps and 1.0714... ns is defined as

1071 ps.

•Using real math, parameters like tAAmin, tRCDmin, etc. which are programmed in systems in numbers of clocks (nCK) but expressed in units of time (in ns) are divided by the clock period (in ns) yielding a unitless ratio, a correction factor of 2.5% is subtracted, then the result is set to the next higher integer number of clocks:

nCK = ceiling [(parameter_in_ns / application_tCK_in_ns) - 0.025]

•Alternatively, programmers may prefer to use integer math instead of real math by expressing timing in ps, scaling the desired parameter value by 1000, dividing by the application clock period, adding an inverse correction factor of 97.4%, dividing the result by 1000, then truncating down to the next lower integer value:

nCK = truncate [{(parameter_in_ps x 1000) / (application_tCK_in_ps) + 974} / 1000]

•Either algorithm yields identical results

- 70 -

Page 70

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

17.2 The DQ input receiver compliance mask for voltage and timing

The DQ input receiver compliance mask for voltage and timing is shown in the figure below. The receiver mask (Rx Mask) defines area the input signal must not encroach in order for the DRAM input receiver to be expected to be able to successfully capture a valid input signal with BER of 1e-16; any input signal encroaching within the Rx Mask is subject to being invalid data. The Rx Mask is the receiver property for each DQ input pin and it is not the valid data-eye.

Figure 24. DQ Receiver(Rx) compliance mask

DQx

Vcent_DQx Vcent_DQy

DQy

(Smallest Vref_DQ Level)

DQz

(Largest Vref_DQ Level)

Vcent_DQz

Vcent_DQ(midpoint)

Vref variation (Component)

Figure 25. Vcent_DQ Variation to Vcent_DQ(midpoint)

The Vref_DQ voltage is an internal reference voltage level that shall be set to the properly trained setting, which is generally Vcent_DQ(midpoint), in order to have valid Rx Mask values.

Vcent_DQ is defined as the midpoint between the largest Vref_DQ voltage level and the smallest Vref_DQ voltage level across all DQ pins for a given DDR4 DRAM component. Each DQ pin Vref level is defined by the center, i.e. widest opening, of the cumulative data input eye as depicted in Figure 25. This clarifies that any DDR4 DRAM component level variation must be accounted for within the DDR4 DRAM Rx mask.The component level Vref will be set by the system to account for Ron and ODT settings.

- 71 -

Page 71

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

DRAMa

DQx-z

DRAMb

DQy

DRAMb

DQz

DQS, DQs Data-in at DRAM Ball

Rx Mask

DQS_t

DQS_c

0.5xTdiVW 0.5xTdiVW

Rx Mask

TdiVW

DQS2DQ

Rx Mask

DQ2DQ

Rx Mask

DQS2DQ

DRAMa

VdiVW

DRAMb

VdiVW

DRAMb

VdiVW

DQx-z

DQy

DQz

DQS, DQs Data-in at DRAM Ball

Rx Mask - Alternative View

DQS_t

DQS_c

0.5xTdiVW 0.5xTdiVW

Rx Mask

TdiVW

+ 0.5 x TdiVW

DQS2DQ

Rx Mask

TdiVW

Rx Mask

TdiVW

DQ2DQ

DQS2DQ

DQ2DQ

+ 0.5 x TdiVW

VdiVW

DRAMc

Rx Mask

DQz

DQ2DQ

DRAMc

Rx Mask

DQy

NOTE : DQx represents an optimally centered mask. NOTE : DRAMa represents a DRAM without any DQS/DQ skews. DQy represents earliest valid mask. DRAMb represents a DRAM with early skews (negative t DQz represents latest valid mask.

NOTE : Figures show skew allowed between DRAM to DRAM and DQ to DQ for a DRAM. Signals assume data centered aligned at DRAM Latch.

TdiPW is not shown; composite data-eyes shown would violate TdiPW. VCENT DQ(midpoint) is not shown but is assummed to be midpoint of VdiVW..

Figure 26. DQS to DQ and DQ to DQ Timings at DRAM Balls

All of the timing terms in Figure 26 are measured at the VdIVW voltage levels centered around Vcent_DQ and are referenced to the DQS_t/DQS_c center aligned to the DQ per pin.

DRAMc

VdiVW

DQz

DQ2DQ

DRAMc

VdiVW

DQy

DRAMc represents a DRAM with delayed skews (positive t

Rx Mask

TdiVW

Rx Mask

TdiVW

DQ2DQ

DQS2DQ

DQS2DQ).

VdiVW

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Page 72

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in Figure 27 below: A low to high transition tr1 is measured from 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint) while tr2 is measured from the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min) above Vcent_DQ(midpoint).

Rising edge slew rate equations: srr1 = VdIVW(max) / tr1 srr2 = (VIHL_AC(min) – VdIVW(max)) / (2*tr2)

Figure 27. Slew Rate Conditions For Rising Transition

The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in Figure 28 below: A high to low transition tf1 is measured from 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint) while tf2 is measured from the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min) below Vcent_DQ(pin mid).

Falling edge slew rate equations: srf1 = VdIVW(max) / tf1 srf2 = (VIHL_AC(min) – VdIVW(max)) / (2*tf2)

Figure 28. Slew Rate Conditions For Falling Transition

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Page 73

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 53] DRAM DQs In Receive Mode;

Symbol Parameter

VdIVW Rx Mask voltage - pk-pk - 136 - 130 - 120 mV 1,2,10

TdIVW Rx timing window - 0.2 - 0.2 - 0.22 UI* 1,2,10

VIHL_AC DQ AC input swing pk-pk 186 - 160 - 150 - mV 3,4,10

TdIPW DQ input pulse width 0.58 - 0.58 - 0.58 - UI* 5,10

tDQS2DQ Rx Mask DQS to DQ offset -0.17 0.17 -0.17 0.17 -0.19 0.19 UI* 6, 10

tDQ2DQ Rx Mask DQ to DQ offset - TBD - TBD - 0.105 UI* 7

Input Slew Rate over VdIVW

srr1, srf1

srr2

srf2

NOTE :

1) Data Rx mask voltage and timing total input valid window where VdIVW is centered around Vcent_DQ(midpoint) after VrefDQ training is completed. The data Rx mask is applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER = e-16 when the RxMask is not violated. The BER will be characterized and extrapolated if necessary using a dual dirac method from a higher BER(tbd).

2) Defined over the DQ internal Vref range 1.

3) See Overshoot and Undershoot Specifications.

4) DQ input pulse signal swing into the receiver must meet or exceed VIHL AC(min). VIHL_AC(min) is to be achieved on an UI basis when a rising and falling edge occur in the same UI, i.e. a valid TdiPW.

5) DQ minimum input pulse width defined at the Vcent_DQ(midpoint).

6) DQS to DQ offset is skew between DQS and DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls over process, voltage, and temperature.

7) DQ to DQ offset is skew between DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls for a given component over process, voltage, and temperature.

8) Input slew rate over VdIVW Mask centered at Vcent_DQ(midpoint). Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7 V/ns of each other.

9) Input slew rate between VdIVW Mask edge and VIHL_AC(min) points.

10) All Rx Mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW(min), VdiVW(max), and minimum

slew rate limits, then either TdiVW(min) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated.

if tCK >0.937ns

Input Slew Rate over VdIVW if 0.937ns > tCK >= 0.625ns

Rising Input Slew Rate over 1/2 VIHL_AC

Falling Input Slew Rate over 1/2 VIHL_AC

1600/1866/2133 2400 2666

min max min max min max

1.0 9 1.0 9 1.0 9 V/ns 8,10

- - 1.25 9 1.25 9 V/ns 8,10

0.2*srr1 9 0.2*srr1 9 0.2*srr1 9 V/ns 9,10

0.2*srf1 9 0.2*srf1 9 0.2*srr1 9 V/ns 9,10

Unit NOTE

* UI=tck(avg)min/2

- 74 -

Page 74

Rev. 1.1

datasheet DDR4 SDRAMECC Unbuffered DIMM

17.3 Command, Control, and Address Setup, Hold, and Derating

The total tIS (setup time) and tIH (hold time) required is calculated to account for slew rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and tIH (base) values, the VIL(DC)/VIH(DC) points; to the ΔtIS and ΔtIH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential clock at 2V/ns. Example: tIS (total setup time) = tIS (base) + ΔtIS.

For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for the time defined by tVAC. Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/ VIL(AC) at the time of

the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/ VIL(AC). For slew rates that fall between the values listed in derating tables, the derating values may be obtained by linear interpolation.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)max that does not ring back above VIL(DC)max. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)minthat does not ring back above VIL(DC)max.

[Table 54] Command, Address, Control Setup and Hold Values

DDR4 1600 1866 2133 2400 2666 Unit Reference

tIS(base, AC100) 115 100 80 62 - ps VIH/L(ac)

tIH(base, DC75) 140 125 105 87 - ps VIH/L(dc)

tIS(base, AC 90) ----55psVIH/L(ac)

tIH(base, DC 65) ----80psVIH/L(dc)

tIS/tIH @ VREF 215 200 180 162 145 ps

NOTE :

1) Base ac/dc referenced for 1V/ns slew rate and 2 V/ns clock slew rate.

2) Values listed are referenced only; applicable limits are defined elsewhere.

[Table 55] Command, Address, Control Input Voltage Values

DDR4 1600 1866 2133 2400 2666 Unit Reference

VIH.CA(AC)min 100 100 100 100 90 mV VIH/L(ac)

VIH.CA(DC)min 75 75 75 75 65 mV VIH/L(dc)

VIL.CA(DC)max -75 -75 -75 -75 -65 mV VIH/L(dc)

VIL.CA(AC)max -100 -100 -100 -100 -90 mV VIH/L(ac)

NOTE :

1) Command, Address, Control input levels relative to VREFCA.

2) Values listed are referenced only; applicable limits are defined elsewhere.

- 75 -

Page 75

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 56] Derating values DDR4-1600/1866/2133/2400 tIS/tIH - ac/dc based

ΔtIS, ΔIH derating in [ps] AC/DC based

CK_t, CK_c Differential Slew Rate

10V/ns 8V/ns 6V/ns 4V/ns 3.0V/ns 2.0V/ns 1.5V/ns 1V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

7 765476557756795882608664947311189

6 735374537554775679588363927110888

5 705071517252745476568060886810585

4 654666476748695071527556836510081

CMD,

ADDR,

CNTL

Input Slew

rate

V/ns

NOTE :

1) VIH/L(ac) = +/-100mV, VIH/L(dc) = +/-75mV; relative to VREFCA.

3 57405741584260446346675075589275

2 40284128422944314633503858467563

1.5 23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50

1 -10 -10 -9 -9 -8 -8 -6 -6 -4 -4 0 0 8 8 25 25

0.9 -17 -14 -16 -14 -15 -13 -13 -10 -11 -8 -7 -4 1 4 18 21

0.8 -26 -19 -25 -19 -24 -18 -22 -16 -20 -14 -16 -9 -7 -1 9 16

0.7 -37 -26 -36 -25 -35 -24 -33 -22 -31 -20 -27 -16 -18 -8 -2 9

0.6 -52 -35 -51 -34 -50 -33 -48 -31 -46 -29 -42 -25 -33 -17 -17 0

0.5 -73 -48 -72 -47 -71 -46 -69 -44 -67 -42 -63 -38 -54 -29 -38 -13

0.4 -104 -66 -103 -66 -102 -65 -100 -63 -98 -60 -94 -56 -85 -48 -69 -31

Rev. 1.1

[Table 57] Derating values DDR4-2666 tIS/tIH - ac/dc based

ΔtIS, ΔIH derating in [ps] AC/DC based

10V/ns 8V/ns 6V/ns 4V/ns 3.0V/ns 2.0V/ns 1.5V/ns 1V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

4 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

CMD,

ADDR,

CNTL

Input Slew

rate

V/ns

NOTE :

1) VIH/L(ac) = +/-tbd mV, VIH/L(dc) = +/- tbd mV; relative to VREFCA

3 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

1.5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

0.4 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

CK_t, CK_c Differential Slew Rate

- 76 -

Page 76

datasheet DDR4 SDRAMECC Unbuffered DIMM

17.4 DDR4 Function Matrix

DDR4 SDRAM has several features supported by ORG and also by Speed. The following Table is the summary of the features.

[Table 58] Function Matrix (By ORG. V:Supported, Blank:Not supported)

Functions x4 x8 NOTE

Write Leveling

Temperature controlled Refresh

Low Power Auto Self Refresh

Fine Granularity Refresh

Multi Purpose Register

Data Mask

Data Bus Inversion

TDQS

ZQ calibration

DQ Vref Training

Per DRAM Addressability

Mode Register Readout

CAL

WRITE CRC

CA Parity

Control Gear Down Mode

Programmable Preamble

Maximum Power Down Mode

Boundary Scan Mode

Additive Latency

3DS

Rev. 1.1

- 77 -

Page 77

datasheet DDR4 SDRAMECC Unbuffered DIMM

[Table 59] Function Matrix (By Speed. V:Supported, Blank:Not supported)

DLL Off mode DLL On mode

Functions

Write Leveling

Temperature controlled Refresh

Low Power Auto Self Refresh

Fine Granularity Refresh

Multi Purpose Register

Data Mask

Data Bus Inversion

TDQS

ZQ calibration

DQ Vref Training

Per DRAM Addressability

Mode Register Readout

CAL

WRITE CRC

CA Parity

Control Gear Down Mode

Programmable Preamble (= 2tCK)

Maximum Power Down Mode

Boundary Scan Mode

3DS

equal or slower

than 250Mbps

VVVV

1600/1866/2133

Mbps

VVV

2400Mbps 2666Mbps

Rev. 1.1

NOTE

- 78 -

Page 78

datasheet DDR4 SDRAMECC Unbuffered DIMM

18. PHYSICAL DIMENSIONS

18.1 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB1

133.35

126.65

(2X 3.35)

30.75

Rev. 1.1

Units : Millimeters

31.25

0.35 Max

C A D B

56.10

4.30

1.50±0.05

0.35 Max

64.60

3.85±0.10

Detail A

0.6 ± 0.03

0.85

Max 1.20

1.40±0.10

NOTE : Passive devices are in the back

side only for M391A1K43BB1

2.1 B

2.60 E

0.25

0.50

Detail B,E

The used device is 1G x8 DDR4 SDRAM, FBGA. DDR4 SDRAM Part NO : K4A8G085WB-BC**

NOTE :

1) Tolerances on all dimensions ±0.15 unless otherwise specified.

2.10

9.35

10.20

Detail C

- 79 -

2.60

9.35

10.20

Detail D

2.10

0.50

Page 79

datasheet DDR4 SDRAMECC Unbuffered DIMM

18.2 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB2

133.35

126.65

(2X 3.35)

30.75

31.25

Max 1.20

Rev. 1.1

Units : Millimeters

0.35 Max

2.1 B

2.60 E

C A D B

56.10

4.30

1.50±0.05

0.35 Max

3.85±0.10

Detail A

0.6 ± 0.03

0.85

2.10

0.25

0.50

Detail B,E

64.60

9.35

10.20

Detail C

2.60

1.40±0.10

9.35

10.20

Detail D

2.10

0.50

The used device is 1G x8 DDR4 SDRAM, FBGA. DDR4 SDRAM Part NO : K4A8G085WB-BC**

NOTE :

1) Tolerances on all dimensions ±0.15 unless otherwise specified.

- 80 -

Page 80

datasheet DDR4 SDRAMECC Unbuffered DIMM

18.3 1Gx8 based 2Gx72 Module (2 Ranks) - M391A2K43BB1

133.35

30.75

126.65

(2X 3.35)

Rev. 1.1

Units : Millimeters

31.25

0.35 Max

C A D B

56.10

4.30

1.50±0.05

0.35 Max

Detail A

0.6 ± 0.03

0.85

2.1 B

2.60 E

0.25

0.50

Detail B,E

The used device is 1G x8 DDR4 SDRAM, FBGA. DDR4 SDRAM Part NO : K4A8G085WB-BC**

NOTE :

1) Tolerances on all dimensions ±0.15 unless otherwise specified.

3.85±0.10

2.10

64.60

9.35

10.20

Detail C

Max 3.9

1.40±0.10

2.60

9.35

10.20

Detail D

2.10

0.50

- 81 -

Samsung M391A1K43BB2-CTD User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

288pin ECC Unbuffered DIMM based on 8Gb B-die

1. DDR4 Unbuffered DIMM ORDERING INFORMATION

2. KEY FEATURES

3. ADDRESS CONFIGURATION

4. x72 DIMM Pin Configurations (Front side/Back side)

5. PIN DESCRIPTION

6. INPUT/OUTPUT FUNCTIONAL DESCRIPTION

6.1 Address Mirroring

7. FUNCTION BLOCK DIAGRAM:

7.1 8GB, 1Gx72 ECC Module (Populated as 1 rank of x8 DDR4 SDRAMs)

7.2 16GB, 2Gx72 ECC Module (Populated as 2 ranks of x8 DDR4 SDRAMs)

8. ABSOLUTE MAXIMUM RATINGS

9. AC & DC OPERATING CONDITIONS

10. AC & DC INPUT MEASUREMENT LEVELS

10.1 AC & DC Logic Input Levels for Single-Ended Signals

10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

10.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)

10.3.3 Single-ended Requirements for Differential Signals

10.3.4 Address, Command and Control Overshoot and Undershoot specifications

10.3.5 Clock Overshoot and Undershoot Specifications

10.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications

10.4 Slew Rate Definitions

10.4.1 Slew Rate Definitions for Differential Input Signals (CK)

10.4.2 Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

10.5 Differential Input Cross Point Voltage

10.6 CMOS rail to rail Input Levels

10.6.1 CMOS rail to rail Input Levels for RESET_n

10.7 AC and DC Logic Input Levels for DQS Signals

10.7.1 Differential signal definition

10.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)

10.7.3 Peak voltage calculation method

10.7.4 Differential Input Cross Point Voltage

10.7.5 Differential Input Slew Rate Definition

11. AC AND DC OUTPUT MEASUREMENT LEVELS

11.1 Output Driver DC Electrical Characteristics

11.1.1 Alert_n output Drive Characteristic

11.1.2 Output Driver Characteristic of Connectivity Test (CT) Mode

11.2 Single-ended AC & DC Output Levels

11.3 Differential AC & DC Output Levels

11.4 Single-ended Output Slew Rate

11.5 Differential Output Slew Rate

11.6 Single-ended AC & DC Output Levels of Connectivity Test Mode

11.7 Test Load for Connectivity Test Mode Timing

12. SPEED BIN

12.1 Speed Bin Table Note

13. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS

13.1 IDD, IPP and IDDQ Measurement Conditions

14. IDD SPEC TABLE

15. INPUT/OUTPUT CAPACITANCE

16. ELECTRICAL CHARACTERISTICS & AC TIMING

16.1 Reference Load for AC Timing and Output Slew Rate

16.2 tREFI

16.3 Clock Specification

16.3.1 Definition for tCK(abs)

16.3.2 Definition for tCK(avg)

16.3.3 Definition for tCH(avg) and tCL(avg)

16.3.4 Definition for tERR(nper)

17. TIMING PARAMETERS BY SPEED GRADE

17.1 Rounding Algorithms

17.2 The DQ input receiver compliance mask for voltage and timing

17.3 Command, Control, and Address Setup, Hold, and Derating

17.4 DDR4 Function Matrix

18. PHYSICAL DIMENSIONS

18.1 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB1

18.2 1Gx8 based 1Gx72 Module (1 Rank) - M391A1K43BB2

18.3 1Gx8 based 2Gx72 Module (2 Ranks) - M391A2K43BB1