Samsung M386A8K40CM2-CTD User Manual

Rev. 1.2, Feb. 2018

M386A8K40CM2

288pin Load Reduced DIMM

based on 8Gb C-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

datasheet

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- 1 -

Rev. 1.2

Load Reduced DIMM

datasheet

DDR4 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC Release 7th Apr. 2017 - J.Y.Lee

1.1 - Update Physical Dimension. 13th Jun, 2017 Final J.Y.Bae

1. Add PCB hole.

2. Change Module height information.

1.2 - Add 2933Mbps. 6th Feb, 2018 Final J.H.Han

- Correct typo. J.Y.Bae

- 2 -

Rev. 1.2

datasheet

DDR4 SDRAMLoad Reduced DIMM

Table Of Contents

288pin Load Reduced DIMM based on 8Gb C-die

1. DDR4 Load Reduced DIMM ORDERING INFORMATION ..................................................................................................................4

2. KEY FEATURES ..................................................................................................................................................................................4

3. ADDRESS CONFIGURATION .............................................................................................................................................................4

4. Load Reduced DIMM PIN COFIGURATIONS (FRONT SIDE / BACK SIDE) ......................................................................................5

5. PIN DESCRIPTION .............................................................................................................................................................................6

6. ON DIMM THERMAL SENSOR ...........................................................................................................................................................7

7. INPUT/OUTPUT FUNCTIONAL DESCRIPTION .................................................................................................................................8

8. REGISTERING CLOCK DRIVER SPECIFICATION ............................................................................................................................10

8.1 Timing & Capacitance Values.........................................................................................................................................................10

8.2 Clock Driver Characteristics ...........................................................................................................................................................10

9. FUNCTION BLOCK DIAGRAM: ...........................................................................................................................................................11

9.1 64GB, 8Gx72 Module (Populated as 4 ranks of x4 DDR4 SDRAMs).............................................................................................11

10. ABSOLUTE MAXIMUM RATINGS .....................................................................................................................................................14

10.1 Absolute Maximum DC Ratings.................................................................................................................................................... 14

11. AC & DC OPERATING CONDITIONS ...............................................................................................................................................14

12. AC & DC INPUT MEASUREMENT LEVELS......................................................................................................................................15

12.1 AC & DC Logic Input Levels for Single-Ended Signals................................................................................................................. 15

12.2 AC and DC Input Measurement Levels: VREF Tolerances. ......................................................................................................... 15

12.3 AC and DC Logic Input Levels for Differential Signals .................................................................................................................16

12.3.1. Differential Signals Definition ................................................................................................................................................16

12.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ....................................................................................................17

12.3.3. Single-ended Requirements for Differential Signals .............................................................................................................18

12.3.4. Address, Command and Control Overshoot and Undershoot specifications........................................................................ 19

12.3.5. Clock Overshoot and Undershoot Specifications.................................................................................................................. 20

12.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................................................... 21

12.4 Slew Rate Definitions.................................................................................................................................................................... 22

12.4.1. Slew Rate Definitions for Differential Input Signals (CK) ......................................................................................................22

12.4.2. Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ........................................................................................23

12.5 Differential Input Cross Point Voltage........................................................................................................................................... 24

12.6 CMOS rail to rail Input Levels .......................................................................................................................................................25

12.6.1. CMOS rail to rail Input Levels for RESET_n .........................................................................................................................25

12.7 AC and DC Logic Input Levels for DQS Signals........................................................................................................................... 26

12.7.1. Differential signal definition ...................................................................................................................................................26

12.7.2. Differential swing requirements for DQS (DQS_t - DQS_c).................................................................................................. 26

12.7.3. Peak voltage calculation method ..........................................................................................................................................27

12.7.4. Differential Input Cross Point Voltage ...................................................................................................................................28

12.7.5. Differential Input Slew Rate Definition ..................................................................................................................................29

13. AC and DC output Measurement levels .............................................................................................................................................30

13.1 Output Driver DC Electrical Characteristics..................................................................................................................................30

13.1.1. Alert_n output Drive Characteristic .......................................................................................................................................32

13.1.2. Output Driver Characteristic of Connectivity Test (CT) Mode............................................................................................... 33

13.2 Single-ended AC & DC Output Levels.......................................................................................................................................... 34

13.3 Differential AC & DC Output Levels.............................................................................................................................................. 34

13.4 Single-ended Output Slew Rate ...................................................................................................................................................35

13.5 Differential Output Slew Rate .............................................................................................

13.6 Single-ended AC & DC Output Levels of Connectivity Test Mode ...............................................................................................37

13.7 Test Load for Connectivity Test Mode Timing ..............................................................................................................................38

14. IDD SPEC TABLE ..............................................................................................................................................................................39

15. INPUT/OUTPUT CAPACITANCE ......................................................................................................................................................41

16. SPEED BIN ........................................................................................................................................................................................42

16.1 Speed Bin Table Note................................................................................................................................................................... 48

17. IDD and IDDQ Specification Parameters and Test conditions ...........................................................................................................49

17.1 IDD, IPP and IDDQ Measurement Conditions.............................................................................................................................. 49

18. DIMM IDD SPECIFICATION DEFINITION .........................................................................................................................................52

19. TIMING PARAMETERS BY SPEED GRADE ....................................................................................................................................64

19.1 Rounding Algorithms ...................................................................................................................................................................70

19.2 The DQ input receiver compliance mask for voltage and timing .................................................................................................. 71

19.3 Command, Control, and Address Setup, Hold, and Derating .......................................................................................................74

19.4 DDR4 Function Matrix ..................................................................................................................................................................76

20. PHYSICAL DIMENSIONS ..................................................................................................................................................................78

20.1 4Gbx4(DDP) based 8Gx72 Module (4 Ranks) - M386A8K40CM2...............................................................................................78

20.1.1. x72 DIMM, populated as Quad physical ranks of x4 DDR4 SDRAMs ..................................................................................78

..........................................................36

- 3 -

Rev. 1.2

datasheet

DDR4 SDRAMLoad Reduced DIMM

1. DDR4 Load Reduced DIMM ORDERING INFORMATION

[Table 1] Ordering Information Table

Part Number

M386A8K40CM2-CRC/TD/VF 64GB 8Gx72 DDP 4Gx4(K4AAG045WC-MC##)*36 4 31.25mm

NOTE :

1) "##" - RC/TD/VF

2) RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)/VF(2933Mbps 21-21-21).

- Backward compatible to lower frequency.

2)

Density Organization

Component Composition

1)

Number of

Rank

2. KEY FEATURES

[Table 2] Speed Bins

Speed

tCK(min) 1.25 1.071 0.937 0.833 0.75 0.682 ns

CAS Latency 11 13 15 17 19 21 nCK

tRCD(min) 13.75 13.92 14.06 14.16 14.25 14.32 ns

tRP(min) 13.75 13.92 14.06 14.16 14.25 14.32 ns

tRAS(min) 35 34 33 32 32 32 ns

tRC(min) 48.75 47.92 47.06 46.16 46.25 46.32 ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933

11- 11-11 13-13-13 15-15-15 17-17-17 19-19-19 21-21-21

Height

Unit

• JEDEC standard 1.2V ± 0.06V Power Supply

•V

• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin, 1333MHz

• 16 Banks (4 Bank Groups)

• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20,21

• Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866), 11,14 (DDR4-2133), 12,16 (DDR4-2400), 14,18 (DDR4-2666)

• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

= 1.2V ± 0.06V

DDQ

for 2666Mb/sec/pin and 1467MHz fCK for 2933Mb/sec/pin.

f

CK

and 16, 20 (DDR4-2933).

85C, 3.9us at 85C < T

CASE

CASE

95C

3. ADDRESS CONFIGURATION

Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge

4Gx4(16Gb DDP) based Module A0-A16 A0-A9 BG0-BG1 BA0-BA1 A10/AP

- 4 -

Rev. 1.2

datasheet

4. Load Reduced DIMM PIN COFIGURATIONS

DDR4 SDRAMLoad Reduced DIMM

(FRONT SIDE / BACK SIDE)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

2 VSS 146 VREFCA 41

3 DQ4 147 VSS 42 VSS 186 DQS3

4 VSS 148 DQ5 43 DQ30 187 VSS 81 BA0 225 A10/AP 120 VSS 264 DQ49

5 DQ0 149 VSS 44 VSS 188 DQ31 82 RAS

6 VSS 150 DQ1 45 DQ26 189 VSS 83 VDD 227 RFU 122

7

8

9 VSS 153 DQS0

10 DQ6 154 VSS 49 CB0 193 VSS 87 ODT0 231 VDD 126 DQ50 270 VSS

11 VSS 155 DQ7 50 VSS 194 CB1 88 VDD 232 A13 127 VSS 271 DQ51

12 DQ2 156 VSS 51

13 VSS 157 DQ3 52

14 DQ12 158 VSS 53 VSS 197 DQS8

15 VSS 159 DQ13 54 CB6 198 VSS 92 VDD 236 VDD 131 VSS 275 DQ57

16 DQ8 160 VSS 55 VSS 199 CB7 93 C0,CS2

17 VSS 161 DQ9 56 CB2 200 VSS 94 VSS 238 SA2 133

18

19

20 VSS 164 DQS1

21 DQ14 165 VSS 60 CKE0 204 VDD 98 VSS 242 DQ33 137 DQ58 281 VSS

22 VSS 166 DQ15 61 VDD 205 RFU 99

23 DQ10 167 VSS 62 ACT

24 VSS 168 DQ11 63 BG0 207 BG1 101 VSS 245 DQS4

25 DQ20 169 VSS 64 VDD 208 ALERT

26 VSS 170 DQ21 65 A12/BC

27 DQ16 171 VSS 66 A9 210 A11 104 DQ34 248 VSS 143 VPP 287 VPP

28 VSS 172 DQ17 67 VDD 211 A7 105 VSS 249 DQ35 144 RFU 288

29

30

31 VSS 175 DQS2

32 DQ22 176 VSS 71 A3 215 VDD 109 VSS 253 DQ41

33 VSS 177 DQ23 72 A1 216 A2 110

34 DQ18 178 VSS 73 VDD 217 VDD 111

35 VSS 179 DQ19 74 CK0

36 DQ28 180 VSS 75 CK0

37 VSS 181 DQ29 76 VDD 220 VDD 114 VSS 258 DQ47

38 DQ24 182 VSS 77 VTT 221 VTT 115 DQ42 259 VSS

39 VSS 183 DQ25 KEY 116 VSS 260 DQ43

3

12V

,NC

TDQS9_t,

DQS9_t

TDQS9_c,

DQS9_c

TDQS10_t,

DQS10_t

TDQS10_c,

DQS10_c

TDQS11_t,

DQS11_t

TDQS11_c,

DQS11_c

145

12V3,NC

151 VSS 46 VSS 190 DQ27 84 S0

152 DQS0

162 VSS 57 VSS 201 CB3 95 DQ36 239 VSS 134 VSS 278 DQS7

163 DQS1

173 VSS 68 A8 212 VDD 106 DQ44 250 VSS

174 DQS2

_c

_t

_c

_t

_c

_t

TDQS12_t,

40

DQS12_t

TDQS12_c,

DQS12_c

47 CB4 191 VSS 85 VDD 229 VDD 124 DQ54 268 VSS

48 VSS 192 CB5 86 CAS_n/A15 230 NC 125 VSS 269 DQ55

TDQS17_t,

DQS17_t

TDQS17_c,

DQS17_c

58 RESET

59 VDD 203 CKE1 97 DQ32 241 VSS 136 VSS 280 DQ63

69 A6 213 A5 107 VSS 251 DQ45

70 VDD 214 A4 108 DQ40 252 VSS

184 VSS 78 EVENT

185 DQS3

195 VSS 89 S1

196 DQS8

_n

202 VSS 96 VSS 240 DQ37 135 DQ62 279 VSS

_n

206 VDD 100

_n

209 VDD 103 VSS 247 DQ39 142 VPP 286 VPP

_t

218 CK1

_c

219 CK1

_c

79 A0 223 VDD 118 VSS 262 DQ53

_t

80 VDD 224 BA1 119 DQ48 263 VSS

_c

90 VDD 234 A17 129 VSS 273 DQ61

_t

91 ODT1 235 NC,C2 130 DQ56 274 VSS

_n

102 DQ38 246 VSS 141 SCL 285 SDA

_t

112 VS S 25 6 DQS 5

_c

113 D Q46 257 VS S

_n

222 PARITY 117 DQ52 261 VSS

_n

/A16 226 VDD 121

_n

228 WE_n/A14 123 VSS 267 DQS6

_n

233 VDD 128 DQ60 272 VSS

_n

,NC 237 NC,CS3_c,C1 132

TDQS13_t,

DQS13_t

TDQS13_c,

DQS13_c

TDQS14_t,

DQS14_t

TDQS14_c,

DQS14_c

243 VSS 138 VSS 282 DQ59

244 DQS4

254 VSS

255 DQS5

TDQS15_t,

DQS15_t

TDQS15_c,

DQS15_c

TDQS16_t,

DQS16_t

TDQS16_c,

DQS16_c

_c

139 SA0 283 VSS

_t

140 SA1 284 VDDSPD

_c

_t

265 VSS

266 DQS6

276 VSS

277 DQS7

VPP

_c

_t

_c

_t

4

NOTE:

1) VPP is 2.5V DC

2) Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs.

3) Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM

4) The 5th VPP is required on all modules. DIMMs.

- 5 -

Rev. 1.2

datasheet

DDR4 SDRAMLoad Reduced DIMM

5. PIN DESCRIPTION

Pin Name Description Pin Name Description

1)

A0–A17

BA0, BA1 Register bank select input SDA I

BG0, BG1 Register bank group select input SA0–SA2 I

RAS_n

CAS_n

WE_n

CS0_n, CS1_n,

CS2_n, CS3_n

CKE0, CKE1 Register clock enable lines input VSS Power supply return (ground)

ODT0, ODT1 Register on-die termination control lines input VDDSPD Serial SPD/TS positive power supply

ACT_n Register input for activate input ALERT_n Register ALERT_n output

DQ0–DQ63 DIMM memory data bus RESET_n Set Register and SDRAMs to a Known State

CB0–CB7 DIMM ECC check bits EVENT_n SPD signals a thermal event has occurred

DQS0_t–
DQS17_t

DQS0_c–
DQS17_c

CK0_t, CK1_t

CK0_c, CK1_c

Register address input SCL I2C serial bus clock for SPD/TS and register

2

C serial bus data line for SPD/TS and register

2

C slave address select for SPD/TS and register

2)

Register row address strobe input PAR Register parity input

3)

Register column address strobe input VDD SDRAM core power supply

4)

Register write enable input VPP SDRAM activating power supply

DIMM Rank Select Lines input VREFCA SDRAM command/address reference supply

Data Buffer data strobes
(positive line of differential pair)

Data Buffer data strobes
(negative line of differential pair)

Register clock input
(positive line of differential pair)

Register clocks input
(negative line of differential pair)

VTT

RFU Reserved for future use

SDRAM I/O termination supply

NOTE :

1) Address A17 is only valid for 16 Gb x4 based SDRAMs.

2) RAS_n is a multiplexed function with A16.

3) CAS_n is a multiplexed function with A15.

4) WE_n is a multiplexed function with A14.

- 6 -

Rev. 1.2

SA0 SA1 SA2

SA0

SA1

SDA

SCL

EVENT_n

SA2

EVENT_n

Serial PD with

Register

Thermal sensor

SA0 SA1 SA2

SDA

SCL

SDA

SCL

ZQCAL

VSS

1K

BFUNC

VSS

datasheet

6. ON DIMM THERMAL SENSOR

NOTE :

1) All Samsung RDIMM support Thermal sensor on DIMM.

[Table 3] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

B

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

Min. Typ . Max.

Temperature Sensor Accuracy

DDR4 SDRAMLoad Reduced DIMM

Units NOTE

-

C

- 7 -

Rev. 1.2

datasheet

7. INPUT/OUTPUT FUNCTIONAL DESCRIPTION

[Table 4] Input/Output Function Description

Symbol Type Function

CK_t, CK_c

CKE, (CKE1) Input

CS_n, (CS1_n)

C0, C1, C2 Input

ODT, (ODT1) Input

ACT_n Input

RAS_n/A16.
CAS_n/A15.

WE_n/A14

DM_n/DBI_n/
TDQS_t, (DMU_n/
DBIU_n), (DML_n/

DBIL_n)

BG0 - BG1 Input

BA0 - BA1 Input

A0 - A17 Input

A10 / AP Input

A12 / BC_n Input

RESET_n Input

DQ

Input/Output

Input

Input

Input

Input/

Output

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and
output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal
DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE are disabled
during Self-Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on
systems with multiple Ranks. CS_n is considered part of the command code.

Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID
is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM.
When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/ TDQS_t, NU/TDQS_c (When
TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied
to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is
programmed to disable RTT_NOM.

Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into
RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered.
Those pins have multi function. For example, for activation with ACT_n Low, these are Addressing like A16, A15 and
A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command
defined in command truth table

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when
DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on both edges of
DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of
DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifing whether to store/
output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4
SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in X8

Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being
applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8 have BG0 and BG1
but X16 has only BG0.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16,
CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code
during Mode Register Set commands. A17 is only defined for the x4 configurations.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be
performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be
performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH.
RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80%
and 20% of VDD.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of
Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4
A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor specific datasheets to determine which
DQ is used.

DDR4 SDRAMLoad Reduced DIMM

- 8 -

Rev. 1.2

datasheet

[Table 4] Input/Output Function Description

Symbol Type Function

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the

DQS_t, DQS_c,

DQSU_t, DQSU_c,

DQSL_t, DQSL_c

TDQS_t, TDQS_c Output

PAR Input

ALERT_n

TEN

NC No Connect: No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V

VSSQ Supply DQ Ground

VDD Supply

VSS Supply

VPP Supply

VREFCA Supply

ZQ Supply

Input/

Output

Input/

Output

Input

x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe
DQS_t , DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to
provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data
strobe only and does not support single-ended.

Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode Register A11 =
1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/TDQS_c that is applied to
DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function
or Data Bus Inversion depending on MR5; A11,12,10and TDQS_c is not used. x4/x16 DRAMs must disable the TDQS
function via mode register A11 = 0 in MR1.

Command and Address Parity Input: DDR4 Supports Even Parity check in DRAM with MR setting. Once it’s enabled
via Register in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0­BA1, A17-A0 and C0-C2 (3DS devices). Command and address inputs shall have parity check performed when
commands are latched via the rising edge of CK_t and when CS_n is low.

Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there
is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in
Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM internal
recovery transaction is complete. During Connectivity Test mode, this pin works as input.
Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin must be bounded
to VDD on board.

Connectivity Test Mode Enable : Required on X16 devices and optional input on x4/x8 with densities equal to or
greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail
to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin
may be DRAM internally pulled low through a weak pull-down resistor to VSS.

Power Supply: 1.2 V ± 0.06 V

Ground

DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)

Reference voltage for CA

Reference Pin for ZQ calibration.

DDR4 SDRAMLoad Reduced DIMM

NOTE :

1) Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.

- 9 -

Rev. 1.2

datasheet

DDR4 SDRAMLoad Reduced DIMM

8. REGISTERING CLOCK DRIVER SPECIFICATION

8.1 Timing & Capacitance Values

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 625 1080 625 1350 TBD TBD MHz

t

CH/tCL

t

ACT

t

PDM

t

t

C

C

NOTE :

1) This parameter does not include package capacitance.

2) Data inputs are DCKE0/1,DODT0/1,DA0,DA17, DBA0,DBA1,DBG0,DBG1,DACT_n, DC0,DC2, DPAR, DCS0/1_n

Pulse duration, CK_t, CK_c
HIGH or LOW

Inputs active time4 before
DRST_n is taken HIGH

Propagation delay, single-bit
switching, CK_t/ CK_c to output

output disable time

DIS

output enable time

EN

C

Input capacitance, Data inputs

I

Input capacitance, CK_t, CK_c

CK

Input capacitance, DRST_n

IR

DCKE0/1 = LOW and
DCS0/1_n = HIGH

1.2V Operation 1 1.3 1 1.3 TBD TBD ns

Rising edge of Yn_t to
output float

Output valid to rising
edge of Yn_t

1,2

NOTE

1,2

NOTE

or VSS;

V

I=VDD

=1.2V

V

DD

DDR4-1600/1866/2133 DDR4-2400/2666 DDR4-2933

Min Max Min Max Min Max

0.4 - 0.4 - TBD -

16 - 16 - TBD -

0.5*tCK +

tQSK1(min

)

0.5*tCK -

tQSK1(ma

x)

0.8 1.1 0.8 1.0 TBD TBD

0.8 1.1 0.8 1.0 TBD TBD

0.5 2.0 0.5 2.0 TBD TBD

-

-

0.5*tCK +

tQSK1(min

)

0.5*tCK -

tQSK1(ma

x)

-TBD-ps

-TBD-ps

Units

t

CK

t

CK

pF

8.2 Clock Driver Characteristics

Symbol Parameter Conditions

t

jit

t

t

t

jit

t

jit

t

t

(cc)

STAB

CKsk

(per)

(hper)

Qsk1

dynoff

Cycle-to-cycle period jit­ter

Stabilization time - 5 - 5 - 5 - TBD us

Clock Output skew - 10 - 10 - 10 - TBD ps

Yn Clock Period jitter

Half period jitter

Qn Output to clock toler­ance

Maximum re-driven
dynamic clock off-set

CK_t/CK_c sta­ble

-0.025 *

-0.032 *

-0.125 *

DDR4-1600/1866/

2133

Min Max Min Max Min Max Min Max

0

tCK

tCK

tCK

-50-45-45-TBDps

0.025 x
tCK

0.025 *
tCK

0.032 *
tCK

0.125 *
tCK

DDR4-2400 DDR4-2666 DDR4-2933

0 0.025 x tCK 0

-0.025 *

-0.032 *

-0.125 *

0.025 * tCK

tCK

0.032 * tCK

tCK

0.125 * tCK -0.1 * tCK 0.1 * tCK TBD TBD ps

tCK

-0.025 *
tCK

-0.032 *
tCK

0.025 x
tCK

0.025 *
tCK

0.032 *
tCK

TBD TBD ps

TBD TBD ps

TBD TBD ps

Units

- 10 -

Rev. 1.2

CK0_t

CK0_c

BA[1:0]

BG[1:0]A -> BA[1:0]: SDRAMs D[3:0],D8,D[12:9],D17,D[3B:0B],D8B,D[12B:9B],D17B

A[17:0]

A[17:0]A -> A[17:0]: SDRAMs D[3:0],D8,D[12:9],D17,D[3B:0B],D8B,D[12B:9B],D17B

CS[3:0]_n

ODT0, ODT1

RESET_n

BG[1:0]B -> BA[1:0]: SDRAMs D[7:4],D[16:13],D[7B:4B],D[16B:13B]

A[17:0]B -> A[17:0]: SDRAMs D[7:4],D[16:13],D[7B:4B],D[16B:13B]

QRESET_n -> RESET_n: All SDRAMs

PARITY, ACT_n

CK1_t

CK1_c

Y0(_t,_c) -> CK(_t,_c): SDRAMs D[16:13],D[16B:13B]

BG[1:0]

BG[1:0]A -> BG[1:0]: SDRAMs D[3:0],D8,D[12:9],D17,D[3B:0B],D8B,D[12B:9B],D17B

BG[1:0]B -> BG[1:0]: SDRAMs D[7:4],D[16:13],D[7B:4B],D[16B:13B]

CKE1A -> CKE: SDRAMs D[3B:0B],D8B,D[12B:9B],D17B

CKE1B -> CKE: SDRAMs D[7B:4B],D[16B:13B]

ODT0A -> ODT: SDRAMs D[3:0],D8,D[12:9],D17

ODT0B -> ODT: SDRAMs D[7:4],D[16:13]

CS0A_n -> CS_n: SDRAMs D[3:0],D8,D[12:9],D17

CS0B_n -> CS_n: SDRAMs D[7:4],D[16:13]

PARA -> PAR,ACT_n: SDRAMs D[3:0],D8,D[12:9],D17,D[3B:0B],D8B,D[12B:9B],D17B

PARB -> PAR,ACT_n: SDRAMs D[7:4],D[16:13],D[7B:4B],D[16B:13B]

CKE0, CKE1

CKE0A -> CKE: SDRAMs D[3:0],D8,D[12:9],D17

CKE0B -> CKE: SDRAMs D[7:4],D[16:13]

R
e
g

i

s

t
e
r.

ODT1A -> ODT: SDRAMs D[3B:0B],D8B,D[12B:9B],D17B

ODT1B -> ODT: SDRAMs D[7B:4B],D[16B:13B]

CS1A_n -> CS_n: SDRAMs D[3B:0B],D8B,D[12B:9B],D17B

CS1B_n -> CS_n: SDRAMs D[7B:4B],D[16B:13B]

Y1(_t,_c) -> CK(_t,_c): SDRAMs D[12:9],D17,D[12B:9B],D17B

Y2(_t,_c) -> CK(_t,_c): SDRAMs D[7:4],D[7B:4B]

Y3(_t,_c) -> CK(_t,_c): SDRAMs D[3:0],D8,D[7B:4B],D8B

ALERT_n

ERROR_IN_n <- ALERT_n: All SDRAMs

CS2A_n -> CS_n: SDRAMs D[3:0],D8,D[12:9],D17

CS2B_n -> CS_n: SDRAMs D[7:4],D[16:13]

CS3A_n -> CS_n: SDRAMs D[3B:0B],D8B,D[12B:9B],D17B

CS3B_n -> CS_n: SDRAMs D[7B:4B],D[16B:13B]

Address, Command and Control lines

Back

Front

D13D14D15D16

D4 D5 D6 D7

D9 D10 D11 D12 D17

D0 D1 D2 D3 D8

D9B D10B D11B D12B D17B

D0B D1B D2B D3B D8B

D13B D14B D15B D16B

D4B D5B D6B D7B

datasheet

DDR4 SDRAMLoad Reduced DIMM

9. FUNCTION BLOCK DIAGRAM:

9.1 64GB, 8Gx72 Module (Populated as 4 ranks of x4 DDR4 SDRAMs)

NOTE :

_t

1) CK0
_t

2) CK1

3) Unless otherwise noted resistors are 22 ± 5%.

, CK0_c terminated with 120 ± 5% resistor.
, CK1_c terminated with 120 ± 5% resistor but not used.

- 11 -

Rev. 1.2

CKE1A

VSS

CS3A_n

CKE1A

ODT1A

CS1A_n

DQ[3:0]

DQS0_t
DQS0_c

DQ[7:4]

DQS9_t

DQS9_c

CKE0A

VSS

CS2A_n

D0

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

CKE0A

ODT0A

CS0A_n

D9

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D9B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D0B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[11:8]

DQS1_t
DQS1_c

DQ[15:12]

DQS10_t

DQS10_c

D1

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D10

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D10B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D1B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[19:16]

DQS2_t
DQS2_c

DQ[23:20]

DQS11_t

DQS11_c

D2

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D11

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D11B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D2B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[27:24]

DQS3_t
DQS3_c

DQ[31:28]

DQS12_t

DQS12_c

D3

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D12

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D12B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D3B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

CB[3:0]

DQS8_t
DQS8_c

CB[7:4]

DQS17_t

DQS17_c

D8

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D17

DQS_c

DQS_t

C

K

E

0

C

S

0
_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D17B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D8B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

datasheet

DDR4 SDRAMLoad Reduced DIMM

- 12 -

NOTE :

1) ZQ resistors are 240 ±1%. For all other resistor values refer to the appropriate wiring diagram.

2) See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3) TEN pin of SDRAMs is tied to VSS.

4) DQ stub resistors are 15Ω ±5%. For all other resistor values refer to the appropriate wiring diagram.

Rev. 1.2

V

SS

D0-D35

D0-D35

V

DD

4

V

DDSPD

4

Serial PD

VREFCA

V

TT

D0-D35

V

PP

D0-D35

SA0 SA1 SA2

SA0

SA1

SDA

SCL

EVENT_n

SA2

EVENT_n

Serial PD with

Register

Thermal sensor

SA0 SA1 SA2

SDA

SCL

SDA

SCL

ZQCAL

VSS

1K

BFUNC

VSS

CKE1B

VSS

CS3B_n

CKE1B

ODT1B

CS1B_n

DQ[35:32]

DQS4_t
DQS4_c

DQ[39:36]

DQS13_t

DQS13_c

CKE0B

VSS

CS2B_n

D4

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

CKE0B

ODT0B

CS0B_n

D13

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D13B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D4B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[43:40]

DQS5_t
DQS5_c

DQ[47:44]

DQS14_t

DQS14_c

D5

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D14

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D14B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D5B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[51:48]

DQS6_t
DQS6_c

DQ[55:52]

DQS15_t

DQS15_c

D6

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D15

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D15B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D6B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

DQ[59:56]

DQS7_t
DQS7_c

DQ[63:60]

DQS16_t

DQS16_c

D7

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

DQ [7:4]

DQS1_t
DQS1_c

MDQ [7:4]

MDQS1_c

MDQS1_t

DQ [3:0]

DQS0_t
DQS0_c

MDQ [3:0]

MDQS0_t
MDQS0_c

Data

Buffer

C

K

E

1

C

S

1

_

n

O

D

T

1

D16

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D16B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

D7B

DQS_c

DQS_t

C

K

E

0

C

S

0

_

n

DQ [3:0]

O

D

T

0

ZQ

VSS

C

K

E

1

C

S

1

_

n

O

D

T

1

datasheet

DDR4 SDRAMLoad Reduced DIMM

NOTE:

1) ZQ resistors are 240Ω ±1%. For all other resistor values refer to the appropriate wiring diagram.

2) See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3) TEN pin of SDRAMs is tied to VSS.

4) VDDSPD is also applied to the register. VDD is also applied to the register and the data buffers.

5) DQ stub resistors are 15 Ω ±5%. For all other resistor values refer to the appropriate wiring diagram.

- 13 -

Rev. 1.2

datasheet

DDR4 SDRAMLoad Reduced DIMM

10. ABSOLUTE MAXIMUM RATINGS

10.1 Absolute Maximum DC Ratings

[Table 5] Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3

VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3

VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4

V

NOTE :

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3) VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA

may be equal to or less than 300mV

4) VPP must be equal or greater than VDD/VDDQ at all times.

5) Overshoot area above 1.5 V is specified in section Address, Command and Control Overshoot and Undershoot specifications, Clock Overshoot and Undershoot

Specifications and section Data, Strobe and Mask Overshoot and Undershoot Specifications.

Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5

IN, VOUT

T

Storage Temperature -55 to +100 °C 1,2

STG

11. AC & DC OPERATING CONDITIONS

[Table 6] Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3

NOTE :

1) Under all conditions V

tracks with VDD. AC parameters are measured with VDD and V

2) V

DDQ

3) DC bandwidth is limited to 20MHz.

must be less than or equal to VDD.

DDQ

Min. Typ. Max.

tied together.

DDQ

Rating

Unit NOTE

- 14 -

Rev. 1.2

voltage

V

DD

V

SS

time

datasheet

DDR4 SDRAMLoad Reduced DIMM

12. AC & DC INPUT MEASUREMENT LEVELS

12.1 AC & DC Logic Input Levels for Single-Ended Signals

[Table 7] Single-ended AC & DC Input Levels for Command and Address

Symbol Parameter

VIH.CA(DC75)

VIH.CA(DC65) - -

VIL.CA(DC75)

VIL.CA(DC65) - - VSS

VIH.CA(AC100)

VIH.CA(AC90) - -

VIL.CA(AC100)

VIL.CA(AC90) - - Note 2

VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD - - V 2,3

NOTE :

1) See “Overshoot and Undershoot Specifications” on section.

2) The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3) For reference : approx. VDD/2 ± 12mV.

DC input logic high

DC input logic low

AC input logic high

AC input logic low

DDR4-1600/1866/2133/2400 DDR4-2666/2933

Min. Max. Min. Max.

+ 0.075

V

REFCA

V

VSS

+ 0.1

REF

Note 2

VDD - -

V

+ 0.065

REFCA

V

-0.075

REFCA

Note 2 - -

V

- 0.1

REF

--

V

+ 0.09

REF

--

V

REFCA

V

VDD

Note 2

REF

-0.065

- 0.09

Unit NOTE

V

V

V

V

1

1

12.2 AC and DC Input Measurement Levels: V

The DC-tolerance limits and ac-noise limits for the reference voltages V

function of time. (V

V

(DC) is the linear average of V

REF

Furthermore V

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

stands for V

REF

(t) may temporarily deviate from V

REF

).

REFCA

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7.

REF

(DC) by no more than ± 1% VDD.

REF

Figure 1. Illustration of V

(DC) tolerance and V

REF

is illustrated in Figure 1. It shows a valid reference voltage V

REFCA

Tolerances.

REF

AC-noise limits

REF

REF

(t) as a

REF

.

"V

" shall be understood as V

REF

This clarifies, that DC-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

and voltage effects due to AC-noise on V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

- 15 -

AC-noise. Timing

REF

Rev. 1.2

0.0

tDVAC

V

IH

.DIFF.MIN

half cycle

Differential Input Voltage (CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

V

IL

.DIFF.MAX

V

IL

.DIFF.AC.MAX

(CK_t - CK_c)

datasheet

12.3 AC and DC Logic Input Levels for Differential Signals

12.3.1 Differential Signals Definition

Figure 2. Definition of differential ac-swing and “time above ac-level” t

NOTE:

1) Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2) Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

DDR4 SDRAMLoad Reduced DIMM

DVAC

- 16 -

Rev. 1.2

datasheet

12.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)

[Table 8] Differential AC and DC Input Levels

Symbol Parameter

V

IHdiff

V

ILdiff

V

(AC)

IHdiff

V

(AC)

ILdiff

NOTE :

1) Used to define a differential signal slew-rate.

2) for CK_t - CK_c use V

3) These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

as well as the limitations for overshoot and undershoot.

[Table 9] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c

differential input high +0.150 NOTE 3 TBD NOTE 3 V 1

differential input low NOTE 3 -0.150 NOTE 3 TBD V 1

differential input high ac

differential input low ac NOTE 3

IH.CA/VIL.CA

Slew Rate [V/ns]

> 4.0 120 -

4.0 115 -

3.0 110 -

2.0 105 -

1.8 100 -

1.6 95 -

1.4 90 -

1.2 85 -

1.0 80 -

< 1.0 80 -

(AC) of ADD/CMD and V

2 x (VIH(AC) - V

DDR4 -1600/1866/2133 DDR4 -2400/2666/2933

min max min max

REFCA

)

REF

;

min max

NOTE 3

2 x (VIL(AC) - V

tDVAC [ps] @ |V

2 x (VIH(AC) - V

)

REF

IH/Ldiff

REF

NOTE 3

(DC) max, V

IH.CA

(AC)| = 200mV

DDR4 SDRAMLoad Reduced DIMM

)

NOTE 3 V 2

2 x (VIL(AC) - V

(DC)min) for single-ended signals

IL.CA

REF

unit NOTE

)

V2

- 17 -

Rev. 1.2

VDD or V

DDQ

V

SEH

min

V

DD

/2 or V

DDQ

/2

V

SEL

max

V

SEH

VSS or V

SSQ

V

SEL

CK

time

datasheet

DDR4 SDRAMLoad Reduced DIMM

12.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC)) for ADD/CMD
signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used
for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c.

Figure 3. Single-ended requirement for differential signals.

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with
respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single­ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.

[Table 10] Single-ended Levels for CK_t, CK_c

Symbol Parameter

V

V

NOTE :

1) For CK_t - CK_c use V

2) V

IH

3) These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V

signals as well as the limitations for overshoot and undershoot.

Single-ended high-level for

SEH

Single-ended low-level for

SEL

(AC)/VIL(AC) for ADD/CMD is based on V

IH.CA/VIL.CA

(AC) of ADD/CMD;

CK_t, CK_c

CK_t, CK_c

;

REFCA

DDR4-1600/1866/2133 DDR4-2400/2666/2933

Min Max Min Max

(VDD/2)+0.100 NOTE3 TBD NOTE3 V 1, 2

NOTE3 (VDD/2)-0.100 NOTE3 TBD V 1, 2

(DC) max, V

IH.CA

IL.CA

Unit NOTE

(DC)min) for single-ended

- 18 -

Rev. 1.2

A

AOS1

V

DD

A

AUS

V

SS

Volts

(V)

1 tCK

V

AOSP

A

AOS2

V

AOS

V

AUS

datasheet

DDR4 SDRAMLoad Reduced DIMM

12.3.4 Address, Command and Control Overshoot and Undershoot specifications

[Table 11] AC overshoot/undershoot specification for Address, Command and Control pins

Parameter

Maximum peak amplitude above VAOS VAOSP 0.06 TBD TBD V

Upper boundary of overshoot area AAOS1 VAOS VDD +0.24 TBD TBD V 1

Maximum peak amplitude allowed for undershoot

Maximum overshoot area per 1 tCK above VAOS AAOS2 0.0083 0.0071 0.0062 0.0055 TBD TBD V-ns

Maximum overshoot area per 1 tCK between VDD and
VAOS

Maximum undershoot area per 1 tCK below VSS AAUS 0.2644 0.2265 0.1984 0.1762 TBD TBD V-ns

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

NOTE :

1) The value of VAOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 5.

Sym-

bol

VAUS 0.30 TBD TBD V

AAOS1 0.2550 0.2185 0.1914 0.1699 TBD TBD V-ns

DDR4-

1600

DDR4-

1866

Specification

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

Unit NOTE

Figure 4. Address, Command and Control Overshoot and Undershoot Definition

- 19 -

Rev. 1.2

A

COS1

V

DD

A

CUS

V

SS

Volts

(V)

1 UI

V

COSP

A

COS2

V

COS

V

CUS

datasheet

DDR4 SDRAMLoad Reduced DIMM

12.3.5 Clock Overshoot and Undershoot Specifications

[Table 12] AC overshoot/undershoot specification for Clock

Specification

Parameter Symbol

Maximum peak amplitude above VCOS VCOSP 0.06 TBD TBD V

Upper boundary of overshoot area ADOS1 VCOS VDD +0.24 TBD TBD V 1

Maximum peak amplitude allowed for undershoot VCUS 0.30 TBD TBD V

ACOS2 0.0038 0.0032 0.0028 0.0025 TBD TBD V-ns

Maximum overshoot area per 1 UI above VCOS

Maximum overshoot area per 1 UI between VDD and
VDOS

Maximum undershoot area per 1 UI below VSS ACUS 0.1144 0.0980 0.0858 0.0762 TBD TBD V-ns

NOTE :

1) The value of VCOS matches VDD absolute max as defined in Table 5 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 5.

ACOS1 0.1125 0.0964 0.0844 0.0750 TBD TBD V-ns

DDR4-

1600

(CK_t, CK_c)

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

Unit NOTE

Figure 5. Clock Overshoot and Undershoot Definition

- 20 -

Rev. 1.2

A

DOS1

V

DDQ

A

DUS2

V

SSQ

Volts

(V)

1 UI

V

DOSP

A

DOS2

V

DOS

V

DUSP

A

DUS1

datasheet

DDR4 SDRAMLoad Reduced DIMM

12.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications

[Table 13] AC overshoot/undershoot specification for Data, Strobe and Mask

Specification

Parameter Symbol

Maximum peak amplitude above VDOS VDOSP 0.16 0.16 0.16 0.16 TBD TBD V

Upper boundary of overshoot area ADOS1 VDOS VDDQ + 0.24 TBD TBD V 1

Lower boundary of undershoot area ADUS1 VDUS 0.30 0.30 0.30 0.30 TBD TBD V 2

Maximum peak amplitude below VDUS VDUSP 0.10 0.10 0.10 0.10 TBD TBD V

Maximum overshoot area per 1 UI above VDOS ADOS2 0.0150 0.0129 0.0113 0.0100 TBD TBD V-ns

Maximum overshoot area per 1 UI between
VDDQ and VDOS

Maximum undershoot area per 1 UI between
VSSQ and VDUS1

Maximum undershoot area per 1 UI below VDUS ADUS2 0.0150 0.0129 0.0113 0.0100 TBD TBD V-ns

NOTE :

1) The value of VDOS matches (VIN, VOUT) max as defined in Table 5 Absolute Maximum DC Ratings if VDDQ equals VDDQ max as defined in Table 6 Recommended DC

Operating Conditions. If VDDQ is above the recommended operating conditions, VDOS remains at (VIN, VOUT) max as defined in Table 5.

2) The value of VDUS matches (VIN, VOUT) min as defined in Table 5 Absolute Maximum DC Ratings

ADOS1 0.1050 0.0900 0.0788 0.0700 TBD TBD V-ns

ADUS1 0.1050 0.0900 0.0788 0.0700 TBD TBD V-ns

DDR4-

1600

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

Unit

NOT

E

Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition

- 21 -

Rev. 1.2

Delta TRdiff

Delta TFdiff

V

IHdiffmin

0

V

ILdiffmax

Differential Input Voltage(i,e, CK_t - CK_c)

datasheet

12.4 Slew Rate Definitions

12.4.1 Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.

[Table 14] Differential Input Slew Rate Definition

Description

Differential input slew rate for rising edge (CK_t - CK_c)

Differential input slew rate for falling edge (CK_t - CK_c)

NOTE :

1) The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

Measured

from to

V

ILdiffmax

V

IHdiffmin

V

IHdiffmin

V

ILdiffmax

[V

[V

IHdiffmin

IHdiffmin

DDR4 SDRAMLoad Reduced DIMM

Defined by

- V

ILdiffmax

- V

ILdiffmax

] / DeltaTRdiff

] / DeltaTFdiff

Figure 7. Differential Input Slew Rate Definition for CK_t, CK_c

- 22 -

Rev. 1.2

Delta TRsingle

Delta TFsingle

V

IHCA(AC) Min

V

IHCA(DC) Min

VREFCA(DC)

V

ILCA(DC) Max

V

ILCA(AC) Max

datasheet

12.4.2 Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

DDR4 SDRAMLoad Reduced DIMM

Figure 8. Single-ended Input Slew Rate definition for CMD and ADD

NOTE :

1) Single-ended input slew rate for rising edge = {VIHCA(AC)Min - VILCA(DC)Max} / Delta TR single.

2) Single-ended input slew rate for falling edge = {VIHCA(DC)Min - VILCA(AC)Max} / Delta TF single.

3) Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4) Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.

- 23 -

Rev. 1.2

Vix

CK_t

VDD/2

VSS

VDD

CK_c

Vix

VSEL

VSEH

datasheet

DDR4 SDRAMLoad Reduced DIMM

12.5 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals
(CK_t, CK_c) must meet the requirements in Table 15. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS.

Figure 9. Vix Definition (CK)

[Table 15] Cross Point Voltage for Differential Input Signals (CK)

Symbol Parameter

- Area of VSEH, VSEL

VlX(CK)

Symbol Parameter

VlX(CK)

Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c

- Area of VSEH, VSEL TBD TBD TBD TBD

Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c

VSEL =< VDD/2 -

145mV

-120mV

TBD TBD TBD TBD

min max

min max

DDR4-1600/1866/2133

VDD/2 - 145mV =<

VSEL =< VDD/2 -

100mV

-(VDD/2 - VSEL) +
25mV

DDR4-2400/2666/2933

VDD/2 + 100mV =<

VSEH =< VDD/2 +

145mV

(VSEH - VDD/2) -

25mV

VDD/2 + 145mV =<

VSEH

120mV

- 24 -