Preliminary specification
Supersedes data of 1996 Sep 27
File under Integrated Circuits, IC03
1997 Mar 07
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
FEATURES
• Designed for compact power plugs supplying up to 20 W
• Integrated high-voltage power DMOS FET 625 V/1 A
• Operates from all mains supplies (90 to 280 V AC)
• Major design: current regulation at the primary side
(no opto-coupler, no secondary electronics)
• Low external/peripheral component count
• Combines accurate constant-voltage source (for supply)
and accurate constant-current source (for charging) in
one IC
• Foldback feature
• Requires simple input filter as a result of good EMC
design
• Overshoot protection (output voltage)
GENERAL DESCRIPTION
The TEA1401T is a Self Oscillating Power Supply (SOPS)
controller IC that operates directly from the rectified
universal mains. It is implemented in the BCD power logic
750 V process and includes the high voltage power switch
making an integrated single-switch flyback converter.
Dedicated circuitry for high power efficiency is built-in,
which makes a slim-line electronic power plug concept
possible.
The basic function is a galvanically isolated, combined
current and voltage source. No electronics are required at
the secondary side of the transformer. Implementation of
the TEA1401T renders a simple, small and accurate
battery charger system. The TEA1401T is capable of self
starting directly from the high voltage mains line.
• Protects against under-voltage input, over-current and
over-temperature
• 20-pin SO medium-power package.
QUICK REFERENCE DATA
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
20
I
20
f
sw
I
1
I
17
T
amb
output voltage at pin 20 (DRAIN)20 times−−625V
current in MOS switchpeak value−−1A
operating switching frequency range C
input current at pin 1 (Vin), from the
high input voltage. VAT can supply
from the low voltage auxiliary
winding
= 470 pF5−150kHz
CPFM
VAT< 10 V (peak)−−3mA
> 10 V (peak);
V
AT
−430530µA
fsw= 90 kHz
> 10 V (peak);
V
AT
= 150 kHz
f
sw
−560660µA
average input current at pin 17 (VAT)VAT< 10 V (peak)−−300µA
> 10 V (peak)−−3mA
V
AT
operating ambient temperature−20−+85°C
ORDERING INFORMATION
TYPE
NUMBER
NAMEDESCRIPTIONVERSION
PACKAGE
TEA1401TSO20plastic small outline package; 20 leads; body width 7.5 mmSOT163-1
1997 Mar 072
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
BLOCK DIAGRAM
output
FET turn-off
TIMING
from mains rectifier and filter
in
V
AT
V
in
117V
IC
14313
V
PFM
C
FOLDBACK
hard wired
secondary
stroke
SUPPLY
T1
auxiliary
PROTECTION
TEMPERATURE
POR
D-TYPE
FLIP-FLOP
RESET
D
winding
temp
over
temperature
foldback
Q
clock
max
TEA1401T
T1
primary
winding
&
TP
SINGLE-SHOT
TR
1
DRAIN
20
on
Q
S
maximum
on time
T1
secondary
1
25 µA
TRACK-
winding
Q
R
AND-
HOLD
y
C
TOP
I
REGULATOR
LIMITER
MINIMUM
4 SOURCE
MBH570
BLANKING
LEADING EDGE
I
U
in
in
2.5 µA
90 mV
130 µA
1.2 V
out
out
n.c.GND
handbook, full pagewidth
Fig.1 Block diagram.
I
82, 18, 195, 6, 15, 16
C
V
low voltage
over voltage
ref
J
ref
I
gap
V
BAND-GAP
VOLTAGE SETTING
12
V
R
mains
10
C
ref
9
R
1997 Mar 073
ref/3
J
ref
J
OUT
R
COMPENSATION
PEAK
I
CORRECTION
I
I
R
=
m
g
I
V
OUT
1/6
11
OUT
G
G
COMPENSATION
CURRENT
SETTING
7
I
R
PEAK
DETECTOR
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
PINNING
SYMBOLPINDESCRIPTION
V
in
n.c.2not connected
C
PFM
SOURCE4source of internal MOS switch
GND15ground 1
GND26ground 2
R
I
C
I
R
ref
C
V
G
OUT
R
V
FOLDBACK13enabling of the foldback feature in
V
IC
GND315ground 3
GND416ground 4
V
AT
n.c.18not connected
n.c.19not connected
DRAIN20drain of internal MOS switch
1input for rectified and filtered mains
voltage for initial powering
3frequency range setting for the
pulse frequency modulation
7setting of nominal output current
8frequency compensation of
current control loop
9setting of reference current
10frequency compensation of voltage
control loop
11nulling of the output conductance
of the current source function
12setting of the nominal output
voltage
the output characteristic
14buffering of internal supply voltage
17input for voltage and power from
auxiliary winding for timing and
powering
handbook, halfpage
V
1
in
n.c.
2
C
3
PFM
SOURCE
GND1
GND2
R
C
R
C
ref
I
I
V
4
5
6
7
8
9
10
TEA1401T
Fig.2 Pin configuration.
MBH571
DRAIN
20
n.c.
19
n.c.
18
V
17
GND4
16
15
GND3
V
14
FOLDBACK
13
R
12
G
11
AT
IC
V
OUT
1997 Mar 074
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
FUNCTIONAL DESCRIPTION
The TEA1401T is the heart of a compact flyback DC-to-DC
converter, with the IC placed at the primary side.
An auxiliary primary winding of the transformer is used for
indirect feedback to control the isolated output. This extra
winding also powers the device.
Control of the converted power is carried out by current
mode control and Pulse Frequency Modulation (PFM), as
illustrated in Fig.1. The primary current is sensed by a
comparator. The frequency is determined by the maximum
of the transformer demagnetizing time and the time of the
voltage controlled monostable multivibrator (single-shot).
The TEA1401T senses signals at the primary side of the
transformer to reconstruct the current and voltage which
are present at the secondary side. Comparison of these
reconstructions with the internal reference leads to
adaptation of the turn-off current level for the primary
switch and also to adaptation of the single-shot time.
Current control (see Fig.3)
The current through the main switch is measured by the
peak detector shown in Fig.1. The timing block generates
a signal ‘secondary stroke’ which is logic 1 when the
voltage of the auxiliary winding is negative.
The measured peak current, multiplied by the ratio of the
resistors connected to pins 4 (SOURCE) and 7 (R
), is
I
integrated by a capacitor during the secondary stroke.
In this way a reconstruction is made of the secondary
charge transfer. The charge estimation Q-pulse’
(see Fig.3) is drawn from the capacitor at pin 8 (CI) for
each pulse. Also this capacitor, the charge error memory,
is continuously charged with the reference current. In this
way the real (reconstructed) current is compared with the
reference yielding the voltage VCI at pin 8. The VCI level
provides the turn-off current level for the main switch and
the single-shot time.
Input from the voltage part of the loop is used to improve
the current reconstruction, resulting in a lower output
conductance of the complete converter. In the block
diagram this is denoted as ‘G
The block ‘I
correction’ is able to increase the output
PEAK
compensation’.
OUT
from the peak detector to improve line regulation.
Voltage control
The voltage from the auxiliary winding is sensed as a
measure of the secondary voltage. During the secondary
stroke the auxiliary winding delivers a negative voltage.
This voltage is converted into a current by an external
resistor at the R
pin between the transformer winding and
V
virtual ground. This current is compared with a reference
current.
The difference between the reconstructed voltage and the
reference is integrated during the secondary stroke by a
capacitor on the C
pin. The voltage on the CV pin is
V
transferred, via a ‘track-and-hold’ circuit, to the connection
point of the current and the voltage loop.
The ‘track-and-hold’ output provides the turn-off current
level for the main switch and the single-shot time.
The ‘track-and-hold’ circuit itself is present for loop
stability.
Input from the current part of the loop is used to improve
the voltage reconstruction, resulting in lower output
impedance of the complete converter (analog to the
current control). In the block diagram this is denoted as
‘R
compensation’.
OUT
Combined control
The two loops, I loop and V loop, each request their own
turn-off current level for the main switch and single-shot
time. The block ‘minimum’ in the block diagram outputs the
lowest value of the two, preventing the output voltage or
current from exceeding its nominal value. The output
characteristics of the power plug are displayed in Fig.4
(with enabled foldback option).
Optional foldback (see Fig.4)
The optional foldback feature of the TEA1401T is
performed by sensing the voltage of the auxiliary winding
at the end of the flyback stroke. It is actually not a voltage,
but the current through pin 12 (RV) that is measured. When
this voltage is low, the reference current in the current
control loop is set to the low level J
ref
/3.
The steep foldback enables a turn-down of the converter
by short-circuiting the output on the secondary side, for
example by a switch-transistor.
1997 Mar 075
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
Overshoot protection
Sensing the voltage during the previously mentioned
flyback stroke is also used to signal a voltage overshoot.
A voltage overshoot will delay and minimize the next active
stroke. This is achieved by discharging the capacitor in the
‘track-and-hold’ circuit (see Fig.1). In this way the power
level of the converter is turned down to its minimum
immediately in case of a voltage overshoot.
Minimum output power
Under no-load condition an additional external pre-load
resistor (or Zener diode) is necessary to keep the output
voltage at its nominal value (or at the Zener diode voltage).
This is due to the fact that under no-load condition and also
at voltage overshoot the converter will keep operating
instead of being switched off. Although the converter then
will operate with a short active stroke and a low frequency,
energy is still being converted to the output. To prevent
excessive output voltage this energy has to be dissipated.
The advantage of a pre-load resistor over a Zener diode is
that the converter will stay in regulation, maintaining its fast
response to load variations.
Duty cycle control
The momentary power level required by the I/V control
loop is achieved by controlling the duty cycle of the
converter by two actions. First the peak value of the
primary current is controlled using a cycle-by-cycle current
control. Secondly the pulse frequency is modulated. There
is a broad region in which both regulation principles are
active simultaneously. Both controls have a minimum and
a maximum value which are set by the resistor on the
SOURCE pin and the capacitor on the C
PFM
pin.
At a high power level the transformer determines the
frequency. This mode of operation is called Self Oscillating
Power Supply (SOPS), and provides maximum efficiency
(for a non-continuous conducting flyback converter).
In SOPS the next primary stroke is started right after the
previous secondary stroke has ended. Timing information
is collected from the auxiliary winding.
The SOPS frequency will increase when the power level
decreases. The frequency however is limited by the PFM
controller (single-shot). When the PFM controller takes
over, the frequency will be proportional to the required
power level. Thus the frequency is reduced when the
power level decreases. In PFM there is a variable dead
time after the secondary stroke. The next primary stroke is
started after the single-shot time has ended.
Supply
Initially the IC is powered by a high DC input voltage at
pin 1 (V
). In operation the auxiliary winding takes over.
in
In the event that the auxiliary winding delivers insufficient
power for the internal circuitry of the IC, this deficit is
supplemented again via pin 1 (Vin).
The supply voltage for the internal circuitry is buffered with
an external capacitor at pin 14 (VIC). When the auxiliary
winding powers the IC, energy is stored during the active
stroke. The rest of the time energy is supplied by the buffer
capacitor.
Protections
The IC has a cycle-by-cycle current regulation, with a
built-in setting for the absolute maximum voltage across
the current sense resistor. Also a maximum time is set for
the duration of the active stroke. A provision for
temperature shut down has been implemented.
SOPS and PFM
The switching frequency f
is set by the transformer
sw
demagnetizing time or the frequency control block within
the IC (block ‘single-shot’ in Fig.1).
1997 Mar 076
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
Q
handbook, halfpage
I
primary x n
pulse
I
secondary
Q
pulse'
V
handbook, halfpage
OUT
(V)
V
nominal
t
MBH575
V
auxiliary
(−V
secondary
)
t
MBH580
Fig.3 Reconstruction of secondary charge transfer.
0
I
FOLDBACK
I
nominal
Fig.4 V/I ideal characteristics.
I
OUT
(A)
1997 Mar 077
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). All voltages are measured with respect to ground;
positive currents flow into the chip; pins 7, 9, 11 and 12 are not allowed to be voltage driven. The voltage ratings are
valid provided other ratings are not being violated; current ratings are valid provided the maximum power rating is not
violated.
discharge resistance to groundV
minimum charge currentVCV=VCI=0V−2.5−µA
maximum charge currentVCV=VCI=4V−130−µA
fixed charge currentactive stroke−25−µA
transfer from pin CI to pin C
transfer from pin CV to pin C
PFM
PFM
high switching voltage level at
pin C
PFM
low switching voltage level at
pin C
PFM
maximum on-time t
voltage level at pin C
on(max)
PFM
switching
frequency spread of the internal
V
ton(max)
;
---------------------- I
charge(fix)
G
transferCV
------------------------- V
sw(high)
G
oscillator;;
spread of t
transferCI
-----------------------V
sw(high)
on(max)
= 1.0 V0.30.60.9kΩ
CPFM
VCI= 2.1 to 3.1 V−−104−µA/V
VCV= 2.1 to 3.1 V−−104−µA/V
−1.0−V
DC at pin C
PFM
−0.17−V
−0.54−V
V
CI=VCV
VCI=VCV=4V;
V
SOURCE
= 2.1 to 3.1 V 93104115µA/V
192225V/mA
<1V
2
SOPS
V
demag
Current regulation
V
i(pkc)
V
i(pkc)(slope)
V
pkc(offset)
I
transfer(RI-CI)
I
transfer(GOUT-CI)
I
PEAKcor
I
chain(CI)
I
ctrl(error)
demagnetization recognition voltage
−250−130−10mV
level
V
-I converter input voltage0.6−1.4V
PEAK
V
-I converter input voltage slope0.1−1.0V/µs
PEAK
V
-I converter systematic offset−−13−mV
PEAK
RIto CI current transferI
G
to CI current transferIRI=0−0.17−A/A
OUT
current through sense capacitor in
block ‘I
correction’ (see Fig.1);
PEAK
dV
SOURCE
-------------------------- dt
GOUT
under test conditions: in
0.1 V/µs>
=0−−0.99 −A/A
71013µA
lasting active stroke
sunk by pin FOLDBACK
CI chain error current−3.3−1.0+1.3µA
current control total measured error−5−+5%
1997 Mar 0710
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Voltage regulation
I
transfer(RV-CV)
V
thres(RI)
g
m(ROUT)
I
chain(CV)
V
ctrl(error)
Current foldback; FOLDBACK (pin 13) connected to V
I
RV/IRref
I
CI(foldback)/ICI(normal)
Voltage overshoot
IRV/I
Rref
V
4(overshoot)
I
charge(overshoot)
References
V
ref
I
transfer(Rref-CI)
I
transfer(Rref-CV)
Output stage
I
LO
V
DRAIN(cont)
V
DRAIN(lim)
∆V
DRAIN-SOURCE
t
f
RVto CV current transferVRI< 0.5 V−−1.00 −A/A
R
converter voltage threshold at
OUT
pin R
I
R
converter transconductance
OUT
ICV/V
RI
VRI> 0.7 V−4.4−µA/V
CV chain error currentICV measurement,
−0.65−V
−1.20+1.2µA
analogue to that of
I
chain(CI)
total error of voltage control loop in IC−4−+4%
(pin 14)
IC
current ratio discrimination level0.050.10.2A/A
current ratio0.260.330.4A/A
current ratio discrimination level1.11.21.3A/A
peak voltage at pin 4at overshoot;
ton>t
on(min)
C
charge currentat overshoot;
PFM
V
=1V
CPFM
R
reference voltage1.241.281.32V
ref
R
to CI current transfer−0.99−A/A
ref
R
to CV current transfer−0.99−A/A
ref
DRAIN output leakage currentV
= 550 V−−100µA
DRAIN
7595120mV
−2.5−µA
DRAIN output voltagecontinuous0−550V
DRAIN output voltage limit20 times625−−V
DRAIN-SOURCE voltage dropT
DRAIN fall timeVin= 300 V;
=25°C;
amb
I
DRAIN
= 125 °C;
T
amb
I
DRAIN
−−6V
= 500 mA
−−11V
= 500 mA
−100−ns
no external capacitor at
pin DRAIN
Temperature protection
T
prot(max)
T
prot(hyst)
maximum temperature threshold132139146°C
hysteresis temperature−±1−°C
1997 Mar 0711
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
OUTPUT CHARACTERISTICS OF COMPLETE
POWER PLUG
Output power
Maximum switching frequency is approximately 150 kHz.
Internal MOS maximum switch current is 0.5 to 1 A.
Maximum handled power with universal mains is
approximately 10 W.
Accuracy of current regulation
The accuracy of the IC itself is ±5%. Accuracy of the
complete converter is approximately ±7%, depending on
the transformer and other components.
Accuracy of voltage regulation
The voltage loop inside the IC has an accuracy of ±4%.
Accuracy of the complete converter is approximately ±7%.
Voltage overshoot
When voltage overshoot is detected (during the secondary
stroke), the IC first has to wait until this stroke is finished in
the normal way. After that the power level of the converter
is set to the minimum level within one cycle.
Voltage overshoot is triggered at 20% above nominal
output voltage. If at the moment that overshoot is detected,
the transformer still contains energy; this energy can
cause some further increase of the output voltage.
Efficiency
An efficiency of 72 to 75% at maximum output power can
be achieved for a complete 8 W converter designed for
universal mains.
Ripple
The magnitude of the ripple in output voltage is determined
by the duty cycle of the converter, the output current level
and the value and Electrical Series Resistance (ESR) of
the output capacitor.
A minimal ripple is obtained in a system designed on a
maximum duty cycle of 50% under normal operating
conditions and a minimized dead time.
Ripple is inversely proportional to input and output
voltages.
INPUT CHARACTERISTICS OF COMPLETE
POWER PLUG
Input voltage
The input voltage range comprises the universal AC-mains
(90 to 280 V). The input transient voltage must be filtered
to a maximum of 450 V.
In case of a pre-load resistor across the output,
the converter keeps the output voltage under static
conditions on its nominal value. Voltage overshoot will only
be a dynamic phenomenon in this situation. When only a
Zener diode is applied, the Zener voltage will appear at the
output continuously under no-load conditions.
1997 Mar 0712
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
APPLICATION INFORMATION
A converter with the TEA1401T consists of an input filter,
a transformer with a third winding (auxiliary), a secondary
diode with a capacitor plus other external components as
illustrated in Fig.5. The load (user) determines the
operating mode of the power plug, current or voltage
source.
The capacitor at VIC (pin 14) buffers the internal supply
voltage of the IC which is powered via Vin and/or VAT.
A sense resistor converts the primary current into a
voltage at SOURCE (pin 4). The voltage of the auxiliary
winding is converted into a current through resistor R
RV
and fed to pin RV.
Nominal current and voltage are set by resistors RRI and
RRV. Output conductance of the current is nullified by
resistor R
reference current by resistor R
. The band-gap voltage is converted into a
RGOUT
. Capacitor C
Rref
CPFM
determines the frequency in non-SOPS mode.
There are two loop capacitors, one for current control (CI),
and the other for voltage control (CV). The impedance at
CV (pin 10) can be made more complex, if required for
stability.
The secondary diode also protects the power plug against
a short-circuited output (during the primary stroke), and
must therefore be placed inside the power plug cabinet.
A pre-load resistor or a Zener diode is required to handle
an open output which will cause an excessively high output
voltage. This is because the power plug continues
operating, provided it is connected to the mains, and thus
continuously converts energy to the secondary side, even
though it is a low, predefined level.
If a Zener diode is used, the Zener voltage must be
selected with care, because the over-voltage protection of
the IC should not be blocked. If the Zener diode voltage is
too close to the nominal output voltage of the converter no
voltage overshoot will be detected by the IC, causing
increased dissipation in the Zener during switching of the
load.
A complete diagram with preliminary component values is
shown in Fig.6. More detailed information can be found in
“Application Note AN96096”
the
.
1997 Mar 0713
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
MBH573
OUT
V
PLUG
POWER
USER
OUT
V
DRAIN
in
V
USER
y
C
RV
R
GOUT
R
OUT
V
AT
R
V
17
20
1
G
12
11
TEA1401T
4
9
3
7
10
8
14
SOURCE
ref
R
PFM
C
I
R
V
C
I
C
IC
V
R
R
CPFM
C
R
C
C
C
sense
Rref
RI
CV
CI
VIC
handbook, full pagewidth
Fig.5 Power plug with TEA1401T.
mains
1997 Mar 0714
13
FOLDBACK
5, 6,
15, 16
hard
GND
wired
4
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
USER
OUT
Z2
(1)
L2
V
BYD77B
D2
MBH574
C1
L3
y
C
RV
(1%)
R
240 kΩ
GOUT
R
L4
(1%)
100 kΩ
2.2 nF
Z1
450 V (also transient)
<
DC
V
L1
mains filter
R1
mains
D1
BYD33J
BZD27C150
f2
C
f1
C
rectifier bridge
800 V at 0.5 A
DRAIN
in
V
V
AT
R
V
17
20
1
FOLDBACK
OUT
G
12
11
TEA1401T
5, 6,
13
SOURCE
4
R
9
C
3
R
7
C
10
C
8
V
14
GND
15, 16
hard
wired
ref
PFM
I
V
I
IC
sense
(1%)
R
2.2 Ω
Rref
(1%)
R
30 kΩ
CPFM
(5%)
470 pF
C
RI
10
kΩ
R
(1%)
CV
10 nF
C
(10%)
CI
C
(10%)
8.2 nF
VIC
1 µF
(10%)
C
= 6.8 µF 385 V 10%.
4
f2
=C
f1
handbook, full pagewidth
Fig.6 Power plug with TEA1401T; completed circuit diagram.
(1) Optional short-circuit provision based on FOLDBACK feature.
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
PACKAGE OUTLINE
SO20: plastic small outline package; 20 leads; body width 7.5 mm
D
c
y
Z
20
pin 1 index
1
e
11
A
2
10
w M
b
p
SOT163-1
E
H
E
Q
A
1
L
p
L
detail X
(A )
A
X
v M
A
A
3
θ
0510 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
OUTLINE
VERSION
SOT163-1
A
max.
2.65
0.10
A
1
0.30
0.10
0.012
0.004
A2A
2.45
2.25
0.096
0.089
IEC JEDEC EIAJ
075E04 MS-013AC
0.25
0.01
b
3
p
0.49
0.32
0.36
0.23
0.019
0.013
0.014
0.009
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
(1)E(1)(1)
cD
13.0
7.6
7.4
0.30
0.29
1.27
0.050
12.6
0.51
0.49
REFERENCES
1997 Mar 0716
eHELLpQ
10.65
10.00
0.42
0.39
1.4
0.055
1.1
0.4
0.043
0.016
1.1
1.0
0.043
0.039
PROJECTION
0.25
0.250.1
0.01
0.01
EUROPEAN
ywvθ
Z
0.9
0.4
0.035
0.004
0.016
ISSUE DATE
92-11-17
95-01-24
o
8
o
0
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
(order code 9398 652 90011).
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Mar 0717
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Mar 0718
Philips SemiconductorsPreliminary specification
Power plug for the universal mainsTEA1401T
NOTES
1997 Mar 0719
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands417027/1200/02/pp20 Date of release: 1997 Mar 07Document order number: 9397 750 01503
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.