Philips NE56605-42 Technical data

INTEGRATED CIRCUITS

NE56605-42

System reset with built-in watchdog timer

Product data

2001 Aug 22

Supersedes data of 2001 Apr 24

File under Integrated Circuits, Standard Analog

P s

on o s

Philips Semiconductors	Product data
System reset with built-in watchdog timer	NE56605-42

GENERAL DESCRIPTION

The NE56605-42 is designed to generate a reset signal, at a threshold voltage of 4.2 V, for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. The NE56605-42 has a built-in Watchdog Timer to monitor the microprocessor and ensure it is operating properly. Any abnormal system operations due to microprocessor malfunctions are terminated by the watchdog's generating a system reset. The NE56605-42 has a watchdog monitoring time of 10 ms (typical).

The NE56605-42 is offered in the SO8 surface mount package.

FEATURES

•Both positive and negative logic reset output signals are available

•Accurate threshold detection

•Internal power-on reset delay

•Internal watchdog timer programmable with external capacitor

•Watchdog monitoring time of 10 ms

•Reset assertion with VCC down to 0.8 VDC (typical)

•Few external components required.

APPLICATIONS

•Microcomputer systems

•Logic systems.

SIMPLIFIED SYSTEM DIAGRAM

VCC

	5		6	WDC
	NE56605-42						LOGIC
	R					RESET	SYSTEM
VS	7				8		RESET
				RESET
				GENERATOR		RESET
	R	VREF			2		RESET
C			PROGRAMMABLE		3	CLK	CLK
			WATCHDOG TIMER				GND
	4	GND		1 CT
							SL01282

Figure 1. Simplified system diagram.

ORDERING INFORMATION

	TYPE NUMBER	PACKAGE		TEMPERATURE
		NAME	DESCRIPTION	RANGE
	NE56605-42D	SO8	plastic small outline package; 8 leads; body width 3.9 mm	±20 to +70 °C

2001 Aug 22

2

853±2251 26949

Philips Semiconductors	Product data
System reset with built-in watchdog timer	NE56605-42

Part number marking

PIN CONFIGURATION

The package is marked with a four letter code in the first line to the

TOP VIEW

right of the logo. The first three letters designate the product. The

fourth letter, represented by `x', is a date tracking code. The

CT

1

8

RESET

remaining two or three lines of characters are internal manufacturing

RESET

2

7

VS

codes.

SO8

CLK

3

6

WDC

GND

4

5

VCC

8

7

6

5

SL01279

Figure 2.

Pin configuration.

1

2

3

4

Part number	Marking
NE56605-42	A A E x

PIN DESCRIPTION

PIN		SYMBOL		DESCRIPTION
1		CT		tWDM, tWDR, tPR adjustment pin.
				tWDM, tWDR, tPR times are dependent on the value of external CT capacitor used. See Figure 18 (Timing
				Diagram) for definition of tWDM, tWDR, tPR times.
2		RESET		Reset HIGH output pin.
3		CLK		Clock input pin from logic system for watchdog timer.
4		GND		Circuit ground.
5		VCC		Power supply pin for circuit.
6		WDC		Watchdog timer control pin.
				The watchdog timer is enabled when this pin is unconnected, and disabled when this pin is connected to
				ground.
7		VS		Detection threshold adjustment pin.
				The detection threshold can be increased by connecting this pin to VCC with a pull-up resistor. The detection
				threshold can be decreased by connecting this pin to ground with a pull-down resistor.
8				Reset LOW output pin.
		RESET

MAXIMUM RATINGS

SYMBOL			PARAMETER	MIN.	MAX.	UNIT
VCC	Power supply voltage			±0.3	10	V
VS	VS pin voltage			±0.3	10	V
VCLK	CLK pin voltage			±0.3	10	V
VOH	RESET and		pin voltage	±0.3	10	V
		RESET
Toper	Operating temperature			±20	70	°C
Tstg	Storage temperature			±40	125	°C
P	Power dissipation			±	250	mW

2001 Aug 22

3

Philips Semiconductors	Product data
System reset with built-in watchdog timer	NE56605-42

DC ELECTRICAL CHARACTERISTICS

Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified.

See Figure 23 (Test circuit 1) for test configuration used for DC parameters.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

ICC

Supply current during watchdog timer

±

0.7

1.0

mA

operation

VSL

Reset detection threshold

VS = open; VCC = falling

4.05

4.20

4.35

V

VSH

Reset detection threshold

VS = open; VCC = rising

4.15

4.30

4.45

V

VS/ Tamb

Temperature coefficient of reset threshold

±20 °C ≤ Tamb ≤ 70 °C

±

±0.01

±

%/°C

Vhys

Reset threshold hysteresis

VHYS = VSH (rising VCC) ± VSL

50

100

150

mV

(falling VCC)

VTH

CLK input threshold

0.8

1.2

2.0

V

IIH

CLK input current, HIGH-level

VCLK = 5.0 V

±

0

1.0

μA

IIL

CLK input current, LOW-level

VCLK = 0 V

±20

±10

±3.0

μA

VOH1

Output voltage, HIGH-level

I

= ±5.0 μA; VS = open

4.5

4.8

±

V

RESET

VOH2

IRESET current = ±5.0 mA; VS = 0 V

4.5

4.8

±

V

VOL1

Output voltage, LOW-level

I

= 3.0 mA; VS = 0 V

±

0.2

0.4

V

RESET

VOL2

I

= 10 mA; VS = 0 V

±

0.3

0.5

V

RESET

VOL3

IRESET = 0.5 mA; VS = open

±

0.2

0.4

V

VOL4

IRESET = 1.0 mA; VS = open

±

0.3

0.5

V

IOL1

Output sink current

V

= 1.0 V; VS = 0 V

10

16

±

mA

RESET

IOL2

VRESET = 1.0 V; VS = open

1.0

2.0

±

mA

ICT1

CT charge current

VCT = 1.0 V; WDC = open during

±8

±12

±24

μA

watchdog operation

ICT2

VCT = 1.0 V;

±0.8

±1.2

±2.4

μA

during power-on reset operation

VCCL1

Supply voltage to assert reset operation

V

= 0.4 V;

±

0.8

1.0

V

RESET

RESET

current = 0.2 mA

VCCL2

VRESET = VCC ± 0.1 V;

±

0.8

1.0

V

1 MΩ resistor (pin 2 to GND)

2001 Aug 22

4

Philips Semiconductors	Product data
System reset with built-in watchdog timer	NE56605-42

AC ELECTRICAL CHARACTERISTICS

Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified.

See Figure 24 (Test circuit 2) for test configuration used for AC parameters.

SYMBOL		PARAMETER				CONDITIONS	MIN.	TYP.	MAX.	UNIT
tP1	Minimum power supply pulse width for			4.0 V ≤ negative-going VCC pulse ≤ 5.0 V			8.0	±	±	ms
	detection
tCLKW	Clock input pulse width						3.0	±	±	ms
tCLK	Clock input cycle						20	±	±	ms
tWDM	Watchdog monitoring time (Notes 1, 6)				CT = 0.1 mF; RCT = open		5.0	10	15	ms
tWDR	Watchdog reset time (Notes 2, 6)					CT = 0.1 mF	1.0	2.0	3.0	ms
tPR	Power-on reset delay time (Notes 3, 6)				VCC = rising from 0 V; CT = 0.1 mF		50	100	150	ms
tPD1	RESET,		propagation delay time			RL1 = 2.2 kW; CL1 = 100 pF	±	2.0	10	ms
		RESET			RESET:
	(Note 4)
tPD2					RESET: RL2 = 10 kW; CL2 = 20 pF		±	3.0	10	ms
tR1	RESET,		rise time (Note 5)			RL1 = 2.2 kW; CL1 = 100 pF	±	1.0	1.5	ms
		RESET			RESET:
tR2					RESET: RL2 = 10 kW; CL2 = 20 pF		±	1.0	1.5	ms
tF1	RESET,		fall time (Note 5)			RL1 = 2.2 kW; CL1 = 100 pF	±	0.1	0.5	ms
		RESET			RESET:
tF2					RESET: RL2 = 10 kW; CL2 = 20 pF		±	0.5	1.0	ms

NOTES:

1.`Watchdog monitoring time' is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse occurs (see Figure 18). A reset signal is output if a clock pulse is not input during this time.

2.`Watchdog reset time' is the reset pulse width (see Figure 18).

3.`Power-on reset delay time' is the duration measured from the time VCC exceeds the upper detection threshold (VSH) and power-on reset release is experienced (RESET output HIGH; RESET output LOW).

4.`RESET, RESET propagation delay time' is the duration from when the supply voltage sags below the lower detection threshold (VSL) and reset occurs (RESET output LOW, RESET output HIGH).

5.RESET, RESET rise and fall times are measured at 10% and 90% output levels.

6.Watchdog monitoring time (tWDM), watchdog reset time (tWDR), and power-on reset delay time (tPR) during power-on can be modified by varying the CT capacitance. The times can be approximated by applying the following formula. The recommended range for CT is 0.001 mF to 10 mF.

Formula 1. Calculation for approximate tPR, tWDM, and tWDR values:

tPR (ms) ≈ 1000 × CT (mF)

tWDM (ms) ≈ 100 × CT (mF)

tWDR (ms) ≈ 20 × CT (mF)

Example: When CT = 0.1 mF and WDC = open:

tPR ≈ 100 ms tWDM ≈ 10 ms tWDR ≈ 2.0 ms

2001 Aug 22

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