Philips 74HCT20D, 74HCT20U, 74HCT20N, 74HCT20DB, 74HC20N Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT20
Dual 4-input NAND gate
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Dual 4-input NAND gate |
74HC/HCT20 |
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FEATURES
·Output capability: standard
·ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
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propagation delay nA, nB, nC, nD to nY |
CL = 15 pF; VCC = 5 V |
8 |
13 |
ns |
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CI |
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input capacitance |
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3.5 |
3.5 |
pF |
CPD |
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power dissipation capacitance per package |
notes 1 and 2 |
22 |
17 |
pF |
Notes |
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1. CPD is used to determine the dynamic power dissipation (PD in mW): |
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PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where: |
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fi |
= input frequency in MHz |
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fo |
= output frequency in MHz |
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CL |
= output load capacitance in pF |
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VCC = supply voltage in V |
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å (CL ´ VCC2 ´ fo) = sum of outputs |
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2. For HC |
the condition is VI = GND to VCC |
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For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
2 |
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