For PNP test circuit, reverse all polarities and D1.
Figure 2. Switching Times Test Circuit
V
CC
+30 V
R
C
R
B
51
D
1
-4 V
MUST BE FAST RECOVERY TYPE, e.g.:
D
1
1N5825 USED ABOVE I
MSD6100 USED BELOW I
≈ 100 mA
B
≈ 100 mA
B
3.0
2.0
1.0
SCOPE
0.7
0.5
0.3
0.2
t, TIME (s)µ
0.1
0.07
0.05
0.03
0.2
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2
T
= 25°C
J
I
= 10
C/IB
V
= 30 V
CE
t
r
td @ V
BE(off)
= 5.0 V
2N5631
2N6031
0.30.5 0.7 1.02.0 3.07.020
5.010
IC, COLLECTOR CURRENT (AMP)
Figure 3. Turn–On Time
1.0
0.5
2N5631 2N6031
D = 0.5
0.2
0.1
0.05
RESISTANCE (NORMALIZED)
0.02
r(t), EFFECTIVE TRANSIENT THERMAL
0.01
0.02
20
10
7.0
5.0
3.0
2.0
1.0
0.7
CURVES APPLY BELOW
, COLLECTOR CURRENT (AMP)
0.5
C
I
0.3
0.2
2.0
0.2
0.1
0.05
0.02
SINGLE PULSE
0.05
T
= 200°C
J
SECOND BREAKDOWN LIMITED
BONDING WIRE LIMITED
THERMALLY LIMITED @ T
RATED V
CEO
3.05.0 7.0 10203050200
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0.01
0.10.20.55.010205010020050020001000
= 25°C
C
1.0ms
0.5ms
5.0ms
dc
2N5631, 2N6031
1.02.0
t, TIME (ms)
Figure 4. Thermal Response
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
limits of the transistor that must be observed for reliable
50ms
operation, i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
200C. T
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
100
70
limitations imposed by second breakdown.
P
θJC(t) = r(t) θ
θJC = 0.875°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
J(pk)
- TC = P
JC
(pk) θJC
1
(t)
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
There are two limitations on the power handling ability of
– V
C
CE
The data of Figure 5 is based on T
may be calculated from the data in
J(pk)
= 200C; TC is
J(pk)
J(pk)
Figure 5. Active–Region Safe Operating Area
NPN
2N5631
5.0
T
J
I
3.0
2.0
1.0
0.7
0.5
0.2
0.30.7 1.02.07.0 1020
0.53.0
IC, COLLECTOR CURRENT (AMP)
t
s
t
f
C/IB
I
B1
VCE = 30 V
5.0
= 25°C
= 10
= I
B2
Figure 6. Turn–Off Time
t, TIME (s)µ
PNP
2N6031
4.0
3.0
2.0
1.0
0.6
0.4
0.3
0.2
0.2
0.53.0
0.30.7 1.02.07.0 1020
I
, COLLECTOR CURRENT (AMP)
C
t
s
t
f
5.0
T
= 25°C
J
I
= I
B1
B2
IC/IB = 10
V
= 30 V
CE
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3
2N5631 2N6031
NPN
2N5631
1000
700
500
300
200
C, CAPACITANCE (pF)
100
0.2
500
300
200
100
70
50
VR, REVERSE VOLTAGE (VOLTS)
T
= 150°C
J
25°C
-55°C
PNP
2N6031
2000
T
= 25°C
J
T
= 25°C
J
1000
C
ib
700
500
C
ib
C, CAPACITANCE (pF)
C
ob
5.01020501002000.51.02.0
300
200
0.25.0102050100 2000.51.02.0
, REVERSE VOLTAGE (VOLTS)
V
R
C
ob
Figure 7. Capacitance
500
T
= +150°C
VCE = 2.0 V
VCE = 10 V
300
200
100
70
50
J
+25°C
-55°C
VCE = 2.0 V
VCE = 10 V
30
, DC CURRENT GAIN
20
FE
h
10
7.0
5.0
0.30.5 0.7 1.02.0 3.05.020
0.2
, COLLECTOR CURRENT (AMP)
I
C
2.0
1.6
1.2
IC = 4.0 A
8.0 A16 A
0.8
0.4
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
0
0.07 0.10.2 0.30.5 0.7 1.02.05.0
0.05
, BASE CURRENT (AMP)
I
B
30
, DC CURRENT GAIN
20
FE
h
10
7.0
10
5.0
0.2
0.30.5 0.7 1.02.0 3.05.020
Figure 8. DC Current Gain
2.0
T
= 25°C
J
1.6
1.2
IC = 4.0 A8.0 A16 A
0.8
0.4
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
3.0
0.0500.07 0.10.2 0.30.5 0.7 1.02.05.0
Figure 9. Collector Saturation Region
, COLLECTOR CURRENT (AMP)
I
C
, BASE CURRENT (AMP)
I
B
10
T
= 25°C
J
3.0
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4
2N5631 2N6031
PACKAGE DIMENSIONS
CASE 1–07
TO–204AA (TO–3)
ISSUE Z
A
N
C
E
D
2 PL
0.13 (0.005)Y
U
V
H
L
2
1
G
–T–
K
M
–Y–
B
T
SEATING
PLANE
M
Q
M
–Q–
0.13 (0.005)T
M
M
Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO-204AA OUTLINE SHALL APPLY.
DIM MINMAXMINMAX
A1.550 REF39.37 REF
B--- 1.050--- 26.67
C 0.250 0.3356.358.51
D 0.038 0.0430.971.09
E 0.055 0.0701.401.77
G0.430 BSC10.92 BSC
H0.215 BSC5.46 BSC
K 0.440 0.480 11.18 12.19
L0.665 BSC16.89 BSC
N--- 0.830--- 21.08
Q 0.151 0.1653.844.19
U1.187 BSC30.15 BSC
V 0.131 0.1883.334.77
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
MILLIMETERSINCHES
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5
Notes
2N5631 2N6031
http://onsemi.com
6
Notes
2N5631 2N6031
http://onsemi.com
7
2N5631 2N6031
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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2N5631/D
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