COMPONENTS IDENTIFIED BY MARK ON THE
SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE
CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK.
REPLACE THESE COMPONENTS WITH ONKYO
PARTS WHOSE PART NUMBERS APPEAR AS SHOWN
IN THIS MANUAL.
MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.
Page 2
SERVICE PROCEDURE
9
USE
33
R
>
r
USE
2
333GR
>
r
USE
5A-S
50V
8GR
>
910
USE
5A-UL/
33
6GR
910 or
USE
5
2
58GR
USE
50V
GR
9
USE
5A-S
K
8GR
>
3
USE
K
5GR
>
USE
5A-UL/
33
6GR
>
r
USE
50V
5GR
>
r
USE
5
2
58GR
>
1. Replacing the fuses
This symbol located near the fuse indicates that the
fuse used is show operating type, For continued protection against
fire hazard, replace with same type fuse, For fuse rating, refer to
the marking adjacent to the symbol.
Ce symbole indique que le fusible utilise est e lent.
Pour une protection permanente, n'utiliser que des fusibles de meme
type. Ce demier est indique la qu le present symbol est apposre.
<Notes>
<DD> : HT-R640 USA model
: HT-R640 European model
<PP>
HT-R640
REF NO.
01
F
F901 o
01
F
F901 o
F903
F903 o
F90
F903 o
F
F
F6901
F6902
PART NAME
F
F
F
F
F
F
F
F
F
F
F
FUSE
DESCRIPTION
10A-UL/T-2
10A-T/UL-ST
E-EA
E-TL2
T-2
A-T/UL-ST
2.5A-SE-EA
2.5A-SE-TL2
T-2
A-T/UL-ST
12A-TUL-2
12A-TUL-250V
PART NO.
252330G
252
25207
25227
25232
2522
25207
25227
25232
2522
252301
252301GR
REMARKS
!, <DD
!, <DD
!, <PP
!, <PP
!, <DD
!, <DD
!, <PP
!, <PP
!
2. To initialize the unit
1. Press and hold down the VIDEO 1/VCR 1 button, then press the STANDBY/ON button when the unit is Power on.
2. After " Clear " is displayed, the preset memory and each mode stored in the memory are initialized and will return to
the factory settings.
3. To check the version of microprocessor
Main microprocessor Q701 only.
1. Press and hold down the DISPLAY button , then press the STANDBY/ON button when the unit is Power on.
The version is displayed on FL display for 3 seconds.
Ex.
Main1.01/05305A
2. Press the STANDBY/ON button to Power off.
4. Memory Backup
The AV receiver uses a battery-less memory backup system in order to retain radio presets and other settings
when it's unplugged or in the case of a power failure.
Although no batteries are required, the AV receiver must be plugged into an AC outlet in order to charge the
backup system. Once it has been charged, the AV receiver will retain the settings for several weeks,
although this depends on the environment and will be shorter in humid climates.
Page 3
OPERATION CHECK-1
SPEAKER PROTECT-1 (DC VOLTAGE DETECTION)
[When]
1. Exchange power transistors (Q6050 - Q6054, Q6060 - Q6064).
2. Exchange amplifier PC board ass'y (NAAF-8911).
[Procedure]
<Note>
No load. No input.
1. Press and hold down the CD button, then press the STANDBY/ON button while the unit is Power ON.
" Test - _ " is displayed only for 5 seconds.
HT-R640
Test - _
2. Press the VIDEO 3 button, while the characters of " Test - _ " are displayed.
The unit will be in the state of "
Test-4-00
Blinks
".
Test - 4-00
3. Repeatedly press TONE
+ button until the characters of " Test-4-21 " are displayed.
Test - 4-21
Check whether the operation starts and continues automatically as follows.
Test - 4-21
Front L ch
Protect OK
Check
Test - 4-22
Front R ch
Protect OK
Check
Test - 4-23
Center ch
Protect OK
Check
Test - 4-25
Protect OK
Protect
Surround R ch
Check
Test - 4-24
Protect OK
If all channels are OK, the characters of
Test - 4-35
4. Press the STANDBY/ON button.
Clear
Surround L ch
Check
" Test - 4 - 35 "
Turn off
are displayed.
Page 4
OPERATION CHECK-2
SPEAKER PROTECT-2 (CURRENT DETECTION)
[When]
1. Exchange power transistors (Q6050 - Q6054 Q6060 - Q6064.
2. Exchange amplifier PC board ass'y (NAAF-8911).
[Procedure]
<Note>
No input.
Do not check two or more channels at the same time.
Do not connect a dummy load to speaker terminal longer than 2 seconds.
HT-R640
1. Press and hold down the
" Test - _ " is displayed only for 5 seconds.
2. Press the VIDEO 3 button, while " Test - _ " is displayed.
The unit will be in the state of "
CD
button, then press the
Test - _
Test-4-00
".
Blinks
STANDBY/ON
button while the unit is Power ON.
Test - 4-00
3. Repeatedly press
TONE
+
button until
" Test-4-35 " is displayed.
Test - 4-35
4. Connect the dummy load of
At this time, confirm that the speaker relay is
3
ohms to the Front L ch speaker terminal.
not turned off.
Test - 4-35
5. Connect the dummy load of 1 ohm to the Front L ch speaker terminal.
At this time, confirm that the speaker relay is turned off and " Protect " is displayed.
Protect
Disconnect the dummy load immediately after checking the display of
" Protect ".
Test - 4-35
6. Check other channels according to the same procedure as 4 and 5.
7. Press the
STANDBY/ON
button.
Turn off
Clear
Page 5
OPERATION CHECK-3
CONTROL OF POWER SUPPLY (OUTPUT SENSOR AND THERMAL SENSOR)
[When]
1. Exchange power transistors (Q6050 - Q6056, Q6060 - Q6066).
2. Exchange power amplifier PC board ass'y (NAAF-8911).
3. Exchange thermal sensor PC board ass'y (NAETC-8913).
[Procedure]
<Note>
No output. No input.
Output sensor
1. Press and hold down the CD button, then press the
" Test - _ " is displayed only for 5 seconds.
STANDBY/ON
button while the unit is Power ON.
HT-R640
Test - _
2. Press the
The unit will be in the state of "
VIDEO 3
button while
" Test - _ "
Test-4-00
Blinks
is displayed.
".
Test - 4-00
3. Repeatedly press TONE
+
button until
" Test-4-37 " is displayed.
Test - 4-37
4. At this time, confirm that the red characters of
And, check relay RL6901 and RL6902 are
" FM STEREO " is displayed.
turned off in 2 or 3 seconds.
FM STEREO
Test - 4-37
5. Press the STANDBY/ON button.
Clear
Thermal sensor
1. Press and hold down the
" Ver. 0.50/05131a " is displayed only for 2 seconds.
<Ex.>
DISPLAY button, then press the
Ver. 0.50/05131a
Turn off
STANDBY button when the unit is power ON.
TONE
2. Press the
3. Confirm that the displayed temperature is within +/-20 degree C from the ambient temperatures.
4. Press STANDBY/ON button.
button while " Ver.0.50/05131a " is displayed.
<Ex.>
T: 25 C/ 77 F
Turn off
Clear
Page 6
OPERATION CHECK-4(1/2)
DSP DEBUG MODE
The operation of DSP is able to checked by the information displayed on FL in this debug mode.
This information will help to pursue the cause of trouble.
To set in DSP debug mode
1. Press and hold down the
<Ex.>
DISPLAY button, then press the
The version number of microprocessor is displayed only for 2 seconds.
STANDBY
Ver. 0.50/05131a
1. Press the TONE+ button within 2 seconds above, the version number of DSP is displayed.
<Ex.>
DSP :06421A
button while the unit is power ON.
HT-R640
2. Press the
DISPLAY
<Ex.>
To exit
Press
STANDBY/ON button.
Content of display
2
1
-------------------------------- DIR ------------------------------------
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
Page 15
TO NADG-8816
(SD-6:A2)
P301
65432
1
HT-R640
C5630
47/50
C_OUT
SR_OUT
SL_OUT
L_OUT
R_OUT
R5630
3
3
220
R5631
Q5670
78M12
O
C5672
C5673
O2I
Q5671
79M12
47K
2
220/25
220/25
1
G
G
C5631
15K
I
C5671
1
10/50
3
2
221J
R5632
5
6
4
R5633
1.2K
8
C5670
10/50
Q5630A
NE5532
C5632
Q5630B
NE5532
GND_IR
VOLH
SEC1H
PROTECT
(SD-2)
TO MAIN AMP
R5681
220K
RN1441
Q5600
Q5601
Q5603
2.2K
Q5604
Q5605
2.2K
Q5606
Q5607
2.2K
RN1441
R5620
100
Q5610
RN1441
RN1441
R5623
R5624
0
RN1441
RN1441
R5625
R5626
0
RN1441
R5627
0
0
0
221J
D5707
22K
R5571
C5707
R5531
100
PRE OUT
SW
D5717
C5600
47/50
C5603
47/50
C5604
47/50
C5605
47/50
C5606
47/50
C5607
47/50
R5610
R5600
R5603
R5613
R5614
R5604
R5605
R5615
R5616
R5606
R5607
R5617
270
220K
220K
2.2K
220K
220K
2.2K
220K
220K
SW_OUT
1
R5634
10K
103J
7
SR_OUT
SL_OUT
L_OUT
R_OUT
C_OUT
+12V
R5677
8.2(2W)
R5670
R5678
R5672
47(2W)
R5673
68(2W)
R5671
68(2W)
8.2(2W)
47(2W)
+22V
-22V
C9004
RL1N4003 x4
1000/35
D9002
C9003
D9004
470/35
D9001
D9003
2.2(1W)
C9001
R5660
334J
R5661
2.2(1W)
GND_S1
GND_AMP
S1L+
S1L-
(SD-2:A3)
TO MAIN AMP
(SD-2:B5)
FROM AMP
221J
D5718
D5708
C5708
P7908
SR
SL
13
12
11
10
9
8
7
6
R
5
4
L
3
2
C
1
P5504B
(SD-3:A1)
TO NAAF-8917
P5503B
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
!
Page 16
A
SCHEMATIC DIAGRAM-2(SD-2)
POWER AMP SECTION-1
NAAF-8911 (2/2)
BCDEFGH
1
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
2
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
3
AMPLIFIER PC BOARD
NAETC-8913
U17
THERMAL
SENSOR
PC BOARD
VOLH
SEC1H
GNDS1
+22V
PROTECT
(SD-1:G1 & F4)
FROM AUDIO SECTION
1
JL6402A
T0 NADG-8816
(SD-6:A2)
!
R6701
22K
Q6380
LM61CIZ
G
V
O
2
+5VDIS
THERMAL
GNDDG2
321
10K
R6702
C6703
Q6703
2SA1163-BL
+
1/50
C6704
3
D6703
104Z
R6704
UDZS5.1B
POWER TRANSISTOR LIST
TYPE
Q6050-56
MN130S
DD
2SC5242
PP
33K
R6708
2SC2712-GR
2SC2712-GR
Q6702
Q6701
47K
R6706
220K
D6702
KDS4148U
+
10/50
C6706
D6701
KDS4148U
C6701
5.6K
UDZS5.1B
R6709
D6704
+
100/25
12K
R6710
Q6060-66
MP130S
2SA1962
Center ch
Front L ch
Front R ch
P6000B
5
NF
4
-B1
3
+B1
2
+B
1
-B
T0 NAAF-8917 (SD-3:B3)
P6001B
5
NF
4
-B1
3
+B1
2
+B
1
-B
T0 NAAF-8917 (SD-3:B4)
P6002B
5
NF
4
-B1
3
+B1
2
+B
1
-B
T0 NAAF-8917 (SD-3:B5)
U15
R6040
R6041
R6042
+B1C
1.1V
+BC
R6020
(1/4W)
2.2
470
R6030
1.0V
-0.4V
3.3K
1.0V
3.3K
3.3K
NFC
+BL
NFL
+B1R
+BR
NFR
-BC
-B1C
+B1L
-BL
-B1L
-BR
-B1R
Q6000
2SC1740S-S
Q6010
-1.1V
1.1V
R6021
2.2
Q6001
2SC1740S-S
2SC1740S-S
Q6011
-1.1V
1.1V
R6022
2.2
2SC1740S-S
Q6002
2SC1740S-S
Q6012
-1.1V
0.6V
2SC1740S-S
-0.6V
(1/4W)
0.6V
-0.6V
(1/4W)
0.6V
-0.6V
5.6K
R6000
-0.3V
3.9K
R6010
2K
R6050
470
R6031
5.6K
R6001
-0.3V
3.9K
R6011
-0.4V
2K
R6051
470
R6032
1.0V
5.6K
R6002
-0.3V
3.9K
R6012
-0.4V
2K
R6052
Q6030
2SC5171 or
2SC5993
(1/4W)
82
R6070
Q6040
2SA1930 or
2SA2140
Q6031
2SC5171 or
2SC5993
(1/4W)
R6071
82
Q6041
2SA1930 or
2SA2140
Q6032
2SC5171 or
2SC5993
(1/4W)
R6072
82
Q6042
2SA1930 or
2SA2140
+
C6040
+
C6041
+
C6042
R6080
0.22
(1/4W)
ID+
ID-
47/50
R6090
0.22
(1/4W)
R6081
0.22
(1/4W)
ID+
ID-
47/50
R6091
0.22
(1/4W)
R6082
0.22
(1/4W)
ID+
ID-
47/50
R6092
0.22
(1/4W)
P6080
-54.5V
P6081
P6082
-54.5V
-54.5V
54.5V
2
1
54.5V
2
1
54.5V
2
1
Q6050
LIST
R6140
22K
R6100
0.22(5W)
Q6060
LIST
R6170
47K
D6000
KDS4148U
Q6051
LIST
R6141
22K
R6101
0.22(5W)
Q6061
LIST
R6171
47K
D6001
KDS4148U
Q6052
LIST
R6142
22K
R6102
0.22(5W)
Q6062
LIST
R6172
47K
D6002
KDS4148U
4
NAPS-8912
U16
SEC. TERMINAL-2 PC BOARD
P15-P19 : Power Trans S1 terminal
P6904B(GRN)
P18
P6900B(BLK)
P17P19
P16
P6903B(YEW)
5
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
P15
JL6952A
1
2
3
4
JL6952B
1
2
3
4
P6903B
P6904B
(1W)
R6197
S1H+
S1H-
F6901
12A 250V
F6902
12A 250V
FROM AUDIO SECTION
100
2SC2712-GR
102J
C6911
S1L+
S1L-
(SD-1:F4)
Q6707
D6902
R6903
4
32
3
1SS352
41
47K
R6902
1K
RL6902
1
RL6901
2
C6912
334J/100V
C6913
C6915
C6916
D6901
334J/100V
D10XB60H
D10XB60H
104J
D6903
104J
GND_AMP
P6901A
+54.5V
+
C6901
LIST
P6900B
+
LIST
C6902
-54.5V
P6902A
CAPACITOR RATING
MODEL
C6901,C6902
DD
10000uF/63V
10000uF/69V
PP
P6011A
(COPPER BUS PLATE)
GND_SPSL
GND_SPSR
GND_SPR
GND_SPSBL
GND_SPSBR
987654321
R6130-6134
8.2(1W)
C6030-6034
473J(50V)
GND_S1
GND_SPL
GND_SPC
+22V
TO NAVD-8819
(SD-5:G1)
JL6603A
R6132
C6033
C6031
R6130
R6133
R6131
C6032
C6030
R6134
TO NAVD-8819 (SD-5:A3)
C6034
Page 17
HT-R640
Q6050
LIST
R6140
22K
R6100
0.22(5W)
Q6060
LIST
R6170
47K
D6000
KDS4148U
Q6051
LIST
R6141
22K
R6101
0.22(5W)
Q6061
LIST
R6171
47K
D6001
KDS4148U
R6150
R6180
47K
12K
R6181
47K
12K
R6151
C6050
R6190
D6010
C6051
R6191
D6011
R6160
103J
220K
KDS4148U
VPRO
VOLH
R6161
103J
220K
KDS4148U
VPRO
VOLH
Q6070
2SC2240
2SC2240
CLIMP AS
from C6901/6902
to Power Amp of all ch
IPRO
33K
SPC
IPRO
33K
Q6071
SPL
P6901B
-B
P6902B
P6910A
+B
P6902C
P6901C
CLIMP AS
from C6901/6902
to Power Amp
of Surr ch
P6910C
P6910B
P6910E
Surround L ch
Surround R ch
P6910D
P6910F
PVC ASSY
from C6901/6902
to Power Amp of Front ch
P6003B
5
NF
4
-B1
3
+B1
2
+B
1
-B
T0 NAAF-8917 (SD-3:D2)
P6004B
5
NF
4
-B1
3
+B1
2
+B
1
-B
T0 NAAF-8917 (SD-3:D3)
R6043
R6044
+B1SL
1.1V
+BSL
R6023
2.2
R6033
R6003
R6013
R6053
R6034
R6004
R6014
R6054
-0.3V
-0.4V
1.0V
-0.3V
-0.4V
1.0V
NFSL
3.3K
-BSL
-B1SL
+B1SR
+BSR
NFSR
3.3K
-BSR
-B1SR
(1/4W)
Q6003
2SC1740S-S
2SC1740S-S
Q6013
-1.1V
1.1V
R6024
(1/4W)
2.2
Q6004
2SC1740S-S
2SC1740S-S
Q6014
-1.1V
0.6V
-0.6V
0.6V
-0.6V
470
5.6K
3.9K
2K
470
5.6K
3.9K
2K
Q6033
2SC5171 or
2SC5993
(1/4W)
R6073
100
Q6043
2SA1930 or
2SA2140
Q6034
2SC5171 or
2SC5993
(1/4W)
R6074
100
Q6044
2SA1930 or
2SA2140
+
C6043
+
C6044
R6083
0.22
(1/4W)
47/50
R6093
(1/4W)
R6084
(1/4W)
47/50
(1/4W)
ID+
ID-
P6083
0.22
0.22
ID+
ID-
P6084
R6094
0.22
-54.5V
-54.5V
54.5V
2
1
54.5V
2
1
Q6053
LIST
R6143
22K
R6103
0.22(5W)
Q6063
LIST
R6173
47K
D6003
KDS4148U
Q6054
LIST
R6144
22K
R6104
0.22(5W)
Q6064
LIST
R6174
47K
D6004
KDS4148U
R6153
R6183
47K
R6154
R6184
IPRO
33K
R6163
Q6073
2SC2240
12K
103J
C6053
SPSL
220K
R6193
D6013
KDS4148U
VPRO
VOLH
IPRO
33K
R6164
Q6074
2SC2240
12K
103J
C6054
SPSR
220K
R6194
D6014
KDS4148U
VPRO
VOLH
47K
Q6052
LIST
R6142
22K
R6102
0.22(5W)
Q6062
LIST
R6172
47K
D6002
KDS4148U
R6152
R6182
IPRO
33K
R6162
Q6072
2SC2240
12K
103J
C6052
SPR
220K
R6192
D6012
KDS4148U
VPRO
VOLH
47K
TO NAVD-8819 (SD-5:A3)
SPC
1
SPL
2
SPR
3
SPSL
4
SPSR
5
6
7
JL6600A
VOLH
IPRO
VPRO
Page 18
HT-R640
A
SCHEMATIC DIAGRAM-3(SD-3)
POWER AMP SECTION-2
1
NAAF-8917
U19
DRIVER AMPLIFIER PC BOARD
TO NAAF-8911 (SD-1)
P5503A
2
Center ch
R5000
C5010
+
47/50
1K
R5010
221K
C5000
3
R5040
D5000
MTZJ5.6B
Front L ch
C5011
R5001
+
1K
47/50
R5011
C5001
221K
R5041
4
D5001
MTZJ5.6B
Front R ch
C5012
R5002
+
1K
47/50
R5012
221K
C5002
R5042
MTZJ5.6B
5
D5002
P5504A
123
4
56789
101112
13
+53.8V
1K
R5110
100K
R5090
Q5000
2SC2240-BL
R5020
-0.65V
330
56K
R5050
4.7K
2.2K
-48.2V
100K
R5021
330
R5022
330
100K
R5100
-48.2V
100K
R5101
100K
-48.2V
R5102
100K
R5111
Q5001
2SC2240-BL
-0.65V
R5051
4.7K
R5112
Q5002
2SC2240-BL
-0.65V
R5052
4.7K
R5060
R5080
K
1
R5061
R5081
1K
R5062
R5082
1.2K
470
1.2K
470
1.2K
470
10/50
+
C5020
R5091
56K
2.2K
10/50
+
C5021
R5092
56K
2.2K
10/50
+
C5022
+52.3V
Q5010
2SC2240-BL
+
C5040
Q5050
2SC2240-BL
-52.9V
-53.8V
+52.3V
Q5011
2SC2240-BL
C5041
Q5051
2SC2240-BL
-52.9V
-53.8V
+52.3V
Q5012
2SC2240-BL
C5042
Q5052
2SC2240-BL
-52.9V
-53.8V
C5100
C5110
+53.8V
C5101
+
C5111
+53.8V
C5102
+
C5112
+
+
+
+
+
+
0V
220/25
0V
0V
220/25
22/100
22/100
22/100
220/25
22/100
22/100
22/100
R5160
R5170
R5161
R5171
R5162
R5172
100
Q5030
C5080
100
100
Q5031
C5081
100
100
Q5032
C5082
100
(1/4W)
2SA949Y
040D
R5230
120K
Q5040
(1/4W)
(1/4W)
040D
R5231
120K
Q5041
(1/4W)
(1/4W)
040D
R5232
120K
Q5042
(1/4W)
P6011B
(1/4W)
10
R5180
1.1V
R5030
120K
C5090
-1.1V
2SC2229-Y
10
R5190
(1/4W)
10
R5181
1.1V
2SA949Y
R5031
120K
C5091
-1.1V
2SC2229-Y
10
R5191
(1/4W)
10
R5182
2SA949Y
1.1V
R5032
120K
C5092
-1.1V
2SC2229-Y
10
R5192
BCD
R5200
101K
(1/4W)
R5201
101K
(1/4W)
R5202
101K
(1/4W)
18K
R5130
18K
R5131
18K
18K
R5132
COPPER BUS PLATE
+
C5050
47/50
18K
+
C5051
47/50
18K
+
47/50
C5052
NFC
5
4
-B1C
+B1C
3
+BC
2
-BC
1
P6000A
TO NAAF-8911 (SD-2:D1)
NFL
5
-B1L
4
3
+B1L
2
+BL
1
-BL
TO NAAF-8911 (SD-2:D2)
P6001A
NFR
5
4
-B1R
+B1R
3
+BR
2
-BR
1
P6002A
TO NAAF-8911 (SD-2:D3)
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
P5019
Surround L ch
C5013
R5003
+
1K
47/50
C5003
221K
D5003
MTZJ5.6B
R5013
R5043
R5093
100K
R5023
330
56K
2.2K
-48.2V
10/50
+
100K
R5103
C5023
Surround R ch
R5094
100K
C5014
+
47/50
221K
MTZJ5.6B
D5004
R5014
R5044
R5024
330
56K
2.2K
-48.2V
10/50
+
100K
R5104
C5024
R5004
1K
C5004
1K
R5113
Q5003
2SC2240-BL
-0.65V
R5053
4.7K
1K
R5114
Q5004
2SC2240-BL
-0.65V
R5054
4.7K
R5063
R5083
R5064
R5084
+52.3V
Q5053
1.2K
-52.9V
470
+52.3V
Q5054
1.2K
-52.9V
470
-53.8V
Q5013
Q5014
!
+53.8V
+
C5103
22/100
2SC2240-BL
0V
+
220/25
C5043
+
C5113
22/100
2SC2240-BL
-53.8V
+53.8V
+
C5104
22/100
2SC2240-BL
0V
+
220/25
C5044
+
22/100
C5114
2SC2240-BL
R5163
R5173
R5164
R5174
100
Q5033
C5083
Q5043
100
100
Q5034
C5084
120K
100
R5183
(1/4W)
2SA949Y
R5033
120K
040D
R5233
120K
(1/4W)
R5184
10
(1/4W)
2SA949Y
R5034
120K
040D
R5234
Q5044
(1/4W)
(1/4W)
10
1.1V
R5203
101K
C5093
-1.1V
2SC2229-Y
R5193
(1/4W)
10
(1/4W)
1.1V
R5204
101K
C5094
-1.1V
2SC2229-Y
(1/4W)
10
R5194
22K
22K
R5133
22K
22K
R5134
+
C5053
+
C5054
47/50
47/50
NFSL
5
4
-B1SL
+B1SL
3
2
+BSL
1
-BSL
P6003A
TO NAAF-8911 (SD-2:F1)
NFSR
5
4
-B1SR
3
+B1SR
2
+BSR
1
-BSR
P6004A
TO NAAF-8911 (SD-2:F2)
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
BLANK17ALSB18GND19VAA20SCLOCK21SDATA22RSET223COMP224DAC F
16
13
4.7K
R4075
R4074
470J
C4084
42
CLAMP
4.7K
470J
220
R4125
41
TTX
R4076100
R4063
40
R4077100
OSD
1
VSS
2
XTALIN1
3
XTALOUT1
4
HSYNCOUT
5
XTALIN2
6
XTALOUT2
7
VSYNCOUT
8
CS
9
SIN
10
SCLK
11
SW1
12
SW2
13
C4085
SW3
14
SW4
15
RST16CVOUT
220
R4124
Q4014
2SA1162-GR
2SA1162-GR
1.2K
1.2K
R4064
C4068
39
37
38
VREF
RSET1
COMP1
TTXREQ
DAC A
SCRESET/RTC
DAC B
DAC C
DAC D
DAC E
R4079
R4078
1.2K
1.2K
TO NADG-8816 (SD-6:D1)
R4147
2.7k
1SS352
D4142
30
VDD1
29
SYNCDET
28
CVCOOUT
27
VCOIN
26
FC
R4104
25
AMPOUT
120
24
AMPIN
R4107
23
PDOUT
1.5K
22
VSS
21
SEPC
20
SYNCIN
19
R4108
CVCR
820K
18
Q4004
CVIN
17
VDD2
LC74763-9836
220
220
R4120
R4121
12k
R4118
Q4013
104Z
VAA
VAA
GND
VAA
VAA
GND
C4072
104Z
36
35
34
33
32
31
30
29
28
27
26
25
+3.3V
104Z
C4073
R4084
C4076
105K
R4088
R4092
C4165
104Z
R4068
R4080
C4074
C4075
104Z
68
C4077
104Z
R4096
P2006B
987654321
10
SPRLB
SPRLSB
SPRLCS
SELY
SPRLF
C4147
0.47/50
C4087
47k
R4148
474J
022K
L4008
C4088
L4009
C4089
056J
C4090
R4103
1K
R4106
C4092
6.8K
C4093
R4109
0.33/50
C4094
C4096
470/6.3
C4097
C4095
470J
104Z
C4099
100/16
Q4012
2SA1162-GR
C4102
104Z
2.7k
R4119
R4065
100
R4067
68
82
R4081
82
68
R4082
100
104Z
R4085
68
82
R4086
100
100
R4090
R4089
82
R4094
100
82
R4093
68
R4098
C4078
105K
100
R4097
82
68
SELV
C4175
R4117
101J
OSDCS
SYCDET
C4091
682J
220
122K
33k
OSDCK
OSDDA
+5V_VDD
022K
L4007
LBC2518
1/50
R4105
R4112
+5V_VD
68
R4114
D4001
C4101
104Z
R4116
2.2K
CYIN_DAC
C4170
101J
C4171
101J
PBIN_DAC
C4172
101J
PRIN_DAC
VIN_DAC
C4173
101J
YIN_DAC
C4174
101J
CIN_DAC
TO SD-5:G3
L4009
NCH-1572
L4008
LBC2518
C4088
C4089
C4090
6.8K
Q4017
2SC2712-GR
1K
R4110
3.3K
47K
R4111
C4100
1SS352
1
D4002
1SS352
270J
220J
223J
100/16
C4098
10K
R4113
104Z
Q4011
10K
R4115
+5V_VDD
+5V_VD
RN2402
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
!
TO SD-5:G3
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
Page 21
HT-R640
A
SCHEMATIC DIAGRAM-5(SD-5)
SPEAKER OUT SECTION
NAETC-8819 (2/2)
U14
1
JL6605B
NAETC-8790 (SD-8:B5)
2
3
JL6600B
TO NAAF-88911 (SD-2:E2)
VIDEO PC BOARD
01
HPL
02
LSPE
03
HPR
04
05
HPDET
R6691
MPUGND
390(1/2W)
R6992
390(1/2W)
LSP
01
02
03
04
05
06
07
CSP
RSP
SLSP
SRSP
BCDEFGH
PP-TYPE
L6602S1.3C
R6602 22
22
R6612
J6851
DD-TYPE
PP-TYPE
L6600S1.3C
R660022
22
R6610
J6600
DD-TYPE
PP-TYPE
S1.3C
L6601
22
R6601
R6611
22
J6604
DD-TYPE
PP-TYPE
S1.3C
L6603
22
R6603
22
R6613
J6619
DD-TYPE
PP-TYPE
L6604
S1.3C
22
R6604
R6614
22
J6620
DD-TYPE
C6602
223Z
RL6602
6
2
D6600
1SS352
C6600
223Z
RL6600
6
2
D6603
1SS352
C6603
223Z
RL6603
6
2
54
FRONT SPEAKERS
1
3
45
C6640
1
3
45
1
3
C6650
102J
C6643
103J
103J
C6653
102J
L
SL
P6601
P6602
SR
102J
C6652
C
R
103J
C6642
102J
103J
C6651
C6641
58
10
C6644
103J
C6654
102J
DTC123JKA
SURROUND SPEAKERS
4
TO NAPS-8787
TO NAETC-8788
5
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
5
4
3
2
JL901B
(SD-9:F1)
1
1
2
3
4
5
JL9101B
6
(SD-9:G2)
POFF
+12VD
MPUGND
FLAC1
FLAC2
SEC3-1
SEC3-2
SEC2-1
SEC2-2
+10S
POWERD
R9010
82(1/2W)
RL1N4003
D9002
+
C9001
R9005
220(1/2W)
470/63
D9013
1SS352
8.2K
R9003
D9005
Q9001
2SC2235-Y
8.2K
R9006
C9005
UDZS36B
47/50
R9004
33K
+5VDIS
223Z
C9006
R9011
4.7(1/2W)
APOWER
SEC2-1
Q9002
RN1405
-VP
SEC2-2
1SS352
1
R9013
D9015
1SS352
C9013
1
R9012
D9014
3.3/50
1SS352
D9012
C9012
334J
100k
R9014
3
D9017
1
D9011
C9011
1SS352
POFF2
10000/16
4
D5SBA20
2
UDZS5.6B
D9024
Page 22
Q6602
Q6601
DTC123JKA
SPRLF
SPRLCS
R6690
10(1/2W)
RLGND
+24V
+24V
RLGND
CSPE
LSPE
RSPE
SLSPE
SRSPE
01
02
03
04
05
06
JL6603B
07
08
TO NAAF-8911 (SD-2:D5)
09
HT-R640
DD:+12V
PP:+10V
R9028
0.47(1/2W)
+
C9021
470/16
1
VIN
5
SS
D9022
RL1N4003
Q9021
SI-8008
GND
TO SD-4:G1
SPRLCS
SPRLF
GND_HD
PP-TYPE
(PURE AUDIO)
Q9022
C9024
3
223Z
+
C9032
1
2
D9020
1SS352
470/6.3
BA00JC5WT
Vc
Vin
GND
3
GND_VD
Adj
Vo
+6V
R9002
R9020
R9021
10k
R9027
1.5k
R9008
MPC2905HF
+
C9031
470/16
DD-TYPE
R9018
0
10k
C9023
1.5k
Q9031
1
I
2
+
O
G
470/6.3
NCH-2541_470K
L9001
2
SW
4
VADJ
3
R9001
D9021
3.3(2W)
CRS09
3.3(2W)
R9017
0
5
4
100k
R9022
6.8k
R9023
33k
R9024
+
+5V_VD
C9025
470/6.3
VPOWER
223Z
C9022
R9029
0.47(1/2W)
L4015
LBC2518
HPDET
VPOWER
+5V_XM
GND_XM
+5VDIS
+5VDSP
GND_VD
GND_VD
+10VDSP
POFF
POFF2
APOWER
10S+12VD
-VP
FLAC1
FLAC2
047K
+5V_VDD
4
3
2
1
JL8001A
TO NAVD-8928 (SD-10 :B1)
TO SD-4G3
16
15
14
13
12
11
10
9
8
P2005B
7
6
5
TO NADG-8816 (SD-6:D1)
4
3
2
1
1
Q9031A
432
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
OPT2
OPT3
DIGITAL
OUT
RESET_3.3V
R284
L282
DIGITAL IN
FLASH ROM
4M Bit
Q282
10K
R281-284
L282
BLM21PG221SN1
SD RAM
16M bit
Q281
Page 25
HT-R640
A
SCHEMATIC DIAGRAM-7
NADG-8817
1
2
3
U13
XM PC BOARD
XM_SDI_L
XM_SDO_L
XM_COM_SEL
XM_ERR_IRQ
XM_RESET
BCDEFGH
Q2002
AK4384ET
1
MCLK
2
BICK
3
SDTI
4
LRCK
5
PDN
6
SMUTE/CSN
7
ACKS/CCLK
8
DIF0/CDTI
+3.3V
C2033
TA48033AF
3
470/6.3
R2001
100K
R2003
100K
C2001
R2002
100K
C2002
102K
104Z
R2004
100K
1
LSDP
2
VSS
3
SC_TX_OUT
4
VDD
5
SC_RX_IN
6
VSS
7
CMD_SEL
8
VDD
9
ERR_IRQ
10
VSS
11
RST
12
SLAVE
_SEL
104Z
C2013
48
47
45
46
VDD
SAII_DA
SAII_EN
F2602E-01
COMM_RX_DIG
COMM_TX_DIG
COMM_TX_EN
13
14
15
16
100K
R2005
R2006
R2007
L2002
BK1608LM182
C2012
41
40
43
42
44
VSS
VSS
VDD
SAII_CLK
I2S_OCLK
I2S_LRCLK
Q2001
XMDTIC
VSS17VDD18COMM_RX_P
COMM_RX_M
VDD21VSS22COMM_TX_M
19
20
104Z
C2003
104Z
R2008
C2004
100
1K
R2009
1K
100
104Z
39
38
VSS
I2S_CLK
HSDP_CLK
COMM_TX_P
23
I2S_OCLK
I2S_SCLK
I2S_SDO
I2S_LRCLK
37
I2S_DA
HSDP_EN
VSS
VDD
HSDP_DA
VSS
TEST
VSS
OSC_IN
VDD
OSC_OUT
VSS
VSS
24
104Z
C2005
C2006
104Z
100
R2012
R2013
330
R2014
330
R2015
330
R2016
0
C2014
102K
DAC_RESET
36
35
34
C2011
33
104Z
32
31
30
29
28
27
26
25
C2007
C2010
104Z
100/16
C2009
080D
1M
R2011
R2010
C2008
040C
+3.3V_XM
X2001
45.1584MHz
680
L2001
LBC2518T2R2M
4
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
5
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
!
Page 26
Q2002
DZFL
DZFR
VDD
VSS
2ch DAC
VCOM
AOUTL
AOUTR
P/S
16
15
14
13
12
11
10
9
+5V
1
C2018
470/6.3
C2017
104Z
C2016
10/50
C2015
104Z
2
O3I
Q2005
78L05
G
C2021
10/50
C2022
10/50
104Z
L2003
C2031
LBC2518T2R2M
R2023
R2024
R2021
2.2K
100K
100K
R2022
2.2K
R2025
2.2K
R2026
2.2K
C2025
821J
C2023
C2024
C2026
821J
821J
R2029
R2030
821J
3
2
3.3K
3.3K
6
5
NE5532APSR
8
Q2003
R2027
2.2K
R2028
2.2K
Q2003
4
NE5532APSR
HT-R640
R2031
22(1/2W)
C2027
1
10/50
C2029
220/16
C2030
C2028
7
10/50
220/16
R2032
22(1/2W)
XM_L_OUT
XM_R_OUT
GND_A
+12V
-12V
1
2
3
4
5
JL5502B
6
7
TO NAAF-8911 (SD-1:C1)
C2033
TA48033AF
3
470/6.3
Q2004
1
O
I
G
2
XM_ERR_IRQ
XM_SDI_L
DAC_RESET
XM_COM_SEL
XM_SDO_L
XM_RESET
C2032
104Z
R2047
22(1/2W)
C2043
100/16
R2036
0
Q2006
TC74HCT7007AF
1
2
3
4
5
6
7
GND8OUT4
Q2007
TC74VHC541FT
11
Y8
12
Y7
13
Y6
14
Y5
15
Y4
16
Y3
17
Y2
18
Y1
19
_G2
20
VCC1_G1
104Z
C2036
VCC
OUT6
OUT5
GND
102K
C2044
E2002
L2004
BLM21PG221SN1
104Z
C2042
C2034
100/16
R2033
22
R2034
22
L2005
BLM21PG221SN1
D2001
UDZS5.1B
C2035
104Z
14
13
IN6
12
11
IN5
10
9
IN4
10
9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
R2035
R2046
0
0
R2044
220
XMDACRST
XMCOMSEL
XMERRIRQ
XMSRSEL
XMSRTXD
XMSRRXD
XMRST
GND
+5V_XM
E2003
E2001
4
3
2
1
P2001
GND
D+
XM
D-
+V
1
2
3
4
5
6
JL101B
7
8
9
TO NADG-8816 (SD-6:E1)
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
Page 27
A
BCDEFGH
SCHEMATIC DIAGRAM-8(SD-8)
DISPLAY SECTION
1
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
2
3
4
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
2
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
SD-x:XY is short for Shcematic Diagram-x and
each socket's location, X=A to H, Y=1 to 5.
!
D930
1SS133
T902
NPT-1519*
1
2
3
4
9
8
7
6
5
C921
223Z
3
1SS133
1SS133
1SS133
1SS133
1SS133
D925
1SS133
C902
104J
D931
D923
D921
D924
D922
56(1/2W)
2
3
PP
41
C901
103M/275VAC
RL901
F901
T5AL250V
AC CORD
1
2
P901A
1
2
P911
41
103M/275VAC
RL901
C901
F903
5A 125V
4
P902
AC OUTLET
100W MAX
F903
T2.5AL250V
P902
AC OUTLET
100W MAX
POWER SUPPLY VOLTAGE AND FREQ.
TYPE
D
120V 60HZ
PAC230-240V 50HZ
5
POWER TRANSFORMER
TYPE
D
P
T901
NPT-1518D
NPT-1518P
T902
NPT-1520JQ
NPT-1519GQ
Page 30
HT-R640
R934
R921
56(1/2W)
MTZJ5.1B
D934
100K
C922
2200/16
+
C930
100/35
+
POFF
+12VD
MPUGND
+10VS
POWERD
102J
C911
E901
D911
1SS133
5
4
3
2
1
D912
1SS133
POWER TRANS
T901
1
JL901A
(SD-5:A5)
TO NAVD-8819
S4
S3
NAETC-8788
U04
SEC TERMINAL-1
PC BOARD
R9102
8
5.6 (1/2W)
104J
9
10
11
12
13
C9101
TO NAVD-8819
(SD-5:A5)
12345
FLAC1
FLAC2
SEC3_2
SEC3_1
JL9101A
6
SEC2_1
SEC2_2
F901
10A 125V
1
2
1
2
3
S2
14
F910
5A 125V
P911
S1
CAUTION
(SD-2:A5)
TO NAPS-8912, P15-P19
FOR CONTINUED PROTECTION
AGAINST FIRE HAZARD, REPLACE
ONLY WITH FUSE OF SAME TYPE
AV
AND RATING INDICATED.
ATTENTION
CAUTIONF AFIN D'ASSURER UNE PROTECTION
V A
THIS SYMBOL LOCATED NEAR THE FUSE INDICATES
THAT THE FUSE USED IS SLOW OPERATING TYPE
FOR CONTINUED PROTECTION AGAINST FIRE FUSE
HAZARD,REPLACE WITH SAME TYPE FUSE. FOR FUSE
RATING REFER TO THE MAKING ADJACENT TO THE SYMBOL.
CE SYMBOLE INDIQUE QUE LE FUSIBLE UTLISE EST
A LENT, E POUR UNE PROTECTION PERMANENTE,N'UTILISER
QUE DES FUSIBLES DE MEME TYPE. CE DARNIER EST
INDIQUE LA QU LE PRESENT SYMBOL EST APPOSE.
PERMANENTE CONTRE LES RISQUES
D'INCENDIE, REMPLACER UNIQUEMENT
PAR UN FUSIBLE DE MEME TYPE
ET CALIBRATION COMME INDIQUE.
Q4003: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
BLOCK DIAGRAM
HT-R640
MD-2000
FIELD/
TTX
TTXREQ
V
AA
P0
COLOR
DATA
P7
PAL
CLOCK
INSERTION BLOCK
4:2:2 TO
4:4:4
INTER-
POLATOR
NTSC
TELETEXT
8
8
8
VIDEO TIMING
GENERATOR
Y
YCrCb
U
TO
YUV
MATRIX
V
8
8
8
CLAMP
SCLOCK SDATA
I2C MPU PORT
BRIGHTNESS AND
CONTRAST CONTROL
SATURATION CONTROL
+
ADD SYNC
+
INTERPOLATOR
+
ADD BURST
+
INTERPOLATOR
CONTROL CIRCUIT
REAL-TIME
SCRESET/RTC
ALSB
PROGRAMMABLE
10
SHARPNESS
10
PROGRAMMABLE
10
LUMA
FILTER
+
FILTER
CHROMA
FILTER
GND
YUV TO
RBG
MATRIX
+
YUV
LEVEL
CONTROL
BLOCK
MODULATOR
+
HUE
CONTROL
1010
SIN/COS
DDS BLOCK
M
10
10
U
10-BIT
L
DAC
T
10
10
I
10-BIT
P
DAC
L
E
10
10
10-BIT
X
DAC
E
R
DAC
CONTROL
M
BLOCK
U
L
10
10-BIT
T
I
P
L
E
X
E
R
10
10-BIT
10
10-BIT
DAC
CONTROL
BLOCK
DAC
DAC
DAC
10
10
10
DAC A
DAC B
DAC C
V
REF
R
SET2
COMP2
DAC E
DAC F
DAC D
R
SET1
COMP1
PIN CONFIGURATION
V
AA
P0
P1
P2
P3
P4
P5
P6
P7
CSO_HSO
V
AA
GND
AA
RESET
VSO
CLOCK
GND
48 47 46 45 4439 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
HSYNC
V
ADV7172
TOP VIEW
BLANK
ALSB
PAL NTSC
GND
CLAMP
TTX
AA
V
SCLOCK
FIELD/VSYNC
SET1
R
SCRESET/RTC
TTXREQ
SET2
R
SDATA
COMP2
REF
V
DAC F
36
35
34
33
32
31
30
29
28
27
26
25
COMP1
DAC A
V
AA
DAC B
V
AA
GND
V
AA
DAC C
DAC D
V
AA
GND
DAC E
Page 61
MD-2000
HT-R640
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -2
Q4003: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
TERMINAL DESCRIPTION
MnemonicInput/OutputFunction
P7–P0I8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7ÐP0) P0 represents the LSB.
CLOCKITTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alter-
natively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
FIELD/VSYNCI/ODual Function FIELD (Mode 1) and
BLANK
SCRESET/RTCIThis pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It
V
REF
R
SET1
R
SET2
COMP1OCompensation Pin for DACs A, B, and C. Connect a 0.1 uF Capacitor from COMP to
COMP2OCompensation Pin for DACs D, E, and F. Co nnect a 0.1 uF Capacitor from COMP to V
DAC AOGREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.
DAC BOBLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.
DAC CORED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output.
DAC DOGREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.
DAC EOBLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.
DAC FORED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.
SCLOCKIMPU Port Serial Interface Clock Input.
SDATAI/OMPU Port Serial Data Input/Output.
CLAMPOTTL Output Signal to external circuitry to enable clamping of all video signals.
PAL_NTSCIInput signal to select PAL or NTSC mode of operation, pin set to Logic "1" selects PAL.
VSO
CSO_HSO
ALSBITTL Address Input. This signal sets up the LSB of the MPU address.
RESET
TTXITeletext Data Input Pin.
TTXREQOTeletext Data Request output signal used to control teletext data transfer.
V
AA
GND
I/O
I/OVideo Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0."
I/OVoltage Reference Input for DACs or Voltage Reference Output (1.235 V).
IA 150 resistor connected from this pin to GND is used to control full-scale amplitudes of
IA 600 resistor connected from this pin to GND is used to control full-scale amplitudes of
O VSO TTL Output Sync Signal.
ODual Function
IT he input resets the on-chip timing generator and sets the ADV7172/ADV7173 into
PPower Supply (3 V to 5 V).
G
HSYNC
Mode) or as an input and accept (Slave Mode) Sync signals.
configured to output (Master Mode) or as an input (Slave Mode) and accept these
control signals.
This signal is optional.
can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a RealTime Control (RTC) Input.
the Video Signals from DACs A, B, and C (the "large" DACs).
the Video Signals from DACs D, E, and F (the "small" DACs).
V
COMP1 capacitor can be lowered to as low as 2.2 nF.
default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered
OFF, DACs D, E, and F powered ON, Composite and S-Video out.
Ground Pin.
(Modes 1 and 2) Control Signal. This pin may be configured to output (Master
VSYNC
. For Optimum Dynamic Performance in Low Power Mode, the value of the
AA
or HSO TTL Output Sync Signal.
CSO
(Mode 2) Control Signal. This pin may be
AA
.
Page 62
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -3
Q4001: ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)
AIN5
AIN11
AIN4
AIN10
AGND
CAP C2
CAP C1
AGND
CML
REFOUT
AVDD
CAP Y2
CAP Y1
AGND
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
Page 63
HT-R640
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -4
Q4001: ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)
TERMINAL DESCRIPTION (1/2)
PinMnemonicInput/OutputFunction
1VS/VACTIVEOVS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
32, 33, 73-76
9, 31, 71DVSS1-3GGround for Digital Supply
10, 30, 72DVDD1-3PDigital Supply Voltage (3.3 V)
11AFFOAlmost Full Flag. A FIFO control signal indicating when the FIFO has
12HFF/QCLK/GLI/OHalf Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
13AEFOAlmost Empty Flag. A FIFO control signal, it indicates when the FIFO
16CLKINIAsynchronous FIFO Clock. This asynchronous clock is used to output
17, 18, 34, 35 GPO[3:0]OGeneral-Purpose Outputs controlled via I C
25LLCREFOClock Reference Output. This is a clock qualifier distributed by the inter-
26LLC2OLine-Locked Clock System Output Clock/2 (13.5 MHz)
27LLC1/PCLKOLine-Locked Clock System Output Clock. A dual-function pin (27 MHz 5%)
28XTAL1OSecond terminal for crystal oscillator; not connected if external clock
29XTALIInput terminal for 27MHz crystal oscillator or connection for external
36PWRDNIPower-Down Enable. A logical low will place part in a power-down status.
37ELPFIThis pin is used for the External Loop Filter that is required for the LLC PLL.
38
39
PVDD
PVSSG
P
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
data onto the P19-P0 bus and other control signals.
2
nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled
by the PLLCREF bit.
or a FIFO output clock ranging from 20 MHz to 35 MHz.
source is used.
oscillator with CMOS-compatible square wave clock signal
Page 64
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -5
Q4001: ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)
TERMINAL DESCRIPTION (2/2)
PinMnemonicInput/OutputFunction
40, 47, 53, 56,
63
41, 43, 45, 57,
59, 61
42, 44, 46, 58,
60, 62
48, 49
50
51
52
54, 55
64
65
66
67
68
69
70
77
78
79
80
AVSS
AVSS1-6
AIN1-6
CAPY1-2
AVDD
REFOUT
CML
CAPC1-2
RESET
ISO
ALSB
SDATA
SCLK
VREF/VRESET
HREF/HRESET
RD
DV
OE
FIELD
G
G
I
I
P
O
O
I
I/O
I
I
I/O
I
O
O
I
O
I
O
Ground for Analog Supply
Analog Input Channels. Ground if single-ended mode is selected. These
pins should be connected directly to REFOUT when differential mode is
selected.
Video Analog Input Channels
ADC Capacitor Network
Analog Supply Voltage (5 V)
Internal Voltage Reference Output
Common-Mode Level for ADC
ADC Capacitor Network
System Reset Input. Active Low.
Input Switch Over. A low to high transition on this input indicates to the
decoder core that the input video source has been changed externally and
configures the decoder to reacquire the new timing information of the new
source. This is useful in applications where external video muxes are used.
This input gives the advantage of faster locking to the external muxed
video sources. A low to high transition triggers this input.
TTL Address Input. Selects the MPU address:
MPU address = 88h ALSB = 0, disables I C filter
MPU address = 8Ah ALSB = 1, enables I C filter
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
VREF or Vertical Reference Output Signal. Indicates start of next field.
VRESET or Vertical Reset Output is a signal that indicates the beginning
of a new field. In SCAPI/CAPI mode this signal is one clock wide and
active low relative to CLKIN. It immediately follows the HRESET pixel,
and indicates that the next active pixel is the first active pixel of the next field.
HREF or Horizontal Reference Output Signal. A dual-function pin
(enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0),
this signal is used to indicate data on the YUV output. The positive slope
indicates the beginning of a new active line; HREF is always 720 Y samples
long. HRESET or Horizontal Reset Output (enabled when SCAPI or
CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the
beginning of a new line of video. In SCAPI/CAPI this signal is one clock
cycle wide and is output relative to CLKIN. It immediately follows the last
active pixel of a line. The polarity is controlled via PHVR.
Asynchronous FIFO Read Enable Signal. A logical high on this pin enables
a read from the output of the FIFO.
DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs to
functions, depending on whether SCAPI or CAPI is selected. It toggles
high when the FIFO has reached the AFF margin set by the user, and
remains high until the FIFO is empty. The alternative mode is where it can
be used to control FIFO reads for bursting information out of the FIFO. In
API mode DV indicates valid data in the FIFO, which includes both pixel
information and control codes. The polarity of this pin is controlled via PDV.
Output Enable Controls Pixel Port Outputs. A logic high will three-state
P19-P0.
ODD/EVEN Field Output Signal. An active state indicates that an even
field is being digitized. The polarity of this signal is controlled by the PF bit.
HT-R640
2
2
Page 65
K
K
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -6
Q2002: AK4384 (192kHz 24-Bit 2ch DAC )
HT-R640
BLOCK DIAGRAM
MCLK
Clock
Divider
Modulator
Modulator
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
LRC
BIC
SDTI
P/S
µP
Interface
Audio
Data
Interface
PDN
ATT
ATT
De-emphasis
Control
8X
Interpolator
8X
Interpolator
TERMINAL DESCRIPTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power -Down Mode Pin
When at “L”, the AK4384 is i n the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
SMUTE I Soft Mute Pin in parallel mode
6
“H”: Enable, “L”: Disable
CSN I Chip Select Pin in serial mode
ACKS I Auto Setting Mode Pin in parallel mode
7
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK I Control Data Clock Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode 8
CDTI I Control Data Input Pin in serial mode
9 P/S I
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10 AOUTR O Rch Analog Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF c
a 10m F electrolytic cap.
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
PIN CONFIGURATION
VDD
VSS
VCOM
DZFL
DZFR
SCF
LPF
SCF
LPF
AOUTL
AOUTR
MCLK
BICK
SDTI
LRCK
PDN
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
1
2
3
4
Top
View
5
6
7
8
eramic capacitor in parallel with
DZFL
16
DZFR
15
VDD
14
VSS
13
12
VCOM
AOUTL
11
AOUTR
10
P/S
9
Page 66
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -7
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
BLOCK DIAGRAM
HT-R640
V1
V2
V3
V4
V5
V6
V7
V8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
C1
C2
C3
C4
C5
C6
C7
C8
4/6dB
6dB
4/6dB
6dB
4/6dB
6dB
Buf
75<E
75<E
75<E
Buf
75<E
75<E
75<E
Buf
75<E
75<E
75<E
Vout1
Vout2
Vout2-FB
Vout3
Vout3-FB
Vout4
Vout4-FB
Yout1
Yout2
Yout2-FB
Yout3
Yout3-FB
Yout4
Yout4-FB
Cout4
Cout1
Cout2
Cout3
CY1
CY2
CY3
CY4
CY5
CY6
PB1
PB2
PB3
PB4
PB5
PB6
PR1
PR2
PR3
PR4
PR5
PR6
SDA
SCL
O1 O2
Logic
6dB
6dB
6dB
6dB
6dB
6dB
BIAS
75<E
75<E
75<E
75<E
75<E
75<E
VCCGNDMUTE
CYout2
CYout2-FB
CYout3
CYout3-FB
PBout1
PBout2
PRout1
PRout2
Page 67
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -8
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (1/3)
DescriptionTypePin namePin No.
Luminance signal in put 3InY31
Luminance signal input 4InY42
Luminance signal input 5InY53
Luminance signal input 6InY64
Luminance s ignal input 7InY75
Luminance signal in put 8InY86
5.0V power supplyPower supplyVCC17
Chrominance signal input 1InC18
Chrominance signal input 2InC29
Chrominance signal input 3InC310
Chrominance signal input 4InC411
Chrominance signal input 5InC512
GroundGroundGND113
Chrominance signal input 6InC614
Chrominance signal input 7InC715
Chrominance signal inpu t 8InC816
HT-R640
Bias voltageOutputBIAS17
CY1 signal inputInCY118
CY2 signal inputInCY219
CY3 signal inputInCY320
CY4 signal inputInCY421
CY5 signal inputInCY522
CY6 signal inputInCY623
PB1 signal inputInPB124
PB2 signal inputInPB225
PB3 signal inputInPB326
PB4 signal inputInPB427
PB5 signal inputInPB528
PB6 signal inputInPB629
PR1 signal inputInPR130
PR2 signal inputInPR231
PR3 signal inputInPR332
PR4 signal inputInPR433
PR5 signal inputInPR534
PR6 signal inputInPR635
Page 68
HT-R640
IC BLOCK DIAGRAM AND
TERMINAL DESCRIPTIONS -9
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (2/3)
DescriptionTypePin namePin No.
Mute control pinInMUTE36
PROUT2 signal outputOutPROUT237
General output 1OutO138
PROUT1 signal outputOutPROUT139
General output 2OutO240
PBOUT2 signal outputOutPBOUT241
PBOUT1 signal outputOutPBOUT142
GroundGroundGND243
CYOUT3 feedback inputInCYOUT3-FB44
CYOUT3 signal outputOutCYOUT345
CYOUT2 feedback inputInCYOUT2-FB46
CYOUT2 signal outputOutCYOUT247
COUT4 signal outputOutCOUT448
5.0V power supplyPower supplyVCC249
COUT3 signal outputOutCOUT350
COUT2 signal outputOutCOUT251
COUT1 signal outputOutCOUT152
GroundGroundGND353
YOUT4 feedback inputInYOUT4-FB54
YOUT4 signal outputOutYOUT455
YOUT3 feedback inputInYOUT3-FB56
YOUT3 signal outputOutYOUT357
YOUT2 feedback inputInYOUT2-FB58
YOUT2 signal outputOutYOUT259
YOUT1 signal outputOutYOUT160
5.0V power supplyPower supplyVCC361
VOUT4 feedback inputInVOUT4-FB62
VOUT4 signal outputOutVOUT463
2
I
C bus data inputInSDA64
VOUT3 feedback inputInVOUT3-FB65
VOUT3 signal outputOutVOUT366
VOUT2 feedback inputInVOUT2-FB67
VOUT2 signal outputOutVOUT268
VOUT1 signal outputOutVOUT169
2
I
C bus clock inputInSCL70
Page 69
IC BLOCK DIA GRAM AND TERMINAL DESCRIPTIONS -10
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (3/3)
DescriptionTypePin namePin No.
Video composite signal input 1InV171
Video composite signal input 2InV272
Video composite signal input 3InV373
Video composite signal input 4InV474
Video composite signal input 5InV575
Video composite signal input 6InV676
Video composite signal input 7InV777
Video composite signal input 8InV878
Luminance signal in put 1InY179
Luminance signal input 2InY280
CX_SCLKCODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
1
Codec Serial Audio Data Input (Input) - Input for two's complement serial audio data.
64
63
62
2
3
CODEC Left Right Clock (Input/ Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
4
Digital Power (Input) - Positive power supply for the digital section.
51
5
Digital Ground (Input) - Ground reference. Should be connected to digital ground.
52
6
Control Port Power (Input) - Determines the required signal level for the control port.
7
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I2C mode as shown in the Typical Connection Diagram.
8
Serial Control Data (Input/Output) - SDA is a data I/O line in IC mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
Address Bit 1 (I2C)/Serial Control Data (SPI) (Input) - AD1 a chip address pin in I2C mode; CDIN is
9
the input data line for control port interface in SPI mode.
Page 73
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -14
Q301 : CS42518 (8-Ch Codec with S/PDIF Receiver)
TERMINAL DESCRIPTION (2/3)
Pin Name#Pin Description
AD0/CS10Address Bit 0 (I2C)/Control Port Chip Select (SPI) (INput) - AD0 is a chip address pin in I2C mode; CS
is the chip select signal in SPI mode.
INT11Interrupt (Ountput) - The CS42518 will generate an interrupt condition as per the Interrupt Mask register.
RST12Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINRAINR+
AINLAINL+
VQ17Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+18Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND19Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTA1 +, -
RXP049S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP50S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
VLP53Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT54
RMCK55Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
Analog Characteristics specification table.
Analog Power (Input) - Positive power supply for the analog section.
Analog Ground (Input) - Ground reference. Should be connected to analog ground.
dition or whenever the PDN bit is set to a "1", forcing the codec into power -down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not mandatoy but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
S/PDIF Receiver Input/ General Purpose Output (Input/ Output) - Receiver inputs for S/PDIF encoded
data. The CS42518 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 resister. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
resisters.
receiver inputs as indicated by the Receiver Mode Control 2 resister.
Serial Audio Interface Serial Data Output (Output) - Output for two's complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the internal and external ADCs.
HT-R640
Page 74
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -15
Q301 : CS42518 (8-Ch Codec with S/PDIF Receiver)
TERMINAL DESCRIPTION (3/3)
Pin Name#Pin Description
CL_SDOUT56CODEC Serial Data Output (Output) - Output for two's complement serial audio data the internal
and external ADCs.
ADCIN1
ADCIN2
OMCK59
SAI_LRCK60
SAI_LRCK61Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface
58
57
External ADC Serial Input (Input) - The CS42518 provides for up two external stereo analog to digital
converter inputs to provide a maximum of six channels on serial data output line when the CS42518
is placed in One Line mode.
External Reference Clock (Input) - External clock reference that must be within the ranges specified in
currently active on the serial audio data line.
Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left of Right, is
currently active on the serial audio data line.
19A11A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is
16CASCAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth
34CKEThe CKE input determines whether the CLK input is enabled within the device.
35CLKCLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired
18CSThe CS input determines whether command input is enabled within the device.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
14, 36LDQM,
17RASRAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth
15WEWE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth
7, 13, 38, 44V
1, 25V
4, 10, 41, 47GNDQGNDQ is the output buffer ground.
26, 50GNDGND is the device internal ground.
A0-A10A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input
I/O0
to
I/O15
UDQM
CCQVCCQ is the output buffer power supply.
and A0-A7 as column address inputs during read or write command input. A10 is also used to
determine the precharge mode during other commands. If A10 is LOW during precharge command,
the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after
the burst access.
These signals become part of the OP CODE during mode register set command input.
selected. This signal becomes part of the OP CODE during mode register set command input.
Table" item for details on device commands.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode,
or the self refresh mode. The CKE is an asynchronous input.
in synchronization with the rising edge of this pin.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in
the previous state when CS is HIGH.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and
UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and
UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to theHIGH
impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to
the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device.
Table" item for details on device commands.
Table" item for details on device commands.
CCVCC is the device internal power supply.
HT-R640
Page 82
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -23
Q4004: LC74763-9836 (On-Screen Display IC)
BLOCK DIAGRAM
HT-R640
SCLK
RST
SECAM
525/625
NTSC/PAL
3.58/4.43
VDD1
VDD2
VSS
SYNCDET
VCOIN
VCOOUT
AMPIN
AMPOUT
PDOUT
CS
SIN
Serialparallel
converter
Composite
synchronization
signal
control
FC
AFC
circuit
8-bit latch
and
command
decoder
Sync
detector
Composite
synchronization
signal separator
control
Horizontal
character
size register
Horizontal
size
counter
Vertical
character
size register
Vertical
size
counter
Timing generator
Horizontal
display
position
register
Horizontal
dot counter
Horizontal
display
position
detection
Character
control
counter
Vertical
display
position
register
Vertical
dot counter
Vertical
display
position
detection
Line
control
counter
Synchronization
signal generator
Flashing/
reversal
control
register
Flashing/
reversal
control
circuit
Character output control
Background control
video output control
Display
control
register
RAM write
address
counter
Decoder
Display RAM
Decoder
Font ROM
Shift register
SYSIN
SEPC
Sync
separator
PIN CONFIGRATION
VDD1
30
1
VSS
VSYNOUTHSYNOUT
SYNCDET
29
2
XTALIN1
VCOOUT
28
3
XTALOUT1
VCOIN
27
4
HSYNCOUT
FC
26
5
XTALIN2
AMPOUT
25
6
XYALOUT2
Xtal IN1
AMPIN
PDOUT
23
24
LC74763
8
7
CS
VSYNCOUT
Xtal OUT1
VSS
22
9
SIN
21
10
SEPC
SCLK
Xtal IN2
SYNCIN
20
11
SECAM
Xtal OUT2
CVCR
19
12
525/625
CVIN
18
13
NTSC/PAL
VDD2
17
14
3.58/4.43
CVOUTCVINCVCR
CVOUT
16
15
RST
Page 83
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -24
Q4004: LC74763-9836 (On-Screen Display IC)
TERMINAL DESCRIPTION
Pin No.SymbolFunctionDescription
1V
2Xtal
3Xtal
4HSYNC
5Xtal
6Xtal
7VSYNC
8CSEnable input
9SINData inputSerial data input (hysteresis input). Pull-up resistor built in (metal option).
10SCLKClock inputClock input for serial data input (hysteresis input). Pull-up resistor built in (metal option).
11SECAM
12525/625
13NTSC/PAL
143.58/4.433.58/4.43 switch input/outputDuring output, functions as general output port or halftone output (command switch).
15RSTReset input
16CV
17V
18CV
19CV
20SYNC
21SEP
22V
23PD
24AMP
25AMP
26FCControl voltage inputAFC control voltage input
27VCO
28VCO
29SYNC
30V
SS
OUT1
OUT2
OUT
DD2
CR
SS
OUT
OUT
DD1
GroundGround connection
IN1
Crystal oscillator connection
Horizontal synchronization Outputs the horizontal synchronization signal (AFC). The output polarity can be selected
OUT
output(metal option). Also functions as general output port (command switch).
IN2
Crystal oscillator connection
Vertical synchronization output
OUT
SECAM mode switch input/
output (command switch)
525/625 switch input/output
(command switch)
NTSC/PAL switch input/output
(command switch)
(command switch)Low = 3.58, high = 4.43
Video signal outputComposite video output
Power supply connectionPower supply connection for composite video signal level generation
Video signal inputComposite video input
IN
Video signal inputSECAM chroma signal input
Sync separator circuit inputBuilt-in sync separator circuit video signal input
GroundGround connection
Control voltage outputAFC control voltage output
IN
AFC filter connectionFilter connection
OUT
IN
LC oscillator connectionVCO LC oscillator circuit coil and capacitor connection
External synchronization signal
DET
detection output
Power supply connection
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. The oscillator can be selected with a command switch.
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal.
Outputs the vertical synchronization signal. The output polarity can be selected (metal
option). Also functions as general output port (command switch).
Enables/disables serial data input. Serial data is enabled when this pin is low (hysteresis
input). Pull-up resistor built in (metal option).
During input, switches between SECAM and other modes.
During output, functions as general output port or internal V output (command switch).
Low = other modes, high = SECAM mode
During input, switches between 525 scan lines and 625 scan lines.
During output, functions as general output port or character data output (command switch).
Low = 525 lines, high = 625 lines
Switches the color mode between NTSC and PAL.
During output, functions as general output port or frame data output (command switch).
Low = NTSC, high = PAL
Switch FSC between 3.58 MHz and 4.43 MHz.
System reset input pin, low is active (hysteresis input).
Pull-up resistor built in (metal option).
Outputs the exclusive NOR of the horizontal synchronization signal (AFC) and CSYNC (sync
separator). The output polarity can be selected (metal option). Also functions as general
output port (command switch).
Power supply connection (+5 V: digital system power supply)
HT-R640
Page 84
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -25
Q7003: M66005 (FL Tube Driver)
BLOCK DIAGRAM
HT-R640
CS
SCK
SDATA
XIN
XOUT
RESET
Vcc1
Vcc2
Vss
Vp
14
15
16
21
20
13
19
60
22
32
Serial
receive
circuit
Clock
generator
data
timing
clock
Display code RAM
Bank 1 : 8bit x 16
Bank 2 : 8bit x 64
code
write
Code/
command
control
circuit
Display
controller
dot data
write
code
select
CGROM
(35bit x 160)
CGRAM
(35bit x 16)
scan pulse
SEG00
59
33
Segment
output
circuit
Segment/
Digit
select/
output
circuit
Digit
output
circuit
2
SEG26
31
SEG27
24
SEG34
SEG35
23
64
DIG12/SEG36
63
DIG13/SEG37
62
DIG14/SEG38
61
DIG15/SEG39
12
DIG00
1
DIG11
P0
18
P1
17
TERMINAL DESCRIPTION
SYMBOLPIN NAME
13
14
15
16
21,
20
1~12
61~64
23~31
33~59
17, 18
19
60
22
32
RESETReset inputThis pin is used to initialize the internal state of the M66004.
CSChip select input
SCKShift clock inputAt the rising edge from "L" to "H", input data is shifted.
SDATASerial data inputCharacter code or command data to display is input from MSB.
XIN,
XOUT
DIG00 ~
Clock input
Clock output
Digit output
DIG15
SEG00 ~
Segment output
SEG39
P0, P1Output port (static operation)
VCC1
VCC2
VSSGND
VPNegative power supply for VFD drive.
DESCRIPTIONPIN NO.
"L" : Communication with the MCU is possible.
"H" : Any instruction from the MCU is neglected.
This pin is used to connect a resister and a capacitor externally to
set oscillation frequency.
These pins are used to connect to digit pins of VFD.
These pins are used to connect to segment pins of VFD.
Positive power supply for internal logic.
Positive power supply for high-pressure-resistant output port.
Page 85
HT-R640
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -26
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)
SYSTEM BLOCK DIAGRAM
Multi
Rin
Multi
Lin
Out L
for
ADC
Out R
for
ADC
Volume
Volume
Multi
SBLin
Multi
SBRin
Multi
Cin
Multi
SWin
Multi
SLin
Multi
SRin
Rch Tone
Bass&
Trebl
Bass&
Treble
Tone
Lch Tone
e
AGND
Volum
Volume
Volum
Volume
CLOCKDATA
MCU I/F
e
e
AVEE
Volume
Volume
Volume
Volume
Volume
Volume
AVCC
Lout
Rout
SBLout
SBRout
Cout
SWout
SLout
SRout
Lch
Rch
10
11
mono
10
11
REC
1
2
Input selector
3
4
5
6
7
8
9
1
2
Input selector
3
4
5
6
7
8
9
REC
SUB
Input
ATT
Input
ATT
SUB
Page 86
HT-R640
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -27
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)
BLOCK DIAGRAM AND PIN CONFIGURATION
DGND
DATA
CLOCK
AVEE
INR1
INL1
INR2
INL2
INR3
INL3
INR4
INL4
INR5
INL5
41
42
43
44
45
46
47
48
49
50
51
52
53
54
MONO
SUBL
ADCR
SUBR
ADCL
FRIN2
FLIN2
SRIN2
SLIN2
SWIN2
CIN2
SBRIN2
SBLIN2
40 39 3837 3635 3433 32 3130 2928 2726 25
ATT
0/-6/-12/-18dB
I/F
MCU
Bass/ Treble
MAIN
SUB
0~-95dB,
-
(1dBstep)
-14~+14dB
(2dB step)
Tone
Tone
Bass/ Treble
0~-95dB,
(1dBstep)
-
-14~+14dB
(2dB step)
+16~-95dB,
- (1dBst
+16~-95dB,
- (1dBst
ep)
+16~-95dB,
-(1dBstep)
ep)
TRER
+16~0dB
(1dBstep)
BASSR2
+16~0dB
(1dBstep)
BASSR1
AVCC
AVCC
24
23
TREL
22
BASSL2
21
BASSL1
FRC
20
FROUT
19
AGND
18
FLOUT
17
FLC
16
6-C
15
6-OUT (SR OUT)
14
AGND
13
5-OUT (SL OUT)
12
5-C
11
INR6
INL6
INR7
INL7
INR8
INL8
INRA/RECR1
INLA/RECL1
INR9
INL9
55
56
57
58
59
60
61
62
63
64
+16~-95dB,
ep)
- (1dBst
+16~-95dB,
- (1dBst
ep)
+16~-95dB,
ep)
- (1dBst
REC
65 66 6768 6970 7172 73 7475 7677 7879 80
CIN1
FRIN1
SWIN1
SLIN1
SRIN1
SBLIN1
INRB/RECR2
INLB/RECL2
INR10/RECR4
INL10/RECL4
INR11/RECR5
RECR3
INL11/RECL5
RECL3
FLIN1
SBRIN1
4-C
10
4-OUT (SW OUT)
9
AGND
8
3-OUT (C OUT)
7
3-C
6
2-C
5
2-OUT (SBR OUT)
4
AGND
3
1-OUT (SBL OUT)
2
1-C
1
Page 87
HT-R640
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -28
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)
Frequency characteristic setting pin of L/R channel tone control (Treble)
Frequency characteristic setting pin of L/R channel tone control (Bass
Positive power supply to internal circ
Input pin of L/R/C/SW/SL/SR/SBL/SBR channel (Multi IN 1/2)
uit
e
)
41DGND
42DATA
43CLOCKInput pin of control clock
44
46,48,50,
52,54,56,
58,60,64
45,47,49,
51,53,55,
57,59,63
40
38,39SUBL,SUBR
36,37ADCL, ADCR
72
71RECR3
61,62,
65,66,
67,68,
69,70
AVEE
INL1,INL2, INL3,
INL4,INL5,INL6,
INL7,INL8,INL9
INR1,INR2, INR3,
INR4,INR5,INR6,
INR7,INR8,INR9
MONO
RECL3
INRA/RECR1,INLA/RECL1,
INRB/RECR2,INLB/RECL2,
INR10/RECR4,INL10/RECL4,
INR11/RECR5,INL11/RECL5
Digital ground of internal ci
Input pin of control data
Negative power supply to internal circ
Input pin of L/R channel (Input Selector)
Input pin of monaural (Input Selector)
Output pin for L/R channel SUB Outpu
Output pin for L/R channel ADC
Output pin for L/R channel REC Output
Input pin of L/R channel (Input Selector)/
Output pin for L/R channel REC Outpu
rcuit
uit
t
t
Page 88
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -29
Q8401 : SiI9030CTU (HDMI Transmitter)
BLOCK DIAGRAM
HT-R640
CSDA
CSCL
CI2CA
R
ESET
IDCK
D[23:0]
HSYNC
VSYNC
SPDIF
MC
SCK
SD[3
DE
LK
WS
:0]
I2C
Sla
ve
Registers
E-DDC
er
Mast
DSDA
DSCL
INT
----------- ---- -
Configuration
#
Logic Bl
oc
k
Video Data
Capture /
DE Gen /
4:2:2 to
4:4:4
656
Logic
ck
Blo
control signals
Audio Data
audio data
Receiver Sense + Interrupt Logic
HDCP
Encryption
Engine
CSCXOR
HDCP
Keys
EEPR
encrypted
data
PanelLink
OM
TMDS
Digital
Core
HPD
EXT_SWIN
TXC±
TX0±
TX1±
TX
2±
Capture
Logic
ck
Blo
SYSTEM APPLICATION
DDC
DDC
TMDS
HDMI Connector Port 0
TMDS
DDC
DDC
HDMI Connector Port 1
EDID
HDMI
RECEIVER
SiI9033
EDID
Micro-
controller
Other Au
dio Sources
0
Digital Video
DSD
I2S
SPDIF
MCLK
1
I2C
Audio DSP
TRANSMITTER
I2S
I2S
SiI9030
Audio DAC
HDMI
TMDS
DDC
HDMI Connector
Amplifier
Page 89
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -30
Q8401 : SiI9030CTU (HDMI Transmitter)
PIN CONFIGURATION
AGND
TXC-
TXC+
AVCC
TX0-
TX0+
AGND
TX1-
TX1+
AVCC
TX2-
TX2+
AGND
PVCC2
CI2CA
RESET#
CSCL
CSDA
CVCC18
CGND
IOGND
IOVCC
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
CVCC18
CGND
41
42
43
44
45
46
47
48
49
51
52
53
54
55
56
57
58
59
60
50
NC
40
61
PGND2
39
62
38
63
37
64
36
65
35
66
31
32
33
34
SiI 9030
80-Pin TQFP
(Top View)
67
68
69
70
30
71
29
72
28
73
27
74
26
75
25
76
EXT_SWING
24
77
PVCC1
23
78
PGND1
22
79
RSVDL
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
80
HT-R640
DSCL
DSDA
HPD
INT
CVCC18
CGND
IOGND
IOVCC
SCK
WS
SD0
SD1
SD2
SD3
MCLK
SPDIF
CVCC18
CGND
VSYNC
HSYNC
D8
D7
D6
D13
D12
D11
D9
D10
IDCK
D5
IOVCC
CGND
IOGND
D4
D3
D2
D1
D0
DE
CVCC18
Page 90
y
y
g
g
p
p
pply
g
g
p
g
g
y
g
pply
g
g
g
g
g
pply
g
g
pply
g
g
p
pply
g
g
p
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -31
Q8401 : SiI9030CTU (HDMI Transmitter)
TERMINAL DESCRIPTION
Pin # Pin NameI/O DescriptionUse
1HSYNCI Horizontal S
2VSYNCIVertical S
3CGNDDi
4CVCC18Di
5SPDIFIS/PDIF Audio in
6MCLKI Audio In
7SD3II2S Serial DataVideo and Audio
8SD2II2S Serial DataVideo and Audio
9SD1II2S Serial DataVideo and Audio
10 SD0I I2S Serial DataVideo and Audio
11 WSI I2S Word SelectVideo and Audio
12 SCKI I2S Serial ClockVideo and Audio
13 IOVCCIO Pin VCC. Connect to 3.3V su
14 IOGNDIO Pin GND.Ground
15 CGNDDi
16 CVCC18Di
17 INTO Interru
18 HPDIHot Plug Detect Input.Confirration/Programmin
19 DSDAI/O DDC dataControl
20 DSCLI/O DDC ClockControl
21 RSVDLIReserved for use b
22 PGND1TMDS Core PLL Ground.Ground
23 PVCC1TMDS Core PLL Power. Connect to 3.3V su