OLYMPUS C-770 UZ DESCRIPTION OF MECHANISM

C-770Ultra Zoom

H. DESCRIPTION OF MECHANISM

[1] CA1 AND PART OF CP1 CIRCUIT DESCRIPTION ............................................... H-2

[2] CP1 CIRCUIT DESCRIPTION ................................................................................ H-5

[3] PW1 POWER CIRCUIT DESCRIPTION ................................................................. H-6

[4] ST1 STROBE CIRCUIT DESCRIPTION................................................................. H-7

[5] SYA CIRCUIT DESCRIPTION........................................................................... H-8~10

H-1 Ver.1

H. DESCRIPTION OF MECHANISM C-770Ultra Zoom

B

A

B

A

[1] CA1 and A PART OF CP1 CIRCUIT

DESCRIPTION

1. IC Configuration

IC903 (ICX498AON) CCD imager
IC991, IC992 (CDX3440EN) V driver
IC906 H driver, CDS, AGC, A/D converter

2. IC903 (CCD imager)

Interline type CCD image sensor

Image size Diagonal 6.667 mm

(1/2.7 type)
Pixels in total 2396 (H) x 1766 (V)
Recording pixels 2288 (H) x 1712 (V)

11

10

OUT

V

Ø3

Ø3

8

13

Ø1

V

ØRG

Ø2

V

7

6

Gb

R

Gb

R

Gb

R

Vertical register

Gb

R

14

15

GND

V

Horizontal register

GND

V

4

5

B

Gb

Gr

R

B

Gb

Gr

R

B

Gb

Gr

R

B

Gb

Gr

R

17

16

SUB

C

ØSUB

(Note) : Photo sensor

Ø4

V

3

18

Ø5

Ø5

V

B

Gr

B

Gr

B

Gr

B

Gr

L

V

V

2

(Note)

19

Ø1

H

20

Ø6

V

1

Ø2

H

hld

st

V

V

9

12

DD

V

Fig. 1-1. CCD Block Diagram

Pin No.

1

2

3

4

5

6

7

8

9

10

Symbol

Vφ
Vφ5B
Vφ5A

Vφ4
Vφ3B
Vφ3A

Vφ2

Vφ1

VST

VHLD

Pin Description

6

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Storage gate

Hold gate

Pin No.

11

12

13

14

15

16

17

18

19

20

Symbol

V

OUT

VDD

φRG

GND

GND

φSUB

CSUB

V

L

Hφ1
Hφ2

Pin Description

Signal output

Circuit power

Reset gate clock

GND

GND

Substrate clock

Substrate bias

Protection transistor bias

Horizontal register transfer clock

Horizontal register transfer clock

Table 1-2. CCD Pin Description

H-2 Ver. 1

C-770Ultra Zoom

X

X

X

X

E
)

C

K

H. DESCRIPTION OF MECHANISM

3. IC906 (H Driver) and IC991, IC992 (V Driver)

An H driver (a part of IC906) and V driver (IC991 and IC992)
are necessary in order to generate the clocks (vertical trans­fer clock, horizontal transfer clock and electronic shutter
clock) which driver the CCD.
IC906 has clock generating which drives horizontal CCD
and its drives function. These clocks are output from pin
(14), (15), (18) and (19) of IC906. In addition the XV1-XV6
signals which are output from IC101 are the vertical trans­fer clocks, and the XSG1A, XSG1B and XSG3A signals
which are output from IC102 is superimposed onto XV1,
XV3 and XV5 at IC904 in order to generate a ternary pulse.
In addition, the XSUB signal which is output from IC101 is
used as the sweep pulse for the electronic shutter, and the
RG signal which is output from pin (21) of IC906 is the re­set gate clock.

V

DD

XSUB

XSG1

XV1
XV2

SG3A

SG3B

1

Input Buffer

2
3
4
5
6

7

26
25

24
23
22
21
20

MOD
(High

SUB
V1
V2

VL
V3A
V3B

4. IC906 (CDS, AGC Circuit and A/D Converter)

The video signal which is output from the CCD is input to
pins (27) of IC906. There are S/H blocks inside IC905 gen­erated from the XSHP and XSHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 12-bit signal, and is then input to IC991 of the CP1 circuit
board. The gain of the AGC amplifier is controlled by pin
(31)-(33) serial signal which is output from IC991 of the
CP1 board.

VRB

VRT

VREF

INTERNAL

REGISTERS

SL

SCK

SDATA

12

DOUT

HBLK
CLP/PBL

CLI

12-BIT

ADC

CLAMP

VD

CDIN

RG

H1-H4

6~42 dB

0~18 dB

VGA

PxGA

CDS

INTERNAL

CLOCKS

HORIZONTAL

4

DRIVERS

AD9949

PRECISION

TIMING

CORE

SYNC

GENERATOR

HD

Fig. 1-4. IC906 Block Diagram

XV3

SG5A

XV5

SG5B

XV4
XV6

8

9
10
11
12

13

19
18
17

16

15
14

V5A
VH
V5B

V4
V6

VM

Fig. 1-3. IC991 and IC992 Block Diagram

H-3 Ver. 1

H. DESCRIPTION OF MECHANISM C-770Ultra Zoom

5. Transfer of Electric Charge by the Horizontal CCD

The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-

5. RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the
timing in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the
timing in (3), and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-6.

(1)

H1 H2 H1 H2 H1 HOG RG

CCD OUT

Floating diffusion

(2)

H1 H2 H1 H2 H1 HOG RG

PD

PD

CCD OUT

H1

H2

RG

13.5V

(1) (2) (3)

3.5V
0V

3.5V
0V

0V

(3)

H1 H2 H1 H2 H1 HOG RG

Reset gate pulse

Direction of transfer

H Register

Electric
charge

Floating diffusion gate is
floated at a high impedance.

CCD OUT

CCD OUT

Fig. 1-5. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage

12V Pre-charge drain bias (PD)

Voltage output

C is charged
equivalently

RG pulse leak signal

Signal voltage

Black level

Fig. 1-6. Theory of Signal Extraction Operation

H-4 Ver. 1

H. DESCRIPTION OF MECHANISMC-770Ultra Zoom

[2] CP1 CIRCUIT DESCRIPTION

1. Circuit description
1-1. Signal processor

γγ

1.

γ correction circuit

γγ

This circuit performs (gamma) correction in order to main­tain a linear relationship between the light input to the cam­era and the light output from the picture screen.

2. Color generation circuit

This circuit converts the CCD data into RGB signals.

3. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y
signals from the RGB signals.

4. Horizontal and vertical aperture circuit

This circuit is used gemerate the aperture signal.

1-2. AE/AWB and AF computing circuit

The AE/AWB carries out computation based on a 64-seg­ment screen, and the AF carries out computations based
on a 6-segment screen.

1-3. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for
controlling the SDRAM. It also refreshes the SDRAM.

1-4. SIO

This is the interface for the 8-bit microprocessor.

1-5. PIO/PWM/SIO for LCD

8-bit parallel input and output makes it possible to switch
between individual input/output and PWM input/output.

1-6. TG/SG

Timing generated for 4 million pixel CCD control.

1-7. Digital encorder

It generates chroma signal from color difference signal.

2. Outline of Operation

When the shutter opens, the reset signals (ASIC and CPU)
and the serial signals (“take a picture” commands) from
the 8-bit microprocessor are input and operation starts.
When the TG/SG drives the CCD, picture data passes
through the A/D and CDS, and is then input to the ASIC as
10-bit data.
The AF, AE, AWB, shutter, and AGC value are computed
from this data, and three exposures are made to obtain the
optimum picture. The data which has already been
stored in the SDRAM is read by the CPU and color genera­tion is carried out. At this time, correction of the lens distor­tion which is a characteristic of wide-angle lenses is car­ried out. After AWB and γ processing are carried out, a matrix
is generated and aperture correction is carried out for the Y
signal, and the data is then compressed by JPEG and is
then written to card memory (xD picture card).

When the data is to be output to an external device, it is
taken data from the memory and output via the USB. When
played back on the LCD and monitor, data is transferred
from memery to the SDRAM, and the image is then elon­gated so that it is displayed over the SDRAM display area.

3. LCD Block

LCD Block is in the CP1 board, and it is constructed by
LCD driver (IC801) and around circuits.
The video signal from the ASIC are converted into RGB
signals by the LCD driver, and these RGB signals and the
control signal which is output by the LCD driver are used to
drive the LCD panel. The RGB signals are 1H transposed
so that no DC component is present in the LCD element,
and the two horizontal shift register clocks drive the hori­zontal shift registers inside the LCD panel so that the 1H
transposed RGB signals are applied to the LCD panel. Be­cause the LCD closes more as the difference in potential
between the COM (common polar voltage: AC) and the R,
G and B signals becomes greater, the display becomes
darker; if the difference in potential is smaller, the element
opens and the LCD become brighter.

4. Lens drive block

4-1. Shutter drive

The shutter motor drive signal (SIN1 and SIN2) which is out­put from the ASIC (IC101) is drived the shutter constant level
driver (IC956), and then mecha shutter is opened and closed.
The current control signal (VCTRL) which is output from the
ASIC (IC101) is restricted the shutter electric current. (main­tenance electric current)

4-2. Iris drive

The iris stepping motor drive signals (IIN1, IIN2, IIN3 and
IIN4) which are output from the ASIC (IC101) are used to
drive by the motor driver (IC956). Detection of the standard
iris positions is carried out by means of the photointerruptor
(PI2) inside the lens block.

4-3. Focus drive

The focus micro stepping motor drive signals (FCW, FCLK
and FOB) which are output from the ASIC (IC101) are used
to drive by the motor driver (IC956). Detection of the stan­dard focusing positions is carried out by means of the
photointerruptor (PI) inside the lens block.

4-4. Zoom drive

The zoom stepping motor drive signals (ZIN1, ZIN2, ZIN3
and ZIN4) which are output from the ASIC (IC101) are used
to drive by the motor driver (IC956). Detection of the zoom
positions is carried out by means of photoreflector (PR1 and
PR2) inside the lens block.

H-5

Ver. 1

H. DESCRIPTION OF MECHANISM C-770UZ(U)

[3] PW1 POWER CIRCUIT DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the fol­lowing blocks.
Switching power controller (IC501)
Digital 5.1 V and analog system power output (T5001,
Q5001)
Digital 1.74 V power supply output (L5006)
Digital 3.25 V power supply output (L5005)
LCD system power supply output (Q5002, L5007)
Backlight power supply output (L5008)

2. Switching Power Controller (IC501)

This is the basic circuit which is necessary for controlling
the power supply for a PWM-type switching regulator, and
is provided with seven built-in channels, only CH1 (power
for IC start), CH2 (digital 3.25 V power supply output), CH3
(digital 1.74 V power supply output), CH5 (analog power
supply output) and 15.0 V (A) (CH5) are used. CH6 (LCD
power supply output), CH7 (backlight power supply output)
and CH4 are not used. Feedback from 6.0 V (D) (CH1),

3.25 V (D) (CH2), 1.54 V (D) (CH3), 15.0 V (A) and 12.0 V
(B) (CH6) power supply outputs are received, and the PWM
duty is varied so that each one is maintained at the correct
voltage setting level.
Feedback for the LCD backlight power (CH7) is provided to
the both ends voltage of registance so that regular current
can be controlled to be current that was setting.

3. Analog System Power Output

3.45 V (A), 15.0 V (A) and -7.5 V (A) are output. Feedback
for the 15.0 V (A) is provided to the switching controller (Pin
(53) of IC501) so that PWM control can be carried out.

4. Digital 1.74 V System Power Output

1.74 V (D) is output. Feedback for the 1.74 V (D) is pro­vided to the swiching controller (Pin (31) of IC501) so that
PWM control can be carried out.

5. Digital 3.25 V System Power Output

3.25 V (D) is output. Feedback for the 3.25 V (D) is pro­vided to the swiching controller (Pin (32) of IC501) so that
PWM control can be carried out.

6. LCD System Power Output

12.0 V is output. Feedback for the 12.0 V is provided to the
switching power controller (Pin (18) of IC501) so that PWM
control can be carried out.

7. Backlight Power Output

Regular current (15 mA) is being transmitted to LED for
LCD backlight. Feedback for the both ends voltage of
registance that is being positioned to in series LED are pro­vided to the switching controller (Pin (48) of IC501) so that
PWM control to be carried out.

2-1. Short-circuit protection circuit

If output is short-circuited for the length of time determined
by the condenser which is connected to Pin (42) of IC501,
all output is turned off. The control signal (P ON) are recon­trolled to restore output.

H-6 Ver. 1

H. DESCRIPTION OF MECHANISMC-770UZ

[4] ST1 STROBE CIRCUIT DESCRIPTION

1. Charging Circuit

When UNREG power is supplied to the charge circuit and
the CHG signal from microprocessor becomes High (3.3
V), the charging circuit starts operating and the main
electorolytic capacitor is charged with high-voltage direct
current.
However, when the CHG signal is Low (0 V), the charging
circuit does not operate.

1-1. Power supply filter

C5401 constitutes the power supply filter. They smooth out
ripples in the current which accompany the switching of the
oscillation transformer.

1-2. Oscillation circuit

This circuit generates an AC voltage (pulse) in order to in­crease the UNREG power supply voltage when drops in
current occur. This circuit generates a drive pulse with a
frequency of approximately 50-100 kHz. Because self-ex­cited light omission is used, the oscillation frequency
changes according to the drive conditions.

2. Light Emission Circuit

When RDY and TRIG signals are input from the ASIC ex­pansion port, the stroboscope emits light.

2-1. Emission control circuit

When the RDY signal is input to the emission control cir­cuit, Q5409 switches on and preparation is made to let cur­rent flow to the light emitting element. Moreover, when a
STOP signal is input, the stroboscope stops emitting light.

2-2. Trigger circuit

When each TRIG signal is input to the two trigger circuit
(TRIG W and TRIG T), D5405 and D5410 switch on, a high­voltage pulse of several kilovolts is generated inside the
trigger circuit, and this pulse is then applied to the light
emitting part.

2-3. Light emitting element

When the high-voltage pulse form the each trigger circuit is
applied to the two light emitting parts, currnet flows to the
light emitting element and light is emitted.

1-3. Oscillation transformer

The low-voltage alternating current which is generated by
the oscillation control circuit is converted to a high-voltage
alternating current by the oscillation transformer.

1-4. Rectifier circuit

The high-voltage alternating current which is generated at
the secondary side of T5401 is rectified to produce a high­voltage direct current and is accumulated at electrolytic ca­pacitor C5412 on the main circuit board.

1-5. Voltage monitoring circuit

This circuit is used to maintain the voltage accumulated at
C5412 at a constance level.
After the charging voltage is divided and converted to a
lower voltage by R5417 and R5419, it is output to the mi­croprocessor as the monitoring voltage VMONIT. When this
VMONIT voltage reaches a specified level at the SYA cir­cuit on the CP1 board, the CHG signal is switched to Low
and charging is interrupted.

Beware of electric shocks.

H-7 Ver. 1

H. DESCRIPTION OF MECHANISM C-770Ultra Zoom

[5] SYA CIRCUIT DESCRIPTION

1. Configuration and Functions

For the overall configuration of the SYA block, refer to the block diagram. The configuration of the SYA block centers around
a 8-bit microprocessor (IC301).
The 8-bit microprocessor handles the following functions.

1. Operation key input, 2. Clock control, 3. Power ON/OFF, 4. Storobe charge control

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 NOT USED

22 LCD ON

23 EVF BL

24

25 PRG SO

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41~46

Signal

AVR EF

AVSS

IC (FLMD0)

VDD

REGC

VSS

XIN

XOUT

RESET

XCIN

XCOUT

CLKSEL0

BAT_OFF

IR IN

USB CONNECT

RXD2

SREQ

BACKUP_CTL

NOT USED

FLMD1

LCD BL

PRG SI

PRG SCK

MAIN RESET

SELF_LED

CARD LED

AVREF ON

VSS

VDD

P ON

PA ON

SCK

SI

SO

CHG ON

FLMD0_SY

SCAN OUT 3~0, 4, 5

I/O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Outline

I

-

I

I

-

-

I

I

I

I

I

I

I

I

-

I

-

I

-

I

I

Analog standard voltage input terminal

GND

Power for program writing

VDD

Regulator output stability capacity connection

GND

Main clock oscillation terminal (4MHz)

Main clock oscillation terminal

Reset input

Clock oscillation terminal (32.768 kHz)

Clock oscillation terminal

PLL oscillation ON/OFF

Battery off detection signal input

Remote control detection signal

USB power detection terminal

External strobe connection detection

Serial communication requirement signal

Backup battery charge control (L= charge)

-

Power for program writing

-

D/D converter (LCD system) ON/OFF signal

EVF backlight ON/OFF signal

LCD backlight ON/OFF signal

Flash for serial data output

Flash for serial data input

Flash for serial clock output

System reset (MRST)

Self-timer LED (L = Lighting)

Card access LED (L = Lighting)

AD VREF ON/OFF signal

GND

VDD

D/D converter (digital system) ON/OFF signal

D/D converter (analog system) ON/OFF signal

Serial clock output

Serial data input

Serial data output

Strobe charge control

Port for 8-bit rewriting

Key matrix output

H-8

Ver. 1

H. DESCRIPTION OF MECHANISMC-770UZ(U)

47

48

49

50

51~56

57

58

59

60

61

62

63

64

PLLEN

NOT USED

COMREQ

ASIC TEST

SCAN IN 5~0

CARD SW

ZJACK IN

NOT USED -

xD CARD

TEMP

DC IN

CHG VOL

BATTERY

Table 5-1. 8-bit Microprocessor Port Specification

O PLL oscillation ON/OFF

-

O

O

I

I

I

I

I

I

I

I

-

ASIC serial communication requirement

ASIC control signal (ZTEST)

Key matrix input

Card lid switch detection (L= detection)

AV JACK detection (L= detection)

-

xD card detection signal (L= detection)

Temperature detection

DC JACK detection

Main capacitor charge voltage detection

Battery voltage detection

2. Internal Communication Bus

The SYA block carries out overall control of camera operation by detecting the input from the keyboard and the condition of
the camera circuits. The 8-bit microprocessor reads the signals from each sensor element as input data and outputs this data
to the camera circuits (ASIC) or to the LCD display device as operation mode setting data. Fig. 5-1 shows the internal
communication between the 8-bit microprocessor and ASIC.

8-bit micro processor ASIC

setting of
external port

communi­cation

MRST

ZTEST

PLLEN

CLKSEL0

SI

SO

SCK

SREQ

COMREQ

Fig. 5-1 Internal Bus Communication System

H-9

Ver. 1

H. DESCRIPTION OF MECHANISM C-770Ultra Zoom

3. Key Operaiton

For details of the key operation, refer to the instruction manual.

SCAN

SCAN
OUT

IN

0

1

2

0

NIGHT SCENE

PORTRAIT

↑

SELF PORTRAIT

123

My

AUTO

OK

SPORTS

↓

A/S/M

COMMEMORA-

TIVE

→

4

P

LANDSCAPE

QV

5

←

3

4

5

WIDE TELE

AEL/CUSTOM

FLASH

Table 5-2. Key Operation

PLAY REC

1st

LCD

2nd

SELF

MOVIE

OFF POP UP

TEST

4. Power Supply Control

The 8-bit microprocessor controls the power supply for the overall system.
The following is a description of how the power supply is turned on and off. When the battery is attached, IC961 is operating
and creating 3.7 V (POWER ON: 3.7 V → 4.7 V), a regulated 3.2 V voltage is normally input to the 8-bit microprocessor
(IC301) by IC652, clock counting and key scanning is carried out even when the power switch is turned off, so that the
camera can start up again.
When the power switch is off, the 8-bit microprocessor halts 4 MHz of the main clock, and operates 32.768 kHz of subclock.
When the battery is removed, the 8-bit microprocessor power switches the capacitor for memory backup by IC652, and
operates at low consumption. At this condition, the 8-bit microprocessor halts 4 MHz of the main clock, and operates clock
counting by 32.768 kHz of sub clock.
Also, the battery for backup is charged 16 hours from it to be attached.
When the power switch is on, the 8-bit microprocessor starts processing. The 8-bit microprocessor first sets both the PON
signal at pin (34) and the PAON signal at pin (35) to High, and then turn on the power circuit. After PON signal is to High, sets
external port of ASIC after approximately 100 ms. According to setting of this external port, carry out setting of the operating
frequency and oscillation control in the ASIC. Also, it starts communication with ASIC, and confirms the system is operative.
When the through image is operating, set the PAON signal to High and then turn on the CCD. When the through image is
playing, set the PAON signal to Low and then turn off the CCD. When LCD panel turns on, set LCD ON signal at pin (22) to
High, and then turn on the power. Set LCD BL signal at pin (24) to High, and turn on the backlight power.
When the power switch is off, the lens will be stowed, and PON, PAON, LCDON and LCD BL signals to Low and the power
supply to the whole system is halted. The 8-bit microprocessor halts oscillation of the main clock, and set operation mode of
clock ocillation.

Power supply voltage

Power OFF

Playback mode

Shooting mode (LCD)

Shooting mode (OVF)

Shooting

USB connection

ASIC,

memory

1.74 V, 3.3 V

OFF

ON

ON

ON

ON

ON

Table 5-3. Power supply control

H-10

CCD

15 V, -7.5 V

3.45 V

OFF

OFF

OFF

OFF

ON

OFF

8bit

CPU

3.2 V

32KHz

4MHz

4MHz

4MHz

4MHz

4MHz

LCD

MONITOR

12 V, 3.0 V

OFF

ON

ON

OFF

ON

OFF

Ver. 1