OLYMPUS C-770 UZ DESCRIPTION OF MECHANISM
C-770Ultra Zoom
H. DESCRIPTION OF MECHANISM
[1] CA1 AND PART OF CP1 CIRCUIT DESCRIPTION ............................................... H-2
[2] CP1 CIRCUIT DESCRIPTION ................................................................................ H-5
[3] PW1 POWER CIRCUIT DESCRIPTION ................................................................. H-6
[4] ST1 STROBE CIRCUIT DESCRIPTION................................................................. H-7
[5] SYA CIRCUIT DESCRIPTION........................................................................... H-8~10
H-1 Ver.1
H. DESCRIPTION OF MECHANISM C-770Ultra Zoom
B
A
B
A
[1] CA1 and A PART OF CP1 CIRCUIT
DESCRIPTION
1. IC Configuration
IC903 (ICX498AON) CCD imager
IC991, IC992 (CDX3440EN) V driver
IC906 H driver, CDS, AGC, A/D converter
2. IC903 (CCD imager)
Interline type CCD image sensor
Image size Diagonal 6.667 mm
(1/2.7 type)
Pixels in total 2396 (H) x 1766 (V)
Recording pixels 2288 (H) x 1712 (V)
11
10
OUT
V
Ø3
Ø3
8
13
Ø1
V
ØRG
Ø2
V
7
6
Gb
R
Gb
R
Gb
R
Vertical register
Gb
R
14
15
GND
V
Horizontal register
GND
V
4
5
B
Gb
Gr
R
B
Gb
Gr
R
B
Gb
Gr
R
B
Gb
Gr
R
17
16
SUB
C
ØSUB
(Note) : Photo sensor
Ø4
V
3
18
Ø5
Ø5
V
B
Gr
B
Gr
B
Gr
B
Gr
L
V
V
2
(Note)
19
Ø1
H
20
Ø6
V
1
Ø2
H
hld
st
V
V
9
12
DD
V
Fig. 1-1. CCD Block Diagram
Pin No.
1
2
3
4
5
6
7
8
9
10
Symbol
Vφ
Vφ5B
Vφ5A
Vφ4
Vφ3B
Vφ3A
Vφ2
Vφ1
VST
VHLD
Pin Description
6
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Storage gate
Hold gate
Pin No.
11
12
13
14
15
16
17
18
19
20
Symbol
V
OUT
VDD
φRG
GND
GND
φSUB
CSUB
V
L
Hφ1
Hφ2
Pin Description
Signal output
Circuit power
Reset gate clock
GND
GND
Substrate clock
Substrate bias
Protection transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
Table 1-2. CCD Pin Description
H-2 Ver. 1
C-770Ultra Zoom
X
X
X
X
E
)
C
K
H. DESCRIPTION OF MECHANISM
3. IC906 (H Driver) and IC991, IC992 (V Driver)
An H driver (a part of IC906) and V driver (IC991 and IC992)
are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter
clock) which driver the CCD.
IC906 has clock generating which drives horizontal CCD
and its drives function. These clocks are output from pin
(14), (15), (18) and (19) of IC906. In addition the XV1-XV6
signals which are output from IC101 are the vertical transfer clocks, and the XSG1A, XSG1B and XSG3A signals
which are output from IC102 is superimposed onto XV1,
XV3 and XV5 at IC904 in order to generate a ternary pulse.
In addition, the XSUB signal which is output from IC101 is
used as the sweep pulse for the electronic shutter, and the
RG signal which is output from pin (21) of IC906 is the reset gate clock.
V
DD
XSUB
XSG1
XV1
XV2
SG3A
SG3B
1
Input Buffer
2
3
4
5
6
7
26
25
24
23
22
21
20
MOD
(High
SUB
V1
V2
VL
V3A
V3B
4. IC906 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
pins (27) of IC906. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 12-bit signal, and is then input to IC991 of the CP1 circuit
board. The gain of the AGC amplifier is controlled by pin
(31)-(33) serial signal which is output from IC991 of the
CP1 board.
VRB
VRT
VREF
INTERNAL
REGISTERS
SL
SCK
SDATA
12
DOUT
HBLK
CLP/PBL
CLI
12-BIT
ADC
CLAMP
VD
CDIN
RG
H1-H4
6~42 dB
0~18 dB
VGA
PxGA
CDS
INTERNAL
CLOCKS
HORIZONTAL
4
DRIVERS
AD9949
PRECISION
TIMING
CORE
SYNC
GENERATOR
HD
Fig. 1-4. IC906 Block Diagram
XV3
SG5A
XV5
SG5B
XV4
XV6
8
9
10
11
12
13
19
18
17
16
15
14
V5A
VH
V5B
V4
V6
VM
Fig. 1-3. IC991 and IC992 Block Diagram
H-3 Ver. 1
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