Copyrightã 2001 Nokia Corporation All Rights Reserved
Page 4
Programmes After Market Services
This document is intended for use by qualified service personnel only.
Company Policy
Our policy is of continuous development; details of all technical modifications will be
included with service bulletins.
While every endeavour has been m ade to ensure the accuracy of this document, some
errors may exist. If any errors are found by the reader, NOKIA MOBILE PHONES Ltd.
should be notified in writing.
Please state:
Technical Documentation
IMPORTANT
Title of the Document + Issue Number/Date of publication
Latest Amendment Number (if applicable)
Page(s) and/or Figure(s) in error
Please send to: Nokia Mobile Phones Ltd.
PAMS Technical Documentation
PO Box 86
FIN-24101 SALO
Finland
Issue 1 10/01
Copyrightã 2001 Nokia Corporation All Rights Reserved
Page 5
Programmes After Market Services
Technical Documentation
Warnings and Cautions
Please refer to the phone's user guide f or instructions relating to operation, care and
maintenance including important safety information. Note also the following:
Warnings:
1. CARE MUST BE TAKEN ON INSTALLATION IN VEHICLES FITTED WITH ELECTRONIC ENGINE MANAGEMENT SYSTEMS AND ANTI-SKID BRAKING SYSTEMS. UNDER CERTAIN FAULT CONDITIONS, EMITTED RF ENERGY CAN
AFFECT THEIR OPERATION. IF NECESSARY, CONSULT THE VEHICLE DEALER/
MANUFACTURER TO DETERMINE TH E IMMUNITY OF VEHICLE ELECTRONIC
SYSTEMS TO RF ENERGY.
2. THE HANDPORTABLE TELEPHONE MUST NOT BE OPERATED IN AREAS LIKELY
TO CONTAIN POTENTIALLY EXPLOSIVE ATMOSPHERES EG PETROL STATIONS
(SERVICE STATIONS), BLASTING AREAS ETC.
3. OPERATION OF ANY RADIO TRANSMITTING EQUIPMENT, INCLUDING CELLU-
Cautions:
1. Servicing and alignment must be undertaken by qualified personnel only.
2. Ensure all work is carried out at an anti-static workstation and that an anti-
3. Ensure solder, wire, or foreign matter does not ent er the te lephone as dam-
4. Use only approved components as specified in the parts list.
5. Ensure all components, modules screws and insulators are corre ctly re-fit-
LAR TELEPHONES, MAY INTERFERE WITH THE FUNCTIONALITY OF INADEQUATELY PROTECTED MEDICAL DEVICES. CONSULT A PHYSICIAN OR THE
MANUFACTURER OF THE MED ICAL DEVICE IF YOU HAVE ANY QUESTIONS.
OTHER ELECTRONIC EQUIPMENT MAY ALSO BE SUBJECT TO INTERFERENCE.
static wrist strap is worn.
age may result.
ted after servicing and alignmen t. Ensure all cables a nd wires are repositioned correctly.
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Copyrightã 2001 Nokia Corporation All Rights Reserved
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Copyrightã 2001 Nokia Corporation All Rights Reserved
Fig 9 Top View of Production Test Pattern.........................................................................23
Fig 10 Test points Located Between UEM and UPP...........................................................24
Fig 11 RF Frequency Block Plan.........................................................................................43
Fig 12 Power distribution ....................................................................................................44
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Abbreviations
ACCHAnalog Control Channel
A/DAnalog to Digital conversion
AMPSAdvanced Mobile Phone System
ANSIAmerican National Standards Institute
ASICApplication Specific Integrated Circuit
AVCHAnalog V oice Channel
BBBase Band
CSDCircuit Switched Data
CSPChipped Scale Package. The same as uBGA.
CTIACellular Telecommunications Industry Association
D/ADigital to Analog conversion
DCCHDi gi tal Control Channel
DSPDigital Signal Processing
DTCHDigital Traffic Channel
EDMSEl ectronic Data Management System
EFREnhanced Full Rate (codec)
FCCFederal Communications Commission
IRInfrared
IrDAInfrared Data Association
IrMCInfrared Mobile Communications
IrOBEXIrDA Object Exchange Protocol
ISInterim Standard
ISAIntelligent Software Architecture
LEDLight Emitting Diode
MCUMicro Control Unit / Master Control Unit
MO/MTMobile Originated/Mobile Terminated (SMS)
OOROut Of Range (mode)
OTAOver The Air (+ service like Programming etc.)
PCPersonal Computer (PC Suite = PC program for phone memory function support)
PWBPrinted Wired Board
PWMPulse Width Modulation
RFRadio Frequency
SARSpecific Absorption Rate
SCFSoftware Component Factory
SMDSurface Mount Device
SMSShort Message Service
SPRStandard Product Requirement
TDDText Device for the Deaf
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TDMATime Division Multiple Access. Here: US digital cellular system.
TIATelecommunications Industry Association
TTYTeletype
UEMUniversal Energy Management, a Baseband ASIC.
UPPUniversal Phone Processor, a Baseband ASIC.
VCTCXOVol tage Controlled temperature Compensated Crystal Oscill ator
WAPWireless Application Protocol (Browser)
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1
2
3
4
5
7
8
System ModulePAMS Technical Documentation
Transceiver NPC-1
Introduction
The NPC-1 is a single band transceiver unit designed for TDMA800 networks. The transceiver consists of the engine module (WS8) and the various assembly parts.
The transceiver has a full graphic display and the user interface is based o n a jack style
UI with two soft keys. An internal antenna is used in the phone, and there is no connection to an external antenna. The transceiver also has a low leakage tolerant earpiece and
an omnidirectional microphone that provides excellent audio quality.
An integrated infrared (IR) link provides connec tion between two NPC-1 transcei vers or
between a transceiver and a PC (internal da ta), or a transceiver and a printer.
Figure 1: Interconnect ing Diagram
TRANSCEIVER
ANT
EXT
RF
Ostrich
LCD DRIVER
B & W
display
BACKLIGHT
BACKLIGHT
✉
RF
☎
6
9
0#
ENGINE
BB
USER INTERFACE
EARPIECE
AUDIO
(discr)
BUZZER
VIBRA
RTC
BACK-UP
BSI
BTemp
MIC
Ext. Aud io
Accessories
BATTER Y
JTAG
Prod.TEST I/F
INF R A R E D
Module
CHARGER
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Operational Modes
Below is a list of the phone’s different ope rational modes:
1Power Off mode
2Normal Mode (include various Active and Idle states):
•Analog Modes (800 MHz only):
•Analog Control Channel, ACCH
•Analog Voice Channel, AVCH
•Digital Modes (800 MHz):
•Control Channel, DCCH
•Digital Voice Channel, S-DTCH
•Digital Data Channel, D-DTCH
3Sleep and OOR modes (both Analog and Digital)
4Local mode
5Test mode
Environmental Specifications
Normal and extreme voltages
Voltage range:
•nominal battery voltage: 3.6 V
•maximum battery voltage: 5.0 V
•minimum battery voltage: 3.1 V
Temperature Conditions
Temperature range:
•ambient temperature: -30 - + 60 ×C
•PWB temperature: -30 - +85 ×C
•storage temperature range: -40 - + 85 ×C
All of the EIA/TIA-136-270A requirements are not exactly specified over the temperature
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range. For example, the RX sensitivity requirement is 3dB lower over the –30 - +60 °C
range.
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V
A
y
UI
T
T
A
X
X
PAMS Technical DocumentationSystem Module
Engine Module
Baseband Module
The core part of the transceiver’s baseband (figure 1) consists of 2 ASICs, the UEM and
UPP, and flash memory. The following sections illustrate and explain these parts in detail.
Figure 2: System Block Diagram (simple)
PA suppl
SAFARI
RFIC CTRL
RFCLK
19.44MHz
UPP
MEMADDA
MEMCON
FLASH
RF Supplies
RF RX/T
PURX
RF RX/T
SLEEPCLOCK
32kHz
CBUS/DBUS
UDIO
BB Supplies
KLIGHT/ DLIGH
PWR ON
BASEBAND
UEM
EXTERNAL AUDIO
CHARGER CONNECTION
IR
EAR
MIC
BUZZER
IBR
BATTERY
System Connector
UEM
Introduction to UEM
UEM is the Universal Energy Management IC for digital hand portable phones. In addition to energy management, it performs all the base band’s mixed-signal functions.
Most UEM pins have 2kV ESD protection, and those signals considered to be more easily
exposed to ESD, have 8kV protection within the UEM. These kinds of signals are (1) all
audio signals, (2) headset signals, (3) BSI, (4) Btemp, (5) Fbus and (6) Mbus signals.
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Regulators
The UEM has six regulators for baseband power supplies and seven regulators for RF
power supplies. The VR1 regulator has two outputs: (1) VR1a and (2) VR1b. In addition to
these, there are two current generators - IPA1 and IPA2 - for biasing purposes.
A bypass capacitor (1uF) is required for each regulator output to ensure stability.
Reference voltages for regulat ors require exter nal 1uF capacitors. Vref25RF is the refer-
ence voltage for the VR2 regulator, Vref25BB is the reference voltage for the VANA,
VFLASH1, VFLASH2, VR1 regulators, Vref278 is the re ference voltage for the VR3, VR4,
VR5, VR6, VR7 regulators, and VrefRF01 is the reference voltage for the VIO, VCORE regulators and for the radio frequency (RF).
40mAmax
VSim: 1.8/3.0V 25mAmaxVR3:2.7 8V 20m A
VIO: 1.8Vtyp
150mAmax
Vcore: 1.0-1.8V
200mAmax
VR2:2.78V 100mAmax
VR4: 2.78V 50mAmax
VR5: 2.78V 50mAmax
VR6: 2.78V 50mAmax
VR7: 2.78V 45mAmax
IPA1: 0-5mA
The VANA regulator supplies the baseband’s (BB) internal and ex ternal analog circuitry.
It is disabled in the Sleep mode.
The Vflash1 regulator supplie s the LCD, the IR-module and the digital parts of th e UEM
and Safari asic. It is enabled during startup an d goes into the low Iq-mode when in the
Sleep mode.
The VIO regulator supplies both the external and internal l ogic circuitries. It is used by
the LCD, flash, bluetooth and UPP. The regulator goes into the low Iq-mode when in theSleep mode.
The VCORE regulator supplies the D SP and the core part of the U PP. The voltage is programmable and the startup default is 1.5V. The regulator goes into the low Iq-mode
when in the Sleep mode.
The VSIM regulator supplies the SIM card. NOT USED IN NPC-1.
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The VR1 regulator uses two LDO s and a charge pump. The charge pump requires one
external 1uF capacitor in the Vpump pin and a 220nF flying capacitor between the CCP
and CCN pins. In practice, the 220nF flying capacitor is f ormed by 2 x 100nF capacitors
that are parallel to each other. The VR1 regulator is used by the Safari RF ASIC.
The VR2 regulator is used to supply the (1) external RF parts, (2) lower band up converter, (3) TX power detector module and (4) Safari. In light load situatio ns, the VR2 regulator can be set to the low Iq-mode.
The VR3 regulator supplies the VCTCXO and Safari in the RF. It is always enabled when
the UEM is active. When the UEM is in the Sleep mode, the VR3 is disabled.
The VR4 regulator supplies the RX frontends (LNA and RX mixers).
The VR5 regulator supplies the lower band PA. In light load situations, the VR5 regulator
can be set to the low Iq-mode.
The VR6 regulator supplies the higher band PA and TX amplifier. In light load situations,
the VR6 regulator can be set to the low Iq-mode.
The VR7 regulator supplies the VCO and Safari. In light load situations, the VR7 regulator
can be set to the low Iq-mode.
The IPA1 and IPA2 are programmable current gener ators. A 27kW/1%/100ppm external
resistor is used to improve the accuracy of the output current. The IPA1 is used by the
lower PA band and IPA2 is used by the higher PA band.
RF Interface
The interface between the baseband and the RF section is also handled by the UEM. It
provides A/D and D/A conversion of the in-pha se and quadrature receive and transmit
signal paths. It also provides A/D and D/ A conve rsions of receiv ed and transmitte d audio
signals to and from the UI section. The UEM supplies the analog AFC signal to the RF section, according to the UPP DSP digital control.
Charging Control
The CHACON block of the UEM asics controls charging. The needed functions for the
charging controls are the (1) pwm-controlled battery charging switch, (2) charger-monitoring circuitry, (3) battery voltage monitori ng circuitry and (4) RTC supply circuitry for
backup battery charging (Not used in NPC-1). In addition to these, external component s
are needed for EMC protection of the charger input to the baseband module.
Digital Interface
Data transmission between the U EM and the UPP is impleme nted using two seri al connections, DBUS (programmable clock) for DSP and CBUS (1.0MHz GSM and 1.08MHz
TDMA) for MCU. The UEM is a dual voltage circuit: the digital parts are run from 1.8V
and the analog parts are run from 2.78V. The Vbat (3,6V) voltage regulators's input is
also used.
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Audio Codec
The baseband supports two external microphone input ar eas and one external ea rphone
output. The input can be taken from an internal microphone, a headset microphone or
from an external microphone signal source through a headset connector. The output for
the internal earpiece is a dual-ended type output, and the dif ferential output is capable
of driving 4Vpp to the earpiece with a 60 dB minimum signal as the total distortion ratio.
The input and output signal source se lection and gain control is performed inside the
UEM Asic, according to the c ontrol messages from the UPP. A buzzer a nd an external
vibra alert control signal are gener ated by the UEM with separate PWM outputs.
UI Drivers
There is a single output driver for the buzzer, vibra, display and keyboard l eds an d the IR
in the side of the UEM. These generate PWM square wave for the various devices.
IR interface
The IR interface is designed and implemented into th e UEM. The low frequency mode of
the IR module covers speeds up to 115.2 kbit/s. The device (Vis hay) transceivers integrate
a sensitive receiver and a built-in power driver. The combination of a thin, long resistive
and inductive wiring should be avoided. The input (Txd, SD/M ode) and the output Rxd
should be directly coupled to the I/O circuit. The VBAT regulator supplies the power to
transmit the led and serial resistor limits’ current. Upon rece ivi ng infra red data to IR led,
it goes straight to the UEM via the RXD line . The Vflash1 is the power supply f or the IR
module, except for transmission.The IR module has one control pin to control the shut
down. The control lever shifter is used to change the proper voltage for shutdown to the
IR module from the UPP.
AD Converters
The UEM is equipped with a 11-channel analog to digital converter. Some AD converter
channels (LS, KEYB1-2) are not used in NPC-1. The AD converters are calibrated in the
production line.
UPP
Introduction
NPC-1 uses the UPPv4M ASIC. The RAM size is 4M. The processor architecture consists of
both the DSP and the MCU processors.
Blocks
The UPP is internally partitioned into two main parts: (1) the Brain and (2) the Body.
1The Processor and Memory System (that is, the Processor cores, Mega-cells,
internal memories, perip herals and external memory inter face) is known as the
Brain.
The Brain consists of the following blocks: (1) the DSP Subsystem (DSPSS), (2) the
MCU Subsystem (MCUSS), (3) the emulation control EMUCtl, (4) the program/
data RAM PDRAM and (5) the Brain Peripherals–subsystem (BrainPer).
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2The NMP custom cellular logic functions are known as the Body.
The Body contains interfaces and functions needed fo r interfacing other baseband and RF parts. The body consists of, fo r example, the following sub-blocks:
(1) MFI, (2) SCU, (3) CTSI , (4) RxModem, ( 5) Acc IF, (6) UIF, (7) C oder, (8) BodyIF, (9)
PUP.
Flash Memory
Introduction
The NPC-1 transceiver uses a 32 Mbit f lash as its external memory. The VIO regulator is
used as a power supply for normal in-system op eration. An accelerated program/erase
operation can be obtained by supplying Vpp of 12 volt to the flash device.
The device has two read modes: asynchronous and burst. The Burst read mode is utilized
in NPC-1, except for the start-up, when the asynchronous read mode is used for a short
time.
User Interface Hardware
LCD
Introduction
NPC-1 uses a black & white GD46 84x48 full dot matrix graphical display. There are two
suppliers for this LCD: Seiko Epson and P hilips. The LCD module includes the LCD glass,
the LCD COG-driver, an elastomer connector and a metal frame. The LCD module is
included in the lightguide assembly module.
Interface
The LCD is controlled by the UI SW and the control signals are from the UPP asic. The VIO
and Vflash1 regulators supply the LCD with power.
The LCD has an internal voltage booster and a booster capacitor is required between
Vout and GND.
Pin 3 (Vss9) is the LCD driver’s ground and Pin 9 (GND) is used to ground the metal
frame.
Keyboard
Introduction
The NPC-1 keyboar d styl e fol lows the Nokia Jack style , withou t side keys for vol ume co ntrol. The PWR key is integrated so that it is part of the IR window an d located on top of
the phone.
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Figure 3: Placement of keys.
Power Key
All signals for the keyboard come from the UPP asic, except PWRONX line for the power
key signal which is connect ed dir ectly to t he U EM. The pr essing o f the PWR k ey gro und s
the PWRONX line and the UEM generate s an inter rupt to U OO, which is then re cognized
as a PWR key press.
Keys
Other keys are detected so that w hen a key is pressed down, the metal dome connects
one S-line and one R-line of the UPP to the GND and creat es an interrupt for the SW.
This kind of detection is also known as metaldome detection. The matrix of how lines are
connected and which lines are used for differen t keys is described in the Table 1. The Sline S0 and R-line R5 are not used at all.
Table 2: Matrix of Key Detection Lines
S0S1S2S3S4
Returns /
Scans
R0NCNCSendEndNC
R1NCSoft leftUpDownSoft right
R2NC147*
R3NC2580
R4NC369#
R5NCNCNCNCNC
where NC = Not Connected
Lights
Introduction
NPC-1 has 10 LEDs for lighting purposes. Six of them are for the keyboard and four for
the display. The LED type is Osram LGM470, green light emitting and SMD through hole
mounted.
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Interfaces
The display lights are controlled by a Dlight signal from the UEM. The Dlight output is the
PWM signal, which is used to control the average current going through the LEDs. When
the battery voltage changes, the new PWM v alue is written onto the PWM register. In
this way, the brightness of the lights remains the same with all battery voltages within
range. The frequency of the signal is fixed at 128Hz.
The keyboard lights are controlled by the Klight signal from the UEM. The Klight output is
also a PWM signal and is used in the same way as Dlight.
Technical Information
Each LED requires a hole in t he PWB, in which the body of the LED locates in hole and
terminals are soldered on the component side of the module PWB. The LEDs have a white
plastic body around the diode, and this directs the emitted light better to the UI-side.
The current for the LCD lights is limited by the resistor between the Vbatt and LEDs. For
the keyboard lights there are resistors in parallel.
Vibra
Introduction
The vibra is located on the D-cover and is connected by spring connectors on the bottom
left-hand side of the engine. The vibra motor is supplied by Namiki.
Interfaces
The vibra is controlled by the PWM signal VIBRA from the UEM. With this signal, it is
possible to control both the frequency and pulse width of the signal. The pulse widt h is
used to control the current when the bat tery vol tage changes. Wit h the freque ncy control, it is possible to search for the optimum frequency to have silent and efficient vibrating.
Table 3: Electrical Parameters
ParameterRequirementUnit
Rated DC Voltage1.3V
Rated speed
Rated current
9500 ±3000
115 ±20
rpm
mA
Starting current
Armature resist ant8.6ohm
Rated DC voltage being able to use1.2 to 1.7V
Starting DC voltagemin. 1.2V
150 ±20
mA
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Audio HW
Earpiece
Introduction
The Philips Speaker System 13mm speaker capsule is used in NPC-1.
The speaker is a dynamic one. It is very sensitive and capable of producing relatively high
sound pressure also at low frequencies. The speaker capsule and the mechanics around it
together make the earpiece.
Microphone
Introduction
The microphone is an electret microphone with an omnidirec tional polar pattern. It consists of an electrically polarized membrane and a metal electrode which form a capacitor.
Air pressure changes (for example, sound) moves the membrane, which causes voltage
changes across the capacitor. Because the capacitance is t ypically 2 pF, a FET buffer is
needed inside the microphone capsule for the signal generated by the capacitor. Because
of the FET, the microphone needs a bias voltage.
The microphone manufacturers for the NPC-1 transceiver are Matsushita and Hosi den.
Buzzer
Introduction
The operating principle of the buzzer is magnetic. The diaphragm of the buzzer is made
of magnetic material and it is located in a magnetic f ield created by a perm anent magnet. The winding is not attached to the diaphragm, as is the case with the speaker. The
winding is located in the magnetic circuit so tha t it can alter the magnetic field o f the
permanent magnet, thus changing the magnetic force affecting the diaphragm. The
buzzer's useful frequency range is approximately from 2 kHz to 5kHz.
The Buzzer manufacturer for the NPC-1 transceiver is Star.
Battery
Phone Battery
Introduction
The BMC-2 battery (Ni-MH 640mAh) is be used in the NPC-1 transceiver by default. It is
also possible to use the BMC-3 (Ni-MH 900mAh) and BLC-2 (Li-ion 850mA) batteries.
Interface
The battery block contains NTC and BSI resistors for tempe rature measur emen t and battery identification. The BSI fixed resistor value indicates the chemistry and default
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Ni-MH
VBATT
GND
BTEMP
Battery
1 (+)
2(BSI)
3(BTEMP)
4(GND)
PAMS Technical DocumentationSystem Module
capacity of a battery. The NTC-resistor measures the battery temperature. Temperature
and capacity information is needed for charge control. These resistors are connected to
BSI and BTEMP pins of the battery connector. The phone has pull-up resistors for these
lines so that they can be re ad by A/D inputs in the phone (see the figure below). Serial
resistors in the BSI and BTEMP lines are f or ESD protection. Both lines also have spark
caps to prevent ESD.
Figure 4: Battery Connection Di agram
C220
1n
C217
1n
R202/1
100k
R205/1
10k
R205/2
10k
VFLASH1VANAVBAT
R202/4
100k
C100
10p
connector
BSI
OVERCHARGE/
OVERDISCHARGE
PROTECTION
The batteries have a specific red line, which indicates if the battery has been subjected to
excess humidity. The batteries are delivered in the protection mode, which gives longer
storage time. The voltage seen in the outer terminals is zero (or floating), and the battery
is activated by connecting the charge r. The battery has internal protection for overvoltage and overcurrent.
Figure 5: BMC-2 Battery contacts (BMC-3, BLC-2 have same interface).
Battery Connector
NPC-1 uses the spring type battery connector. This makes the phone easier to assemble
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in production and the connection between the battery and the PWB is more reliable. The
battery connector is manufactured by Molex.
Table 4: Battery Connector Interface
#Signal
name
1VBAT(+)
2BSIBSI
3BTEMPBTEMP
4GNDGNDGNDGND
Connected from - toBatt.
(batt.)
(batt.)
(batt.)
VBATI/OVbat3.0-5.1VBattery
UEMOutAnaBattery size
UEMOutAna40mA/
Accessories Interface
System connector
Introduction
NPC-1 uses accessories via a system connector.
I/O
Signal properties
A/D--levels--freq./timing
Gns
Switch
400mA
Description /
Notes
voltage
indicator
Battery
temperature
indicator
Ground
Interface
The interface is supported by fully differential 4-wire (XMICN, XMICP, XEARN and
XEARP) accessories. NPC-1 supports the HDC-5 headset, LPS-3 loopset and the PPH-1
car kit.
Figure 6: System Connector
GND
VIN
XMICN
XEARN
MICP
XMICP
XEARP
HEADINT
MICN
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An accessory is de tecte d by t he Head Int-lin e, whi ch is connect ed to the XEARP inside the
system connector. When an accessory is connected, it disconnects XEARP from HEADINT,
and the UEM detects it and generates an interrupt ( UEMINT) to the MC U. After that, the
HOOKINT line is used to determine which accessory is connected. This is done by the
voltage divider, which consists of the phone's internal pull-up and accessory-specific
pull-down. The voltage generated by this divider is then read by the ad- converter of
UEM. The HOOKINT- interrupt is generated by the button in the headset or by the accessory external audio input.
Figure 7: Accessory Detection / External Audio
2.7V
Hookint
/MBUS
EAD
HeadintHeadint
MIC1&3 Bias
MIC1P
MIC1N
HF
HFCM
3...25k
UEM
Technical Information
ESD protection is made up by (1) spark caps, (2) a buried capacitor (Z152 and Z154-157)
and (3) ±8kV inside the UEM. The RF and BB noises are prevented by inductors.
PPH-1 Handsfree
Introduction
2.1V
33N
0.8V
33N
1k2
1.8V
0.3V
1k2
The PPH-1 handsfree device
•provides the charging and handsfree functionality
•has a built-in speaker
•and uses a phone microphone, but also has a connector for t he HFM-8 optional
external microphone (using HFM-8 mutes phone microphone)
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Interface
A 4-wire interface is implemented with 2.5mm diame ter round plug/jack which is otherwise like a so-called standard stereo plug, but th e innermost contact is split into two.
Figure 8: 4-wire, fully differential headset connector pi n layo ut
2. XEAR N
4. XEAR P
5. H EADINT
3. XM IC P
1. XM IC N
IR module
Introduction
The IR module integrates a sensitive receiver and a built-in power driver complaint to the
IrDA 1.2 standard. The IR module is located at the top of the engine side, next to the
Power switch.
The IR module manufacturer for the NPC-1 transcei ver is Vishay.
Interface
The Vflash1 regulator supplies the IR module, except for the transmit LED. The transmit
LED is supplied by the VBAT regulator and the maximum current is limited by a se rial
resistor. The bypass capacitor is needed in the VBAT line for proper voltage. TXD and RXD
lines are connected to the UEM and shutdown is controlled by the UPP (GENIO(10))
through a level-shifter V350.
Technical Information
The IR interface is located in the UEM. The IR link supports speeds fr om 9600 bit/s to
1.152 MBit/s, up to 1m.
Charger IF
Introduction
The charger connection is implemente d through the system connector. The system connector supports charging with both plug chargers and desktop stand chargers.
There are three signals for charging. The cha rger GND pin is used for both desktop and
plug chargers as well as for charger voltage. The PWM cont rol line, which is needed for
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FBUS_TX
PAMS Technical DocumentationSystem Module
3-wire chargers, is connected directly to the GND in the PWB module, so the NPC-1
engine does not provide any PWM control for chargers. Charging controlling is done
inside the UEM by switching the UEM’s intern al charger switch on and off.
Interface
The fuse F100 protects the phone from too high currents, for example, when broken or
pirate chargers are used. L100 protects the engine from RF noises, which may occur in
the charging cable. V100 protects the UEM ASIC from reverse polarity charging voltage
and from too high charging voltages. C106 is also used for ESD and EMC protection.
Spark gaps right after the charger plug are used for ESD protection.
Test Interfaces
Production Test Pattern
The interface for NPC-1 production testing is a 5pin pad layout in the BB area (see the
figure below). The production tester conne cts to these pads by using spring connectors.
The interface includes the MBUS, FBUSRX, FBUSTX, VPP and GND signals. The pad size i s
1.7mm. The same pads are used also for AS test e quipment, such as the module jig and
the service cable.
Other Test Points
As BB asics and flash memory are CSP components, the visibility of BB signals is very
poor. This makes the measuring of most of the BB signals impossible. In order to debug
the BB, at least to some level, the most important signals can be accessed from the
0.6mm test points. The figure below shows the test points located between the UEM and
the UPP. There is an opening in the baseband shield to provide access to these pads.
Figure 9: Top View of Production Test Pattern
2.
3. FBUS_RX
7.
MBUS
8.
G ND
6.
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Figure 10: Test points Located Between UEM and UPP
UE M (D 200)
J414
EMC
General
The EMC performance of NPC-1’s baseband is improve d by using a shield to cover the
main components of the BB, such as the UEM, UPP and Flash. The UEM has internal protection against a ±8kV ESD pulse. The BB-shield is soldered to the PWB and it also
increases the rigidity of the PWB in the BB area, thus improving the phone’s reliability.
The shield also improves the thermal dissipation by spreading the heat more widely.
DBUSCLKDBUSDA
J403
J413
J402
PURXSLEEPX
SLEEPCLK
J404
J405
UEMINT
CBUSDA
J407
J415
DBUSEN1X
UPP (D400)
CBUSENX
J408
J412
FBUS RX
CBUSCLK
J406
J409
MBUSTXMBUSR
FBUS TX
J411
J410
The BB and RF shield are connected together on the PWB and the protective metal deck
underneath the battery is grounded to RF shield.
BB Component and Control IO Line Protection
Keyboard lines
ESD protection for keyboard signals is implemented by using metaldome detection.
Grounded keydomes are very eff ective for ESD protectio n and do not require additional
components for ESD protection. The distance from the A-cover to the PWB is made
longer using spikes in the key mat. The C-cover metalliza tion also protects th e keyboard
lines.
C-Cover
The C-cover on the UI-side is metallized on the inne r sur face (partl y) and is gro unded to
the GND module. All areas in which the plated C-cover touches the PWB surface are
grounded and the solder masks are opened.
PWB
All edges are grounded on both sides of the PWB and the solder mask is opened in these
areas. The aim is that any ESD pulse faces the ground area when enter ing the phone, for
example, between the mechanics covers.
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All holes in the PWB are grounded and plated through holes. The only exception i s the
LED holes, which cannot be grounded.
LCD
ESD protection for LCD is implemented by connecting the metal fr ame of the LCD into
ground. The connection is only on one side, at the top of the LCD, which is not the best
solution. The software takes care of the LCD's crashing in case of an ESD pulse.
Microphone
The microphone’s metal cover is connected to the GND and ther e are spark gaps on the
PWB. The microphone is an asymmetrical circuit, which makes it w ell protected against
EMC.
EARP
The EARP is protected with C-cover metallization and with a plastic-fronted earpiece.
Buzzer
PWB openings with the C-cover metallization protect the buzzer from ESD.
IRDA
PWB openings with C-cover metallization protect IRDA lines fr om ESD.
System Connector Lines
Table 5: System Connector lines
System Connector signals that have EMC protection
Protection typeVINXMIXPXMICNXEARPXEARNHEADINTMICP
ferrite bead (600
/199MHz)
ferrite bead (420
/100MHz)
spark gapsXXXXXX
PWB capacitorsXXXXXX
RC-circuitXXXXX
capacitor to
ground
X
XXXXX
XXXXX
Battery Connector Lines
BSI and BTEMP lines are protected by spark gaps and the RC-circuit (10k & 1n), in which
the resistors are size 0603.
MBUS and FBUS
The opening in the protective met al deck, underneath the battery, is so small that ESD
does not get into the MBUS and FBUS lines in the producti on test pattern.
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Transceiver Interfaces
The tables in the following sections illustrate the signals between the various transceiver
blocks.
BB - RF Interface Connections
All the signal descriptions and prope rt ies in th e following table s ar e valid only f or act ive
signals, and the signals are not necessarily present all the time .
Table 6: BB - RF Interface Signal Description
RIPSignal name Connected
from - to
RFICCNTRL(2:0)RF IC Control Bus from UPP to RF IC (SAFARI)
0RFBUSCLKUPPRFICInDig0/1.8V
1RFBUSDAUPP/
RFIC
2RFBUSEN1XUPPRFICInDigRFIC Chip Set X
PUL (2:0)Power Up Reset from UEM to RF IC (SAFARI)
0PURXUEMRFICOutDig0/1.8V10usPower Up Reset for RFIC
GEN (28.0)General I/= Bus connected to RF, see also separate col lective GEN(28.0)
5TXP1RFIC,
Loband
mixer
6TXP2R FICUPPOutDig0/1.8VHigh band Tx enabled
RFIC
UPP
UPPOutDig0/1.8V10 usLow Band Tx enabled
BB I/OSignal Properties
A/D Levels-F re q. /
Timing resolut ion
9.72
(0: <0.4V
1: >1.4V
I/ODigBi-directional RF Control serial
table
Control lines from UPP G E NIOs to RF
MHz
Description / Notes
RF Control serial bus bit clock
bus data.
SLCLK & SLEEPX not used in RF
RFCLK (not BUS -> no rip #)System Clock from RF to BB, original source VCTCXO, buffered (and fre-
2AFCUEMVCTCXOOutAna0.1-2.4V11bitsAFC control voltage to VCTCXO,
IRIF, no bus no ripsUEM 2.7V signals to IR Module
IRLEDCUEMIROutDig0/2.7V9k6 -
IRRXNIRUEMInDig0/2.7V9k6 -
UIDRV lines, no busUEM drivers: sinking outputs to Buzzer, Vibra, KLED, DLED
BUZZOUEMBuzzerOutDig350mA max. /
UEMInAna0.1-2.7VTx PWR Detector Output to
UEM
default about 1.3V
IR Tx signal to IR Module
1Mbit/s
IR Receiver signal from IR Mod-
Vbatt
1Mbit/s
1-5 kHz,
PWM vol
ule
Open collector sink switch output for Buzzer. Frequency controlled pitch, PWM for volume.
VIBRAUEMVibraOutDig135mA max /
Vbatt
DLIGHTUEMUIOutDig100mA /
Vbatt
64/128/
256/512
Hz
Switch/
100Hz
pwm
Open collector sink switch/Frequency/ pwm output for buzzer
Open drain switch/pwm output
for display light
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RIPSignal name Connected
from - to
KLIGHTUEMUIOutDig100mA /
ACCDIF lines, no bus *Wired Digital Accessory Interface, only to test pattern
MBUSUEMTest
Pad 7
FBUSTXOUEMTest
Pad 2
FBUSRXOTest
Pad 3
RTCBATT lines, no bus *Connector pads for Real Ti me Clock back up battery
VBACKUEMRTC-
GNDGlobal GND0
VBB, Globals instead of Bus *Regulated BB Supply Voltages
UEMInDig0/2.7 V9k6-
BATT
UEM I/OSignal Properties
A/D Levels-Freq./
Timing resolution
Switch/
Vbatt
In/
Dig0/2.7 V9k6bit/sMbus bidirectional asynchro-
Out
OutDig0/2.7 V9k6-
In/
Vsu
+2-3.3VFor back up battery Li 6.8x1.4
Out
pply
/
Chrg
100Hz
pwm
115kbit/s
115kbit/s
Description / Notes
Open drain switch/pwm output
for key light
nous serial data bus/FDL clock,
0-8MHz depends on project
Fbus asynchronous serial data
output / FDL data out <1Mbit/s
Fbus asynchronous serial data
input/FDL in, 0-8Mbit/s
depends on project
2.3mAh@3.3V
VANAUEMOutVreg2.78V
+-3%
VFLASH1UEMOutVreg2.78V
+-3%
VFLASH2UEMOutVreg2.78V
+-3%
VIOUEMOutVreg1.8V
+-4.5%
VCOREUEMOutVreg1.0-1.8V
+-5%
VBACKUEMIn/
Vreg3.0 VNo external use, only for RTC
Out
80mA
max.
70mA
max
40mA
max.
150mA
max.
200mA
max.
Disable in sleep mode
1.5mA max. in sleep mode.
VFLASH1 is always enabled
after power on.
VFLASH2 is disabled by default
1.5mA max. in sleep mode. VIO
is always enabled after power
on.
200 uA max. in sleep mode
battery charging/discharging.
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UPP Block signals
Table 9: UPP to UEM Interfaces
RFCCONVDA(5:0)See Table 8. UEM Block Signals to UPP / RFCCONVDA(5:0)
RFCONVCTRL(2:0)See Table 8. UEM Block Signals to UPP / RFCONVCTRL(2:0)
AUDUEMCTRL(3:0)See Table 8. UEM Block Signals to UPP / AUDUEMCTRL(3:0)
AUDIODATA(1:0)See Table 8. UEM Block Signals to UPP / AUDIODATA(1:0)
ISIMIF(2:0)See Table 8. UEM Block Signals to UPP / ISIMIF(2:0)
PUSL(2:0)See Table 8. UEM Block Signals to UPP / PUSL(2:0)
IACCDIF(5:0)See Table 8. UEM Block Signals to UPP / IACCDIF(5:0)
Table 1 0 : UPP - RF In ter f ace s
RFICCNTRL(2:0)See Table 7. BB - RF Interface Signal Description / RFICCNTRL(2:0)
GENIO(28:0)/rips 5 and 6See Table 7. BB - RF Interface Signal Description / GENIO(28:0)
RFCLK & GNDSee Table 7. BB - RF Interface Signal Description / RFCLK (not BUS...)
Table 11: UPP Globals
RIPSignal name Connected
from - to
UPP Globals, no bus, no ripPower supplies and GND
VIOUPPUEMInVreg1.8V
VCOREUPPUEMInVreg1.0-1.8V
GNDUPPVSSXX
X
UPP
I/O
Signal Properties
A/D Levels-Freq./
Timing resolution
20mA
+- 4.5%
+- 5%
0Global GND
max.
100mA
max.
Description / Notes
UPP I/O power supply
UPP logics and processors’
power supply, settable to reach
the speed for various clock frequencies
GENIO(28:0)General I/O Pins. Bolded lines are only valid for one product
although may be described also in other tables
UPP
I/O
Signal Properties
A/D Levels-Freq./
Timing resolution
Description / Notes
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RIPSignal name Connected
from - to
2Not UsedUP PIn /
3Not UsedUPPOutDig0-1.8 VI n / Pull
4LCDRstXUPPDis-
play
5TXP1UPP RF OutDig0-1.8 VOut / 0Tx Power Enable (low Band)
6TXP2UPP RF OutDig0-1.8 VOut / 0Tx Power Enable (High Band)
7Not UsedUPPOutDig0-1.8 VI n / Pull
8Not UsedUPPOutDig0-1.8 VI n / Pull
9Not UsedUPPOutDig0-1.8 VI n / Pull
10IRModSDUPPIR
Module
UPP
I/O
Dig0-1.8 VIn / Pull
Out
OutDig0-1.8 VOut / 0Display reset
OutDig0-1.8 VI n / Pull
Signal Properties
A/D Levels-Freq./
Timing resolution
Up
Down
Down
Down
Down
Down
Description / Notes
IR Module Shut Down
11BandsetUPPRF /
FMR
12ADataUPPIn/
13IR ModuleFIRUPPIR / RFOutDig0-1.8 VIn / Pull UpFast IR
14Not Us edUPPInDig0-1.8 VIn / Pull
15Not Us edUPPOutDig0-1.8 VIn / Pull
16Not Us edUPPInDig0-1.8 VIn / Pull
17Not Us edUPPInDig0-1.8 VIn / Pull
18Not Us edUPPOutDig0-1.8 VIn / Pull
19Not Us edUPPLPRF/RFIn/
20Not Us edUPPLPRFOutDig0-1.8 VO ut / 0LPRF Data Out
21Not Us edUPPLPRFOutDig0-1.8 VI n / Pull UpLPRF Sync / Accessory Mute
OutDig0-1.8 VIn / Pull UpLo/Hi Band Selection (DAMPS) /
Extended Band Selection (PDC)
Dig0-1.8 VIn / Pull
Out
Dig0-1.8 VIn / Pull
Out
Down
Down
Down
Up
Up
Down
Down
LPFR Data In / Accessory Buffer
Enable / PAGain
22Not Us edUPPLPRFOutDig0-1.8 VIn / Pull
Down
23FLSWRPXUPPFLASHOutDig0-1.8 VOut / 1Write Protect, 0-active w h en
LPRF Interrupt/Accessory P ower
Up
protected
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RIPSignal name Connected
from - to
24Not Us edUPPOutDig0-1.8 VIn / Pull
25Not Us edUPPIn/
26Not Us edUPPOutDig0-1.8 VIn / Pull
27Not Us edUPPIn/
28Not Us edUPPOutDig0-1.8 VOut / 1
UPP
I/O
Dig0-1.8 VIn / Pull
Out
Dig0-1.8 VIn / Pull
Out
Signal Properties
A/D Levels-Freq./
Timing resolution
Up
Up
Down
Up
Table 14: UPP to Key/Display Interfaces
RIPSignal name Connected
from - to
KEYB(10:0)*Keyboard matrix
0P00UPP KEY-
BOARD
UPP
I/O
InDig0-1.8 VKeyboard Matrix Line S0. Not
Signal Properties
A/D Levels-Freq./
Timing resolution
Description / Notes
Description / Notes
used.
1P01UPP KEY2P02Keyboard Matrix Line S2
3P03Keyboard Matrix Line S3
4P04Keyboard Matrix Line S4
5P010UPP KEY6P011Keyboard Matrix Line R1
7P012Keyboard Matrix Line R2
8P013Keyboard Matrix Line R3
9P014Keyboard Matrix Line R4
10P015UPPKEY-
LCDUI lines, no bus *Display & UI Serial Interface
LCDCamClkUPPDIS-
LCDCamTxDaI/
BOAR
D
BOAR
D
BOARD
PLAY
InDig0-1.8 VKeyboard Matrix Line S1
InDig0-1.8 VKeyboard Matrix Line R0
InDig0-1.8 VKeyboard Matrix Line R5. Not
used.
OutDig0-1.8 V4.86
MHz/
2.43 MHz
Dig4.86
Out
MHz/
2.43
Mbit/s
Data clock for LCD serial bus,
the speed may vary according
to the display and direction
requirements.
Signal Properties
A/D Levels-Freq./
Timing resolution
+- 3%
1Mbit/s
1Mbit/s
500mA
peak @Tx
1=99uA
max.
@Rx
Description / Notes
IR Tx signal to IR Module
IR Receiver signal from IR Module
inverting level shifter to 2.7V
Transmitter IR LED pow e r supply from battery 3.6V nominal,
3...5.1V total range
IR Receiver and Transmitter
power supply
Audio Interfaces
Table 17: Internal A udio
RIPSignal name Connected
from - to
HP INTERNAL AUDIO
AUDIO(4:0)HP Internal microphone and earpiece IF between UEM and Mic/Ear cir cui ty
0EARPUEMEar-
piece
1EARN
2MIC1NMicUEMInAna100mVpp
3MIC1P
4MICB1Mic UEMOutV
System ConnectorHP Internal microphone IF between System Connector and Mic/ear circuitry
MIC+MicAudio
- UEM
AUDIO
I/O
OutAna1.25VAudioDifferential s i g nal t o HP inter-
bias
In
Ana
Out
Bias
Signal Properties
A/D Levels-Freq./
Timing resolution
max diff.
2.1V typ./
<600 uA
2mV nom
2V2kohm
Audio, AC
coupled
to UEM
Audio
DC bias
Description / Notes
nal Earpiece.
Load resistance 32 ohm.
Differential signal from HP
internal MIC
Bias voltage for internal MIC
Mic bias and audio signal.
Microphone mounted into system connector
MICInGND0 (GND)AGND coupled to GND at UEM
Earpiece Connector PadsHP Internal IF between Earpiece and Mic/Ear circuitry
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RIPSignal name Connected
from - to
“1”-EARPEARAudio
UEMEAR
P/N
AUDIO
I/O
OutAna1.25VDiff DC
Signal Properties
A/D Levels-Freq./
Timing resolution
coupled
Audio
Table 18: External Audio
RIPSignal name Connected
from - to
EXTERNAL AUDIO INTERFACE
XAUDIO(9:0)*External Au dio IF between UEM and X-audio circuitry
0HEADINTSysCon
/HSet
1HFUEMSysCon
2HFCMAna0.8 Vdc
UEMOutDig0/2.7VOutput to UEM for Headset
/HSet
AUDIO
I/O
InAna1.0Vpp
Signal Properties
A/D Levels-Freq./
Timing resolution
bias 0.8V
AudioExternalEarpiece Audio Signal
Description / Notes
Differential audio signal to earpiece 32 ohm
Description / Notes
Connector “HeadInt” Switch
Reference for DC coupled
external Earpiece
3MICB2UEMSysCon
/HSet
4MIC2P
MIC2N
5
6HOOKINT Sys
7Not used
8Not used
9Not used
System ConnectorHP Internal microphone IF between system connector and Mic/Ear circuitry
XMICPHS/HF
XMICNInAna2/60mV nom
SysCon
/HeadSet
Con
Mic
UEMOutAna200mVpp
UEMOutAna/
Audio
- UEM
OutV
In
Out
2.1V tvp/ 600
bias
uA
AudioDifferential signal from exter-
max diff
0...2.7 VDCHS Button interrupt, External
Dig
Ana
Bias
2/60mV nom
diff
2.1V bias
1kohm
diff
GND/1kohm
Audio
DC bias
Audio
Bias voltage for external MIC
nal MIC
Audio Accessory Detect (EAD)
Headset Mic bias and audio
signal 2mV nomi nal. HF Mic
signal 60mV nominal. Differential symmetric input.
Accessory detection by bias
loadind (EAD channel of slow
ADC of UEM)
Hook interrupt by heavy bias
loading
Mic - connecting to GND
through lower part of split
symmetric lo ad resistor (2 x 1
kohm)
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RIPSignal name Connected
from - to
XEARPHS/HF
XEARN
INTSwitchAudio
EAR/
Amp.
Audio
- UEM
- UEM
AUDIO
I/O
InAna100 mV nom
InDig0/2.7VHS interrupt from system con-
Signal Properties
A/D Levels-Freq./
Timing resolution
diff
Key/Display blocks
Table 19: KEY Block Interface Signal Description
RIPSignal name Connected
from - to
KEYB(10:0)Keyboard matrix, Roller key
0P00Not usedUPPOutDig0/1.8V
KEY
I/O
AudioQuasi differential DC-coupled
Signal Propertie s
A/D Levels-Freq./
Timing resolut ion
Description / Notes
earpiece/HF amplifier signal to
accessory. DC biased to 0.8V;
XEARN a quiet refe ren c e
although have signal when
loaded due to internal series
resistor.
nector switch when plug
inserted.
Description / Notes
1P01KeyboardKeyboard Matrix Line
2P02KeyboardKeyboard Matrix Line
3P03KeyboardKeyboard Matrix Line
4P04KeyboardKeyboard Matrix Line
5P10KeyboardKeyboard Matrix Line
6P11KeyboardKeyboard Matrix Line
7P12KeyboardKeyboard Matrix Line
8P13KeyboardKeyboard Matrix Line
9P14KeyboardKeyboard Matrix Line
10P15Not Used
PWR_KEYP ower Key, not a member of the keyboard matrix
PWR_KEYPower keyUEMOutDig0/VbattPower key, not a member of
the keyboard matrix
Table 20: Display block Signal Description
RIPSignal name Connected
from - to
Display
I/O
Signal Properties
A/D Levels-Freq./
Timing resolution
Signal Properties
A/D Levels-Freq./
Timing resolution
Description / Notes
Baseband External Connections
Table 2 1: System Connector Interface
RIPSignal name Connected
from - to
System ConnectorHP Internal microphone IF between System Connector and Mic/Ear circuitr y
XMICPHS/HF
Mic
XMICNInAna2/60mV
Audio
- UEMInOut
Sys Conn
I/O
Ana
Bias
Signal Properties
A/D Levels-F re q. /
Timing resolution
2/60mV
nom diff
2V2koh
m
nom diff
Audio
DC bias
Audio
Description / Notes
Headset Mic bias and audio signal 2mV nominal. H f Mi c sig nal
60mV nominal. Di ff erential symmetric output.
Accessory detection by bias loadind.
Hook interrupt by heavy bias
loading.
XEARPHS/HF
XEARN
INTSwitchAudio
CHARGER INTERFACE
CHARGER lines, no bus *
VCHARINChargerUEMI nV chr< 16V
GNDGNDGND from/to Charger connector
EAR/
Amp.
AudioUEM
- UEM
InAna100mV
nom diff
InDig0/2.7VHS interrupt from system connec-
<1.2A
AudioQuasi differential DC-coupled
earpiece/HF amplifier signal to
accessory. DC biased to 0.8V;
XEARN a quiet referen c e
although have signal when
loaded due to internal series
resistor.
tor switch when plug inserted
DCVch from Charger Connector, max
20V
Table 22: Battery Connector Interface
RIPSignal name Connected
from - to
GNDGlo-
bally
VBATBatt +Vbatt3.0-5.1VD CBatt e ry Voltage
Batt -Global GND
Batt Conn
I/O
Signal Properties
A/D Levels-Freq./
Timing resolution
Description / Notes
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RIPSignal name Connected
from - to
BSIUEMAna
BTEMPUEMBtemp NTC Resistor, 100 kohm
Test Pattern for Production Tests
Table 23: Test Pattern Interface Signal Description
RIPSignal name Connected from
- to
2FBUSTX /
FDLTX
3FBUSRX /
FDLRX
6VPPTest
Test
Point
Test
Point
Point
UEMOutDig0/2.7VFbus asynchronous serial data
UEMInDig0/2.7VFbus asynchronous serial data
Memory
Batt Conn
I/O
Ana
UI
I/O
OutAna0/5/12VExte rnal Flash Programming
Signal Properties
A/D Levels-Freq./
Timing resolution
0-2.7VPull down
res
Signal Properties
A/D Levels-Freq./
Timing resolution
Description / Notes
Battery Size Indicator Resistor,
100 kohm pull up to
2.78V(VFLASH)
pull up to 2.78V(VANA)
Description / Notes
output / FDL
input / FDL RxData
Voltage fo r Flash Memory
7MBUS / FDL-
CLK
8GNDTest
Test
Point
Point
UEMIn/
BBGround
Dig0/2.7V9k6bit/sMbus bidirectional asynchro-
Out
nous serial data bus/FDL Clock
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RF Module
Requirements
The NPC-1 RF module supports the following systems:
•AMPS
•TDMA800
Hence, the minimum transceiver performance requirements are described in TIA/EIA136-270. The NPC-1 RF must follow the requirements in the revision A. The EMC requirements are set by FCC 47CFR 15.107 (conducted emissions), 15.109 (radiated emissions,
idle mode) and 22.917 (radiated emissions, call mode).
Design
The RF design is centered around the SAFARI RF-IC. The SAFARI consists of receivers,
transmitter IF parts and all PLL's. RF filtering, 2G LNA, powe r amplifiers, TX upconverter
and TX power detection circuitry are left outside SAFARI.
The phone comprises of one single-sided 8 –layer PWB. A single multiwall RF shield i s
used and this sets the maximum component height to 2.0mm. An internal antenna is
located on the top of t he phone and there is room f or a 4.0mm high ceramic duplexer
under the antenna assembly.
Software Compensations
The following software compensations are required:
•Power levels temperature compensation
•Power levels channel compensation
•Power level reduction due to low battery Voltage
•TX Power Up/Down Ramps
•PA's bias reference currents vs. power, temp and operation mode
•RX IQ DC offsets
•RSSI channel compensation
•RSSI temperature compensation
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2
F 2
F 2
BaseBand
PAMS Technical DocumentationSystem Module
Main Technical Characteristics
RF Frequency Plan
The NPC-1 frequency plan is shown in the figure below. A 19.44 MHz VCTCXO is used for
UHF and VHF PLLs and as a baseband clock signal. All RF locals are generated in PLLs.
Figure 11: RF Freq uency Block Plan
Rx IF
0 MHz
RX IQ
Rx Channel Centre F requencies
TDMA800 869.04...893.97
Rx IF
135.54 MHz
F
Rx VHF
271.08 MHz
PLL
UHF
TDMA800 2009.16 MHz 2059.02 MHz
VCTCXO
19.44 MHz
PLL
PLL
Tx VHF
TDMA800: 361.08 MHz
Tx channel centre frequencies
TDMA800 824.04...848.97 MHz
Tx IF
180.54 MHz
TX IQ
Due to the AMPS mode, simultaneous reception and transmission, TX and RX IF frequencies are exactly 45MHz apart from each other. RXIF is 135.54 MHz and TXIF 180.54MHz.
The RXIF frequency is set so that it is not a multipl e of either of VHF's comparison fre quency (120k).
DC Characteristics
Power Distribution Diagram
Note: The current values in the figure below are not absolute values and cannot be
measured. These values represent maximum/typical currents drawn by the corresponding RF or SAFARI blocks in use, and are, therefore, dependent on the phone’s
operating mode and state.
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Figure 12: Power distribution
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Regulators
The regulator circuit is the UEM and the specifications can be found in the table below:
Table 24: Regu la tor specifications
Regulator nameOutput voltage (V)Regulator Max. cur-
Receiver
The receiver shows a superheterodyne structure with zero 2nd IF. Most of the receiver
functions are integrated in the RF ASIC. The only funct ions out of the c hip are duplex ers
and SAW filters.
An active 1st downconverter sets naturally high gain requi rements f or preceding sta ges.
Hence, losses in very select ive frontend filters are minimized dow n to the limits set by
filter technologies used and component sizes. LNA gain is set up to 16dB, which is close
to the maximum available stable gain from a single stage amplifier. LNAs are not exactly
noise matched in order to keep passband gain rippl e in minimum. Filters have relative
tight stopband requirements, which are not all set by the system requirements but the
interference free operation in t he fie ld. In this re ceive r stru cture, linear ity lies heavily on
mixer design. The 2nd order distortion re quirements of t he mixer are set by the 'half IF'
suppression. A fully balanced mix er topology is required. Additionally, the receiver 3rd
order IIP tends to depend on active mixer IIP3 linearity due to pretty high LNA gain.
IF stages include a narrowband SAW filter on the 1st IF and a integrated lowpass filtering on zero IF. SAW filter guarantee s 14dBc attenuation at alternating channels, which
gives acceptable receiver IMD performance wit h only moderate VHF local phase noise
performance. The local signal's partition to receiver selectivity and IMD depends then
mainly on the spectral purity of the 1st local. Zero 2nd IF stages inc lude most of receiv-
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ers signal gain, AGC control range and channel filtering.
Table 25: RF Characteristics
ITEMNMP Requirement TDMA, AMPS 800
RX frequency range, DAMPS 800869.01...
893.97
LO frequency range2009.1...
2059.2
1st IF frequency135.54
Channel NBW, RF28.6
IF 1 3dB roll off min. frequency (+-?f)13
2nd IF min. 3dB bandwidth16 / IQ-branch
Max total group delay at 3dB bandwidth
C/N for sensitivity, digital
analog
C/I for selectivity, digital
analog
Sensitivity, digital mode static ch (BER < 3%)
ANALOG MODE (sinad >12Db)
Adjacent channel selectivity, digital
analog
Alternate channel selectivity, digital
analog
IMD attentuation selectivity, digital
analog close spaced (60/120)
analog wide spaced (330/660)
Cascaded NF, digital
analog
Cascaded IIP 3, digital 120/240, 240/48 0 k Hz
analog 60/120 kHz
analog 330/660 kHz
Available receiver gain digital/analog85 (min.)
RF front end gain control range, A G C 1 step20
7
3.5
8
4
-110 (min.)
-116 (min.)
13
16*
45
65*
65
65*
70*
< 9.5
< 9.5
> -7.7
> -17*
> -8*
1st IF gain co nt rol range, A G C 2 step30
R X 2nd IF gain control range, 8x6dB steps42
Min signal level at RX-ADC input @ sensitivity
digital
analog
Input dynamic range-116... -2.0
Gain relative accuracy in receiving band **2
Gain absolute accuracy in receiving band **4
* referenced to the sensitivity level
** After production alignment
-31
-25
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AMPS/TDMA 800 MHz Front End
Default vendor for 881.5MHz bandfilter is Murata, type 4146
Table 26: RX800 Front End Characteristics Ant to 1st Mixer
ParameterMINTYPMAXUnit/Notes
Diplexer input loss0.350.40.45dB
Duplexer input loss2.534.1dB
LNA gain: High gain mode
Gain18.218.620dB
Noise Figure4.65.57dB
3rd order intercept (IIP3)-8.9-7.5-6.8dBm
*see Safari spec/measurements
16
-4.5
16.5
-4
17.3
-3.8
dB
dB
Table 27: RF - IX Spe c ification
ParameterMinimum
Typical/
Nominal
MaximumUnit/Notes
Total
Pow er up time0. 1ms
Noise figure, total9.5dB
3rd order input intercept point-25dBm
Max voltage gain,
Mixer + 2nd IF (IF+2nd AGC max)
Min voltage gain,
Mixer + 2nd IF (IF+2nd AGC min.)
Gain charge,
Mixer+2nd IF
IQ mixers + AMP2
RF input impedence differential1.2kohm/pF
RF input frequency range135.54MHz
78.5dB
6dB
1.40.9dB, temp
-30...+85 C
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ParameterMinimum
Conversion gain @ RI=1kohm23 .52424.5dB
IF AGC gain range (5x6 dB)30dB
IF AGC gain step (5 steps)6dB
IF AGC gain error relative to max gain-0.5+0.5dB
AMP2 gain18dB
7 steps
AGC gain error relative to max gain-0.5+0.5dB
Max IF/2nd IF buffer output level3V pp (differential)
6dB
Frequency Synthesizers
NPC-1 synthesizer consists of three synthesizers, one UHF synthesizer and two VHF synthesizers. UHF synthesizer is based on integrated PLL and external UHF VCO, loop filter
and VCTCXO. Its main goal is to achieve the channel select ion f or the dual mode. Due to
the RX and TX architecture this UHF synthesizer is used for down conversion of the
received signal and for f inal up conversion in transmitter. Frequency divider by two is
integrated in Safari.
Two VHF synthesizers consists of: RX VHF Synthesizer includes integrated PLL and VCO
and external loop filter a nd r esonator. The output of RX-VHF PLL is used a s L O signal for
the second mixer in receiver. TX VHF Synthesizer includes integrated PLL and external
amplifier, loop filter and resonator. The output of TX-VHF PLL is used as a LO signal for
the IQ-modulator of the transmitter. See depicted block diagrams and synthesizer characteristics from synthesizer specification document [6].
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Transmitter
The transmitter RF architecture is up-conversion type (desired RF spectrum is low side
injection) whit (RF-) modulation and gain control at IF. The IF frequency is 180.54MHz.
The cellular band is 824.01-848.97MHz.
Common IF
The RF-modulator is integrated with PGA (Programma ble Gain Amplifier) and IF output
buffer inside SAFARI_T RFIC-chip (later as Safari) . I- and Q-signals, t hat are output signals from BB-side SW IQ-modulator, have some filtering inside Safari before RF-modulation is performed. The required LO-signal from TXVCO is buffered with phase sifting in
Safari. After modulation (π/4 DQPSK or FM) the modulated IF signal is amplified in PGA.
Cellular Band
The maximum linear (balanced) IF signal level to 50Ω load is about –8 dBm.
For proper AMPS-mode receiver (duplex)sensitivity IF signal is filtered in strip-filter
before up-conversion. The upconverter mixer is actually a mixer with LO and output
driver being able to deliver about +6dBm linear output power. Note, that in this point,
term linear means –33dB ACP. The required LO power is about –6dBm. The LO signal is
fed from Safari.
Before power amplifier RF signal is filter in band filter. The typical insertion loss is about
–2.7dB, and maximum less than –3.5dB. The input and outp ut return losses are about –
10dB.
Power amplifier is 50Ω/50Ω module. It does not have own enable/disable control signal,
but it can be enabled by bias voltage and reference bias current signals. The gain window
is +27 to +31dB and linear output power is +30dBm (typical condition) with –28dB ACP.
The nominal efficiency is 50%.
Power Control
For power monitoring there is a power detector module (PDM) build up from a coupler, a
biased diode detector and an NTC resistor. RF signals are routed via this PDM. The RF isolation between couplers is sufficient not to loose filtering performance given by duplex
filters.
The diode output voltage and NTC voltage are routed to BB A/D converters for power
control purpose. The TX AGC SW takes samples from diode output volt age a nd compa res
that value to target value, and adjust BB I-and Q-signal amplitude and/or Safari PGA
settings to keep power control in balance.
NTC voltage is used for diode temperature compensation and for thermal shut down
when radio board’s temperature exceeds +85°C.
False TX indication is based on detected power measurement when carrier is not on.
The insertion loss of coupler is –0.42dB (max). Typical values for inser tion l oss is about -
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0.2dB. The filtering performance of diplexer is taken in account in system calculations.
Signal levels
(For AMPS mode PL2 25.5 dBm, PL2 27.3 dBm for digital mode both bands)
Antenna Circuit
Here the antenna circuit stands for duplex filters and the diplexer. The cellular band
duplex filter is band pass type SAW filter with typical insertion loss about –2.0dB. The
insertion loss of the diplexer is-0.2 (max) and the typical value is about –0.1dB.
RF Performance
The outpu t po wer tu nin g ta rge t fo r po wer le vel 2 a fte r d iple xer (or aft er swit ch for exte rnal RF) is +27.3dBm for π/4 DQPSK type of modulation and +25. 5dBm for FM type of
modulation. Power levels downwards from PL2 are –4dB below next to highest power
level, PL10 being –4.7dBm (and PL7 +6.5dBm with FM type of modulation). Modulation
accuracy and ACP shall be within limits specified in IS-136/137.
Antenna
The NPC-1 antenna solution is an internal single r esonance PIFA-antenna. In a single
band transceiver, a SMD compatible through chip can be used.
1012-4dB
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Programmes After Market Services
NPC-1 Series Transceivers
P arts List
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Parts ListPAMS Technical Documentation
Table of contents
Page No
Parts List of WS8 (EDMS Issue 2.14)........................................................................... 3
Fig 3 Exploded view of NPC-1NG product variants (Gradiente design)............................9
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Transceiver NPC-1
The NPC-1 transceiver is a TDMA single band (SB), 800 MHz + AMPS hand portable.
NOTE: The Service Manual is intended for use by qualified service pe rsonnel only.
Modules and Transceiver Structure
Custom Transceiver
ATO Transceiver
1A-cover
2Keymat
3Co-label, if needed
4Type label
5Software settings
• CSF-file
• SW Language package (PPM)
Basic Transceiver NPC-10506131
•RF/System Module0201800
•Mechanics MNPC10262389
•Software SW NPC-10242181
The Basic Transceiver NPC-1 consists of the System, Mechanics and Software -modules.
After FINUI testing, the Basic Transceiver is a tested engine. All NPC-1 product variants
are based on the Basic Transceiver.
Note: This is the basic structure of the phone. The Basic Transceiver codes vary
according to the manufacturing site.
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Figure 1: Explod ed view of Basic Transc eiver NPC-1
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Assembly Parts of the Basic Transceiver NPC-1
EDMS
CIRCUIT REF./
ITEMQ’TYCODEDESCRIPTIONVALUE, TYPE
Some of the existing custom 3320 transceiver variants are listed below:
10503270 Nokia default english transceiver
20506315 Nokia default spanish transceiver
30505859 Bellsouth Chile transceiver
40505860 Bellsouth peru Subsidy lock transceiver
50506325 Central America and Caribbean Spanish LTA with subsidy lock trans-
This section briefly describes how to install the Phoenix software and includes some
basic information on how to use the program. For more detailed information, please refer
to the Phoenix’s Help -files. Each feature in Phoenix has its own Help function, which
can be activated while running the program.
Press the F1 key or the feature's Help-button to activate a Help -file.
Setting up Phoenix
1Download the latest release. Please contact your regiona l After Market Services
point for information on where to download the latest release.
Download and read the release notes, whic h will have useful information on the
software version you are using.
2Install Phoenix by executing the phoenix installation package and follow the
instructions on the screen.
Note: In some products the setup may require you to reboot the computer. In
either case, the setup will register Phoenix components. This process
can take several minutes.
3Download the latest data packages for the products you will be using.
By default, the program files are stored under C:\Program Files\Nokia\Phoenix
The Phoenix program has been built using component architecture. This mea ns
that the actual program is very small and most of the program’s f unctionality i s
divided into dynamically loaded modules (DLLs).
The data packages will create product spe cific directories under the insta llation
directory.
HW requirements for using Phoenix
Table 1: HW requirements for AMS
Minimum HW requirements for AMS
Processor233 Mhz
RAM64 MB
Needed disk space50 - 100 MB
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Table 2: Recommended HW for Windows 2000
Recommended HW for Windows 2000
Processor700 Mhz
RAM512 MB
Needed disk space50 - 100 MB
Table 3: Supported Operating Systems
Supported Operating Systems
Windows 95
Windows 98
Windows NT 4.0
Windows 2000
Installing Phoenix
1Before you start installing the program, check that
• the dongle is attache d to the parallel port. Contact your supervisor in order to
obtain a suitable dongle.
• you have administrator rights (Windows NT or Windows 2000). This is required
in order to be able to install Phoenix.
2The installation checks that the latest supported dongle driver version is
installed. The dongle driver is installed if there is no previous installa tion of the
dongle driver or if the installed dongle driver is older than the latest supported
version.
3Reboot your PC before using Phoenix, if you are requested to do so.
Uninstalling Phoenix
Uninstalling another Phoenix version
1Make sure that the dongle is attached.
2Go to the Control Panel and select Add/Remove Programs.
3Select TSS4 Phoenix Release xx.yy .zzz for uninstallation and click Add/Remove.
4Click OK to remove the application
You may be required to reboot your PC after uninstallation.
Note: If you have different product packages installed, the components are unin-
stalled only if they are not included in other product packages.
Data Packages
Data Packages (DP) is a name for a helpful feature in the Phoenix software. This type of
feature provides a flexible way of distributing and installing Phoenix and its data files.
All product-specific data is separated from the pr ogram code and installed separately.
This means that the installation is performed in at least two steps.
Each product will have its own DP. The FPS-8 flashing equipment also has its own package.
Starting a session
Concepts
In the Phoenix context, Product means the cellular phone attached to a PC. More specifically, it is a particular type of phone.
Connection means the type of cable used to attach the phone to the port to which the
other end of the cable is attached.
Selecting a connection
The connection defines the cable and the comm unications port that will be used when
connecting to the phone.
1Active connections are l isted in the toolbar’s Connection pull-down menu. You
should make sure that the connection is correct before using the software.
Change it, if necessary.
In case the connection is the wrong one, you need to create a new one.
2Select Settings from the pull-down menu.
3Select Add in the Connection List Dialog and in fill the relevant fields in the Con-
nection setup dialog.
Selecting a product
Many of Phoenix’s features are product-specific. It is, therefore, mandatory to choose the
product you will be working on at the beginning of the session.
1Select File - Scan Product (or hold the Ctrl key down and press R). Phoenix will
scan the connected product and load additional menus which ar e designed for
the product. If the product is not supported then an error message will be displayed and a different Phoenix data package may be required.
2If you want to manually choose the product or if the phone is dead , select File -
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Choose Product. You will be presented with a list of available products.
After the product selection, you will see an addit ional menu item on the main
menu. If you take a look at the available menu items, you will see that their number has increased.
Phoenix environment
You can configure the program’s main toolbar and the product or t ool -specific options
to your liking.
You can control which toolbars are visible by selecting View and Toolbars from the pulldown menu. The visible toolbars are marked with a check.
The rest of the options are product or tool -specific. The tool-specific options are set
using the associated toolbar.
Using components
When working with Phoenix, each task gene rally has its own component that will per form the task. The first thing, therefore, is to open the desired component.
Opening a component means that you open a tool window within Phoenix.
The POS flash concept needs the Flash Adapter and cable between the phone and the
FLS-4.
Product Code
FLS-4: 0774263
Figure 2: View of POS Dongle, FLS-4
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FPS-8 Flash Prommer for heavy flash (0080321, sales pack)
The FPS-8 flash prommer is used for heavy flashing.
Product Code
FPS-8: 0080321
Figure 3: View of Flash Prommer for heavy flash, FPS-8
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FPS-8C Flash Prommer for heavy parallel flash (0080396)
The FPS-8C Flash Prommer is used for heavy parallel flashing.
Product Code
FPS-8C: 0080396
Figure 4: View of Flash Prommer for heavy parallel flashing
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Docking Station (JBV-1, 0770298) and Docking Station Adapter (MJF-2,
0770300)
The Docking Station and Docking Station Adapter are needed for Mbus, Fbus, RF and
Audio connections. This setup allows a connection be tween flash prommers. When the
audio box is connected, it has to be connected to the phone’s audio connector. The Docking Station can be powered by the FPS-8 or an external power supply.
Product Code
JBV-1: 0770298
MJF-2: 0770300
Spare parts for MJF-2 test pin: 540Y207 (test probe code)
Figure 5: View of Docking Station, JBV-1
Figure 6: Docking station and docking station adapter
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Galvanic Contact (GAC-1, 0770301)
The GAC-1 adapter is needed for the RF conne ction. The GAC-1 adapter makes galvanic
connections to assembled handset RF-switches p ossible. Via this ad apter, the handset is
connected to the RF measuring and test equipment.
Note: Unnecessary usage of the handset’s RF-switch must be avoided.
Product Code
GAC-1: 0770301
Figure 7: View of Galvan ic Contact, GAC-1
Page 10ãNokia CorporationIssue 1 10/01
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