NEC VR4181 User Manual

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User’s Manual

VR4181™

64-/32-Bit Microprocessor
Hardware

PD30181

µµµµ

Document No. U14272EJ3V0UM00 (3rd edition)
Date Published November 2002 NS CP(K)



 NEC Electronics Corporation 2000




 MIPS Technologies, Inc. 1998



Printed in Japan

[MEMO]

2

User’s Manual U14272EJ3V0UM

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

VR10000, VR12000, VR4000, VR4000 Series, VR4100, VR4100 Series, VR4110, VR4111, VR4121, VR4122,
V

R4181, VR4300, VR4305, VR4310, VR4400, VR5000A, VR5432, and VR Series are trademarks of NEC

Electronics Corporation.
MIPS is a registered trademark of MIPS Technologies, Inc. in the United States.
MBA is a trademark of Vadem Corporation.
Pentium, Intel, and StrataFlash are trademarks of Intel Corporation.
DEC VAX is a trademark of Digital Equipment Corporation.
PC/AT is a trademark of International Business Machines Corporation.

User’s Manual U14272EJ3V0UM

3

Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.

•

The information in this document is current as of January, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

•

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative

•

purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.

•

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.

•

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer­designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.

(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

4

User’s Manual U14272EJ3V0UM

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics America, Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Europe) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

• Sucursal en España

Madrid, Spain
Tel: [phone]
Fax: [phone]

• Succursale Française

Vélizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

• Filiale Italiana

Milano, Italy
Tel: [phone]
Fax: [phone]

• Branch The Netherlands

Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

• Tyskland Filial

Taeby, Sweden
Tel: [phone]
Fax: [phone]

• United Kingdom Branch

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore
Tel: [phone]
Fax: [phone]

User’s Manual U14272EJ3V0UM

J02.11

5

Page Description

Throughout this
manual

p. 30
p. 34
p. 35
pp. 38 to 42
p. 43
pp. 45, 46
p. 47
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p. 52
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p. 58
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pp. 67 to 90
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p. 113

p. 114
p. 117

Major Revisions in This Edition (1/5)

Separation of the following parts of the previous (the 2nd) edition

CHAPTER 3 MIPS III INSTRUCTION SET SUMMARY, CHAPTER 4 M IPS16 INSTRUCTION SE T ,
CHAPTER 5 V
CHAPTER 7 EXCEPTION PROCESSING (second half), CHAPTER 9 CACHE MEMORY,
CHAPTER 10 CPU CORE INTERRUP T S, CHAPTER 27 MIPS III INSTRUCTIO N SET DETAILS,

CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT
Deletion of modem block in
Modification of desc ri ption in
Modification of Remark i n
Addition of
Modification of desc ri ption and deletion of figure in
Addition of
Addition of descriptions in
Addition of

Connection Circuits of Resonator

Modification of Note in
Modification of descriptions for SYSDIR and SYSEN# and additi on of description in Note in

System bus interface signals

Addition of descript i on f o r I RDIN/RxD2 in
Addition and modificati on i n
Addition of

Circuits

Addition of
Modification of
Modification of desc ri ption in
Addition of description i n Note in
Modification in
Modification of desc ri ption in
Addition of description i n
Modification of desc ri ption in
Addition of
Modification in
Modification of desc ri ption in
Modification of desc ri ption for bit 4 and addition of Caution and Remark in

(0x0A00 0000)

Modification of desc ri ptions for bits 14 to 12, bit s 3 to 0, and Remark in

(0x0A00 000C)

Modification of
Deletion of description f or Di v4 mode and addition of description i n Rem ark in

clock (TClock)

4181 PIPELINE, CHAPTER 6 MEMORY MANAGEMENT SYSTEM (first half),

R

Figure 1-1. Internal Block Diagram

1.3.16 LCD interface

1.3.17 Wake-up events

1.4.2 CPU instruction set overview

and

1.4.3 Data formats and addressing

1.4.4 CP0 registers

1.4.9 Power modes

and

1.4.10 Code compatibility

1.5 Clock Interface

Figure 1-8. External Circuits of Clock Oscillator

and

Figure 1-9. Incorrect

2.2.1 System bus interface signals

2.2.10 IrDA interface signals

2.3 Pin Status in Specific Status

2.4 Recommended Connection of Unused Pins and I/O Circuit Types

CHAPTER 3 CP0 REGISTERS

Table 4-6. DRAM Address Map

5.1.1 RTC reset
Figure 5-1

through

Figure 5-5, Figure 5-8

, and

Figure 5-9

Figure 5-2. RSTSW Reset

5.1.5 HALTimer shutdown

5.3.1 Cold Reset

5.3.2 Soft Reset

5.4 Notes on Initialization

R

Figure 6-1. V

4181 Internal Bus Structure

6.1.2 (3) LCD module (LCD Control Unit)

6.2.1 BCUCNTREG1

6.2.3 BCUSPEEDREG

Figure 6-2. ROM Read Cycle and Access Parameters

6.2.6 (2) Peripheral

and

2.2.1

2.5 Pin I/O

6

User’s Manual U14272EJ3V0UM

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p. 151
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p. 186
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Major Revisions in This Edition (2/5)

Modification of desc ri ption in
Modification of Remark i n
Modification of figure i n
Modification of

Figure 6-3

Addition of description i n
Addition of Caution and modifi cation in Remark in
Modification of desc ri ption for bits 6 to 4 in
Modification of Note in
Addition of description i n
Addition of description i n
Modification of desc ri ption for bits 10 and 9 and addition of description in

02C4)

Modification of desc ri ption for bits 3 and 2 in
Modification of values at reset in

(0x0A00 065A)

Addition of description for bit 8 in
Addition of description for bit 0 in
Addition of description for bits 5 and 4 in
Modification of desc ri ption and addition of Caution in
Addition of Caution in
Addition and modificati on of descriptions in
Modification of desc ri ption in
Addition of Remarks and description in
Addition of description i n
Modification of desc ri ption in
Modification of address and description for bits 2 and 1, and addition of description in

KIUINTREG (0x0B00 0086)

Modification of R/W and addition of description in
Modification of desc ri ption in
Addition and modificati on of descriptions in
Modification of desc ri ption in
Modification of location of
Modification of

Figure 10-2. EDO DRAM Sign als on RSTSW Reset (SDRAM Bit = 0)

Modification of desc ri ption in
Modification of desc ri ption in
Modification of desc ri ption of Caution in
Modification of signal nam e i n
Modification of desc ri ption in

6.3.2 Connection to external ROM (x 16) devices

6.3.3 (4) 64 Mbit PageROM

6.3.3 (5) 32 Mbit flash memory (when using Intel

through

Table 6-2. V

Figure 6-8

R

4181 EDO DRAM Capacity

6.5.2 MEMCFG_REG (0x0A00 0304)

6.5.3 MODE_REG (0x0A00 0308)

6.5.4 SDTIMINGREG (0x0A00 030C)

6.6 ISA Bridge

6.7.1 ISABRGCTL (0x0B00 02C0)

7.2.6 AIUDMAMSKREG (0x0A00 0046)

7.2.7 MICRCLENREG (0x0A00 0658)

7.2.9 MICDMACFGREG (0x0A00 065E)

7.2.10 SPKDMACFGREG (0x0A00 0660)

7.2.11 DMAITRQREG (0x0A00 0662)

8.1 Overview

Figure 8-1. SCK and SI/SO Relationship

8.2.2 SCK phase and CSI transfer timing

8.2.3 (1) Burst mode

8.3.1 CSIMODE (0x0B00 0900)

9.1 Overview
Table 9-1. ICU Registers

9.2.11 MAIUINTREG (0x0B00 0090)

Figure 10-1. Transition of V

R

4181 Power Mode

10.2.1 Power mode and state transition

Table 10-2. Operations During Reset

10.3.3 Deadman’s Switch reset

10.3.4 (2) Preserving SDRAM data
Table 10-3. Operations During Shutdown

10.5 Power-on Control

10.5.2 Activation via CompactFlash interrupt request

10.5.3 Activation via GPIO activation in terrupt request

TM

DD28F032)

6.7.3 XISACTL (0x0B00

and

7.2.8 SPKRCLENREG

9.2.9

User’s Manual U14272EJ3V0UM

7

Page Description
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p. 298
p. 301
pp. 303, 304

p. 308

p. 314

pp. 315, 316
p. 320
p. 321
p. 324
p. 325
p. 327
p. 328

Major Revisions in This Edition (3/5)

Modification of desc ri ption of Cautions in
Modification of desc ri ptions in
Addition of
Modification of desc ri ption for bit 6 in
Modification of value at reset for bit 7 in
Modification of desc ri ption for bit 2 to 0 in
Modification of desc ri ption for bit 4 in
Modification of value at reset for bit 15 in
Modification and addition of descriptions in
Modification of desc ri ption in
Modification of R/W f or bi ts 15 to 8 in
Modification of desc ri ption in
Modification of desc ri ption for bit 15 in
Modification of desc ri ption for bit 7 in
Addition of Caution in
Modification of location of Note in
Modification of desc ri ption for bits 5 to 0 in
Addition of description i n
Modification of desc ri ption in
Addition of description i n
Modification of values at reset for bits 2 to 0 in
Modification of desc ri ption in
Addition of Note in
Modification of
Modification of desc ri ption and addition of Caution in
Modification of address es in

(0x0B00 0162)

Modification of values at reset for bits 11, 10 and 5 and addition of Caution in

(0x0B00 016E)

Modification of values at reset for bits 11, 10 and 5 and addition of Caution in

(0x0B00 017E)

Addition of descriptions in
Modification of desc ri ption in
Modification of desc ri ption in
Modification of desc ri ption for bits 1 and 0 in
Modification of desc ri ptions for bits 14 to 10 and bits 4 t o 0 i n
Modification and addition of descriptions for bits 2 t o 0 i n
Modification of signal nam e i n

through

10.6.5

Figure 14-6. Touch/Release Detection Timing

Figure 14-7. A/D Port Scan Timing

10.6.1

10.6.8

13.2.5 16-bit bus cycles

13.3.15 KEYEN (0x0B00 031C)

14.1 General

14.3.6 PIUASCNREG (0x0B00 0130)
Table 14-4. PIUASCNREG Bit M an ipulation and States

14.3.7 PIUAMSKREG (0x0B00 0132)

Table 14-7. Mask Clear During Scan Sequencer Operation

15.2.1 SDMADATREG (0x0B00 0160)

15.3.1 Output (speaker)

16.2.6 Interrupts and status reporting
Table 16-3. KIU Interrupt Registers

17.1 General

10.5.4 Activation via DCD interrupt req u est

through

Table 14-3. PIUCNTREG Bit Man ipulation and States

10.6.4

10.7.1 PMUINTREG (0x0B00 00A0)

10.7.2 PMUCNTREG (0x0B00 00A2)

10.7.4 PMUDIVREG (0x0B00 00AC)

10.7.5 DRAMHIBCTL (0x0B00 00B2)

11.2.2 (3) ECMPHREG (0x0B00 00CC)

13.1.3 General-purpose registers

13.3.5 GPDATHREG (0x0B00 0308)

13.3.19 PCS1STRA (0x0B00 0326)

13.3.23 LCDGPMODE (0x0B00 032E)

14.3.4 PIUSTBLREG (0x0B00 0128)

14.3.8 PIUCIVLREG (0x0B00 013E)

15.1 General

and

15.2.2 MDMADATREG

and

15.3.2 Input (microphone)

16.3.3 KIUSCANS (0x0B00 0192)

16.3.4 KIUWKS (0x0B00 0194)

16.3.6 KIUINT (0x0B00 0198)

15.2.6 SCNVC_END

15.2.12 MCNVC_END

8

User’s Manual U14272EJ3V0UM

Page Description
p. 333
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p. 344

p. 345

p. 346
p. 346

p. 348
p. 349

pp. 350, 351
p. 352
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p. 360
p. 361
pp. 362, 364, 376
p. 365
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pp. 381, 383, 395
p. 384
p. 387
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p. 394
p. 395
p. 397

Major Revisions in This Edition (4/5)

Modification of signal nam es in
Modification of desc ri ption for bit 0 in
Addition of Caution for bit 4 i n
Modification of desc ri ption for bit 7 in
Modification of desc ri ption and addition of Caution for bit 0 in
Modification of desc ri ptions for bits 7, 4, 3, and 0 i n
Modification of desc ri ption for bit 6 in

0x31)

Modification of desc ri ption for bits 7 and 6 and addition of description in

(Index: 0x13, 0x1B, 0x23, 0x2B, 0x33)

Addition of description i n
Modification of Remark for bits 5 to 0 in

0x35)

Modification of desc ri ption for bit 2 in
Modification of desc ri ption for bits 1 and 0 and addition of description in

(Index: 0x2F)

Addition of
Addition of
Addition of function f or bi t 2 in
Modification of desc ri ption in
Modification of figure i n
Addition of Caution in
Modification of desc ri ption in
Modification of values at reset in
Addition of description i n
Modification of desc ri ptions for bits 2 to 0 in
Modification of R/W and addition of description in
Modification of desc ri ptions for bits 7 to 4 in
Modification of R/W f or bi t 1 in
Addition of description and Caution in
Modification of desc ri ption in
Modification of values at reset in
Addition of description i n
Modification of desc ri ptions for bits 2 to 0 in
Modification of R/W and addition of description in
Modification of desc ri ptions for bits 7 to 4 in
Addition of description i n
Modification of R/W f or bi t 1 in

17.5 Memory Mapping of CompactFlash Card

17.6 Controlling Bus When CompactFlash Card Is Used

19.1 General

Figure 17-1. CompactFlash Interrupt Logic

17.3.3 CFG_REG_1 (0x0B00 08FE)

17.4.3 PWRRSETDRV (Index: 0x02)

17.4.4 ITGENCREG (Index: 0x03)

17.4.5 CDSTCHGREG (Index: 0x04)

17.4.8 IOCTRL_REG (Index: 0x07)

17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29,

17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34)

17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D,

17.4.20 GLOCTRLREG (Index: 0x1E)

18.2.3 LEDCNTREG (0x0B00 0248)

18.2.4 LEDASTCREG (0x0B00 024A)

18.3 Operation Flow

Table 19-1. SIU1 Registers

through

19.3.1

Table 19-2. Correspondence between Baud Rates and Divisors

19.3.14 SIUACTMSK_1 (0x0C00 001C)

20.1 General

Table 20-1. SIU2 Registers

through

20.3.1

Table 20-2. Correspondence between Baud Rates and Divisors

20.3.13 SIUIRSEL_2 (0x0C00 008)

20.3.16 SIUACTMSK_2 (0x0C00 000C)

19.3.3, 19.3.5

19.3.7 SIUFC_1 (0x0C00 0012: Write)

19.3.10 SIULS_1 (0x0C00 0015)

19.3.11 SIUMS_1 (0x0C00 0016)

20.3.3, 20.3.5

20.3.7 SIUFC_2 (0x0C00 0002: Write)

20.3.10 SIULS_2 (0x0C00 0005)

20.3.11 SIUMS_2 (0x0C00 0006)

, and

, and

19.3.12

20.3.12

17.4.16 MEMSELn_REG

17.4.22 VOLTSELREG

User’s Manual U14272EJ3V0UM

9

Page Description
p. 399
p. 401
p. 406
p. 420
p. 428
p. 429
p. 433
pp. 436 to 438
pp. 439 to 444

Major Revisions in This Edition (5/5)

Modification of desc ri ption in
Modification of bus width in
Modification of desc ri ption in
Addition of Remark in
Addition of Remark in
Addition of Caution in
Addition of Caution in
Addition of
Addition of

APPENDIX A RESTRI CTIONS ON V
APPENDIX B INDEX

21.4.11 LCDCFGREG0 (0x0A00 0414)

21.4.22 CPINDCTREG (0x0A00 047E)

21.4.23 CPALDATREG (0x0A00 0480)
Table 23-1. Coprocessor 0 Hazards

The mark shows major revised points.

21.1.1 LCD interface

Figure 21-1. LCD Controller Block Diagram

21.3.4 Frame buffer memory and FIFO

R

4181

10

User’s Manual U14272EJ3V0UM

PREFACE

Readers This manual targets users who intend to understand the functions of the V

to design application systems using this microprocessor.

4181 to users, following the

Purpose This manual introduces the hardware functions of the V

organization described below.

4181: Hardware User’s Manual (this manual)

Organization Two manuals are available for the V

R

and Architecture User’s Manual common to the V

R

4100 SeriesTM.

R

4181 and

R

Hardware

User’s Manual

• Pin functions

• Physical address space

• Function of Coprocessor 0

• Initialization interface

• Peripheral units

• Pipeline operation

• Cache organization and memory
management system

• Exception processing

• Interrupts

Architecture

User’s Manual

• Instruction set

How to read this manual It is assumed that the reader of this manual has general knowledge in the fields of

electric engineering, logic circuits, microcomputers, and SDRAMs.
To learn about the overall functions of the VR4181,

→ Read this manual in sequential order.

To learn about instruction sets,

→ Read V

R4100 Series Architecture User’s Manual that is separately

available.

To learn about electrical specifications,

→ Refer to Data Sheet that is separately available.

Conventions Data significance: Higher on left and lower on right

Active low: XXX# (trailing # after pin and signal names)

Note: Description of item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information

Numeric representation: binary/decimal ... XXXX

hexadecimal ... 0xXXXX

Prefixes representing an exponent of 2 (for address space or memory capacity):

K (kilo) … 2
M (mega) … 2
G (giga) … 230 = 1024
T (tera) … 240 = 1024
P (peta) … 250 = 1024
E (exa) … 260 = 1024

10

= 1024

20

= 1024

2

3

4

5

6

User’s Manual U14272EJ3V0UM

11

Related Documents When using this manual, also refer to the following documents.

Document name Document number

VR4181 Hardware User’s Manual This manual

PD30181 (VR4181) Data Sheet U14273E

µ

VR4100 Series Architect ure User’s Manual U15509E
VR Series TM Programming Guide Application Note U10710E

The related documents indicated here may include preliminary version. However,
preliminary versions are not marked as such.

12

User’s Manual U14272EJ3V0UM

CONTENTS

CHAPTER 1 INTRODUCTION ............................................................................................................. 29

1.1 Features .................................................................................................................................... 29

1.2 Ordering Information ............................................................................................................... 30

1.3 V

4181 Key Features ............................................................................................................... 30

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1.3.1 CPU core ..................................................................................................................................... 31

1.3.2 Bus interface ............................................................................................................................... 31

1.3.3 Memory interface ......................................................................................................................... 32

1.3.4 DMA controller (DCU) .................................................................................................................. 32

1.3.5 Interrupt controller (ICU) .............................................................................................................. 32

1.3.6 Real-time clock ............................................................................................................................ 32

1.3.7 Audio output (D/A converter) ....................................................................................................... 32

1.3.8 Touch panel interface and audio input (A/D converter) ............................................................... 32

1.3.9 CompactFlash interface (ECU) ................................................................................................... 32

1.3.10 Serial interface channel 1 (SIU1) .............................................................................................. 32

1.3.11 Serial interface channel 2 (SIU2) .............................................................................................. 32

1.3.12 Clocked serial interface (CSI) .................................................................................................... 33

1.3.13 Keyboard interface (KIU) ........................................................................................................... 33

1.3.14 General-purpose I/O .................................................................................................................. 33

1.3.15 Programmable chip selects ....................................................................................................... 34

1.3.16 LCD interface ......................................................................................................... ................... 34

1.3.17 Wake-up events ........................................................................................................................ 35

1.4 VR4110 CPU Core ..................................................................................................................... 35

1.4.1 CPU registers .............................................................................................................................. 37

1.4.2 CPU instruction set overview ...................................................................................................... 38

1.4.3 Data formats and addressing ...................................................................................................... 40

1.4.4 CP0 registers ............................................................................................................................... 43

1.4.5 Floating-point unit (FPU) ............................................................................................................. 44

1.4.6 Memory management unit ........................................................................................................... 44

1.4.7 Cache .......................................................................................................................................... 44

1.4.8 Instruction pipeline ...................................................................................................................... 44

1.4.9 Power modes .............................................................................................................................. 45

1.4.10 Code compatibility ..................................................................................................................... 46

1.5 Clock Interface ......................................................................................................................... 47

CHAPTER 2 PIN FUNCTIONS ............................................................................................................ 50

2.1 Pin Configuration ..................................................................................................................... 50

2.2 Pin Function Description ........................................................................................................ 52

2.2.1 System bus interface signals ....................................................................................................... 52

2.2.2 LCD interface signals .................................................................................................................. 54

2.2.3 Initialization interface signals ...................................................................................................... 55

2.2.4 Battery monitor interface signals ................................................................................................. 55

2.2.5 Clock interface signals ................................................................................................................ 55

2.2.6 Touch panel interface and audio interface signals ...................................................................... 56

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2.2.7 LED interface signals ................................................................................................................... 56

2.2.8 CompactFlash interface and keyboard interface signals ............................................................. 56

2.2.9 Serial interface channel 1 signals ................................................................................................ 57

2.2.10 IrDA interface signals ................................................................................................................ 58

2.2.11 General-purpose I/O signals ...................................................................................................... 58

2.2.12 Dedicated VDD/GND signals ...................................................................................................... 59

2.3 Pin Status in Specific Status .................................................................................................. 60

2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63

2.5 Pin I/O Circuits ......................................................................................................................... 66

CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67

3.1 Coprocessor 0 (CP0) ............................................................................................................... 67

3.2 Details of CP0 Registers ......................................................................................................... 69

3.2.1 Index register (0) ......................................................................................................................... 69

3.2.2 Random register (1) ..................................................................................................................... 69

3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ...................................................................................... 70

3.2.4 Context register (4) ...................................................................................................................... 71

3.2.5 PageMask register (5) ................................................................................................................. 72

3.2.6 Wired register (6) ......................................................................................................................... 73

3.2.7 BadVAddr register (8) .................................................................................................................. 74

3.2.8 Count register (9) ......................................................................................................................... 74

3.2.9 EntryHi register (10) .................................................................................................................... 75

3.2.10 Compare register (11) ............................................................................................................... 76

3.2.11 Status register (12) .................................................................................................................... 76

3.2.12 Cause register (13) .................................................................................................................... 79

3.2.13 Exception Program Counter (EPC) register (14) ....................................................................... 81

3.2.14 Processor Revision Identifier (PRId) register (15) .....................................................................82

3.2.15 Config register (16) .................................................................................................................... 83

3.2.16 Load Linked Address (LLAddr) register (17) .............................................................................84

3.2.17 WatchLo (18) and WatchHi (19) registers ................................................................................. 85

3.2.18 XContext register (20) ............................................................................................................... 86

3.2.19 Parity Error register (26) ............................................................................................................ 87

3.2.20 Cache Error register (27) ........................................................................................................... 87

3.2.21 TagLo (28) and TagHi (29) registers ......................................................................................... 88

3.2.22 ErrorEPC register (30) ............................................................................................................... 89

CHAPTER 4 MEMORY MANAGEMENT SYSTEM ............................................................................ 91

4.1 Overview ................................................................................................................................... 91

4.2 Physical Address Space ......................................................................................................... 92

4.2.1 ROM space .................................................................................................................................. 93

4.2.2 External system bus space .......................................................................................................... 93

4.2.3 Internal I/O space ........................................................................................................................ 94

4.2.4 DRAM space ............................................................................................................................... 95

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CHAPTER 5 INITIALIZATION INTERFACE ....................................................................................... 96

5.1 Reset Function ......................................................................................................................... 96

5.1.1 RTC reset .................................................................................................................................... 97

5.1.2 RSTSW reset .............................................................................................................................. 98

5.1.3 Deadman’s Switch reset .............................................................................................................. 99

5.1.4 Software shutdown ...................................................................................................................... 100

5.1.5 HALTimer shutdown .................................................................................................................... 101

5.2 Power-on Sequence ................................................................................................................ 102

5.3 Reset of CPU Core ................................................................................................................... 104

5.3.1 Cold Reset ................................................................................................................................... 104

5.3.2 Soft Reset .................................................................................................................................... 105

5.4 Notes on Initialization ............................................................................................................. 106

5.4.1 CPU core ..................................................................................................................................... 106

5.4.2 Internal peripheral units ............................................................................................................... 106

5.4.3 Returning from power mode ........................................................................................................ 107

CHAPTER 6 BUS CONTROL .............................................................................................................. 108

6.1 MBA Host Bridge ..................................................................................................................... 108

6.1.1 MBA Host Bridge ROM and register address space ................................................................... 109

6.1.2 MBA modules address space ...................................................................................................... 109

6.2 Bus Control Registers ............................................................................................................. 110

6.2.1 BCUCNTREG1 (0x0A00 0000) ................................................................................................... 111

6.2.2 CMUCLKMSK (0x0A00 0004) ..................................................................................................... 112

6.2.3 BCUSPEEDREG (0x0A00 000C) ................................................................................................ 113

6.2.4 BCURFCNTREG (0x0A00 0010) ................................................................................................ 115

6.2.5 REVIDREG (0x0A00 0014) ......................................................................................................... 116

6.2.6 CLKSPEEDREG (0x0A00 0018) ................................................................................................. 117

6.3 ROM Interface .......................................................................................................................... 118

6.3.1 External ROM devices memory mapping .................................................................................... 118

6.3.2 Connection to external ROM (x 16) devices ................................................................................ 119

6.3.3 Example of ROM connection ....................................................................................................... 120

6.3.4 External ROM cycles ................................................................................................................... 125

6.4 DRAM Interface ........................................................................................................................ 128

6.4.1 EDO DRAM configuration ............................................................................................................ 128

6.4.2 Mixed memory mode (EDO DRAM only) ..................................................................................... 129

6.4.3 EDO DRAM timing parameters ................................................................................................... 129

6.4.4 SDRAM configuration .................................................................................................................. 130

6.5 Memory Controller Register Set ............................................................................................. 131

6.5.1 EDOMCYTREG (0x0A00 0300) .................................................................................................. 131

6.5.2 MEMCFG_REG (0x0A00 0304) .................................................................................................. 133

6.5.3 MODE_REG (0x0A00 0308) ....................................................................................................... 135

6.5.4 SDTIMINGREG (0x0A00 030C) .................................................................................................. 136

6.6 ISA Bridge ................................................................................................................................ 137

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6.7 ISA Bridge Register Set ........................................................................................................... 137

6.7.1 ISABRGCTL (0x0B00 02C0) ....................................................................................................... 138

6.7.2 ISABRGSTS (0x0B00 02C2) ....................................................................................................... 139

6.7.3 XISACTL (0x0B00 02C4) ............................................................................................................. 140

CHAPTER 7 DMA CONTROL UNIT (DCU) ....................................................................................... 142

7.1 General ...................................................................................................................................... 142

7.2 DCU Registers ......................................................................................................................... 144

7.2.1 Microphone destination 1 address registers ................................................................................ 145

7.2.2 Microphone destination 2 address registers ................................................................................ 146

7.2.3 Speaker source 1 address registers ............................................................................................ 147

7.2.4 Speaker source 2 address registers ............................................................................................ 148

7.2.5 DMARSTREG (0x0A00 0040) ..................................................................................................... 149

7.2.6 AIUDMAMSKREG (0x0A00 0046) ............................................................................................... 149

7.2.7 MICRCLENREG (0x0A00 0658) .................................................................................................. 150

7.2.8 SPKRCLENREG (0x0A00 065A) ................................................................................................. 150

7.2.9 MICDMACFGREG (0x0A00 065E) .............................................................................................. 151

7.2.10 SPKDMACFGREG (0x0A00 0660) ............................................................................................ 152

7.2.11 DMAITRQREG (0x0A00 0662) .................................................................................................. 153

7.2.12 DMACTLREG (0x0A00 0664) .................................................................................................... 154

7.2.13 DMAITMKREG (0x0A00 0666) .................................................................................................. 155

CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) ............................................................. 156

8.1 Overview ................................................................................................................................... 156

8.2 Operation of CSI ....................................................................................................................... 156

8.2.1 Transmit/receive operations ........................................................................................................ 156

8.2.2 SCK phase and CSI transfer timing ............................................................................................. 157

8.2.3 CSI transfer types ........................................................................................................................ 159

8.2.4 Transmit and receive FIFOs ........................................................................................................ 160

8.3 CSI Registers ............................................................................................................................ 160

8.3.1 CSIMODE (0x0B00 0900) ........................................................................................................... 161

8.3.2 CSIRXDATA (0x0B00 0902) ........................................................................................................ 163

8.3.3 CSITXDATA (0x0B00 0904) ........................................................................................................ 163

8.3.4 CSILSTAT (0x0B00 0906) ........................................................................................................... 164

8.3.5 CSIINTMSK (0x0B00 0908) ......................................................................................................... 166

8.3.6 CSIINTSTAT (0x0B00 090A) ....................................................................................................... 167

8.3.7 CSITXBLEN (0x0B00 090C) ........................................................................................................ 169

8.3.8 CSIRXBLEN (0x0B00 090E) ....................................................................................................... 170

CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) ............................................................................ 171

9.1 Overview ................................................................................................................................... 171

9.2 Register Set .............................................................................................................................. 173

9.2.1 SYSINT1REG (0x0A00 0080) ..................................................................................................... 174

9.2.2 MSYSINT1REG (0x0A00 008C) .................................................................................................. 176

9.2.3 NMIREG (0x0A00 0098) .............................................................................................................. 178

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9.2.4 SOFTINTREG (0x0A00 009A) .................................................................................................... 179

9.2.5 SYSINT2REG (0x0A00 0200) ..................................................................................................... 180

9.2.6 MSYSINT2REG (0x0A00 0206) .................................................................................................. 181

9.2.7 PIUINTREG (0x0B00 0082) ........................................................................................................ 182

9.2.8 AIUINTREG (0x0B00 0084) ........................................................................................................ 183

9.2.9 KIUINTREG (0x0B00 0086) ........................................................................................................ 184

9.2.10 MPIUINTREG (0x0B00 008E) ................................................................................................... 185

9.2.11 MAIUINTREG (0x0B00 0090) ................................................................................................... 186

9.2.12 MKIUINTREG (0x0B00 0092) ................................................................................................... 187

CHAPTER 10 POWER MANAGEMENT UNIT (PMU) ...................................................................... 188

10.1 General ................................................................................................................................... 188

10.2 V

4181 Power Mode .............................................................................................................. 188

R

10.2.1 Power mode and state transition ............................................................................................... 188

10.3 Reset Control ......................................................................................................................... 191

10.3.1 RTC reset .................................................................................................................................. 191

10.3.2 RSTSW reset ............................................................................................................................ 192

10.3.3 Deadman’s Switch reset ............................................................................................................ 192

10.3.4 Preserving DRAM data on RSTSW reset .................................................................................. 192

10.4 Shutdown Control ................................................................................................................. 193

10.4.1 HALTimer shutdown .................................................................................................................. 193

10.4.2 Software shutdown .................................................................................................................... 193

10.4.3 BATTINH shutdown ................................................................................................................... 193

10.5 Power-on Control ................................................................................................................... 194

10.5.1 Activation via Power Switch interrupt request ........................................................................... 195

10.5.2 Activation via CompactFlash interrupt request .......................................................................... 196

10.5.3 Activation via GPIO activation interrupt request ........................................................................ 197

10.5.4 Activation via DCD interrupt request ......................................................................................... 198

10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request ....................................................... 200

10.6 DRAM Interface Control ........................................................................................................ 201

10.6.1 Entering Hibernate mode (EDO DRAM) .................................................................................... 201

10.6.2 Entering Hibernate mode (SDRAM) .......................................................................................... 202

10.6.3 Exiting Hibernate mode (EDO DRAM) ...................................................................................... 203

10.6.4 Exiting Hibernate mode (SDRAM) ............................................................................................. 204

10.6.5 Entering Suspend mode (EDO DRAM) ..................................................................................... 205

10.6.6 Entering Suspend mode (SDRAM) ............................................................................................ 206

10.6.7 Exiting Suspend mode (EDO DRAM) ........................................................................................ 207

10.6.8 Exiting Suspend mode (SDRAM) .............................................................................................. 207

10.7 Register Set ............................................................................................................................ 208

10.7.1 PMUINTREG (0x0B00 00A0) .................................................................................................... 209

10.7.2 PMUCNTREG (0x0B00 00A2) .................................................................................................. 211

10.7.3 PMUWAITREG (0x0B00 00A8) ................................................................................................. 213

10.7.4 PMUDIVREG (0x0B00 00AC) ................................................................................................... 214

10.7.5 DRAMHIBCTL (0x0B00 00B2) .................................................................................................. 215

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CHAPTER 11 REALTIME CLOCK UNIT (RTC) ................................................................................ 216

11.1 General .................................................................................................................................... 216

11.2 Register Set ............................................................................................................................ 216

11.2.1 ElapsedTime registers ............................................................................................................... 217

11.2.2 ElapsedTime compare registers ................................................................................................ 219

11.2.3 RTCLong1 registers .................................................................................................................. 221

11.2.4 RTCLong1 count registers ......................................................................................................... 223

11.2.5 RTCLong2 registers .................................................................................................................. 225

11.2.6 RTCLong2 count registers ......................................................................................................... 227

11.2.7 RTC interrupt register ................................................................................................................ 229

CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) ........................................................................... 230

12.1 General .................................................................................................................................... 230

12.2 Register Set ............................................................................................................................ 230

12.2.1 DSUCNTREG (0x0B00 00E0) ............................................................................................... .... 231

12.2.2 DSUSETREG (0x0B00 00E2) ................................................................................................... 232

12.2.3 DSUCLRREG (0x0B00 00E4) ................................................................................................... 233

12.2.4 DSUTIMREG (0x0B00 00E6) .................................................................................................... 234

12.3 Register Setting Flow ............................................................................................................ 235

CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) ...................................................................... 236

13.1 Overview ................................................................................................................................. 236

13.1.1 GPIO pins and alternate functions ............................................................................................. 236

13.1.2 I/O direction control ................................................................................................................... 238

13.1.3 General-purpose registers ......................................................................................................... 238

13.2 Alternate Functions Overview .............................................................................................. 238

13.2.1 Clocked serial interface (CSI) .................................................................................................... 238

13.2.2 Serial interface channels 1 and 2 .............................................................................................. 239

13.2.3 LCD interface ............................................................................................................................. 241

13.2.4 Programmable chip selects ....................................................................................................... 242

13.2.5 16-bit bus cycles ........................................................................................................................ 242

13.2.6 General purpose input/output .................................................................................................... 242

13.2.7 Interrupt requests and wake-up events ..................................................................................... 243

13.3 Register Set ............................................................................................................................ 244

13.3.1 GPMD0REG (0x0B00 0300) ...................................................................................................... 246

13.3.2 GPMD1REG (0x0B00 0302) ...................................................................................................... 248

13.3.3 GPMD2REG (0x0B00 0304) ...................................................................................................... 250

13.3.4 GPMD3REG (0x0B00 0306) ...................................................................................................... 252

13.3.5 GPDATHREG (0x0B00 0308) ................................................................................................... 254

13.3.6 GPDATLREG (0x0B00 030A) .................................................................................................... 255

13.3.7 GPINTEN (0x0B00 030C) .......................................................................................................... 256

13.3.8 GPINTMSK (0x0B00 030E) ....................................................................................................... 257

13.3.9 GPINTTYPH (0x0B00 0310) ...................................................................................................... 258

13.3.10 GPINTTYPL (0x0B00 0312) .................................................................................................... 260

13.3.11 GPINTSTAT (0x0B00 0314) .................................................................................................... 262

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13.3.12 GPHIBSTH (0x0B00 0316) ...................................................................................................... 263

13.3.13 GPHIBSTL (0x0B00 0318) ...................................................................................................... 264

13.3.14 GPSICTL (0x0B00 031A) ........................................................................................................ 265

13.3.15 KEYEN (0x0B00 031C) ........................................................................................................... 267

13.3.16 PCS0STRA (0x0B00 0320) ..................................................................................................... 268

13.3.17 PCS0STPA (0x0B00 0322) ..................................................................................................... 268

13.3.18 PCS0HIA (0x0B00 0324) ........................................................................................................ 269

13.3.19 PCS1STRA (0x0B00 0326) ..................................................................................................... 270

13.3.20 PCS1STPA (0x0B00 0328) ..................................................................................................... 270

13.3.21 PCS1HIA (0x0B00 032A) ........................................................................................................ 271

13.3.22 PCSMODE (0x0B00 032C) ..................................................................................................... 272

13.3.23 LCDGPMODE (0x0B00 032E) ................................................................................................ 273

13.3.24 MISCREGn (0x0B00 0330 to 0x0B00 034E) ........................................................................... 274

CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) ................................................................. 275

14.1 General ................................................................................................................................... 275

14.1.1 Block diagrams .......................................................................................................................... 276

14.2 Scan Sequencer State Transition ......................................................................................... 278

14.3 Register Set ............................................................................................................................ 280

14.3.1 PIUCNTREG (0x0B00 0122) ..................................................................................................... 281

14.3.2 PIUINTREG (0x0B00 0124) ...................................................................................................... 284

14.3.3 PIUSIVLREG (0x0B00 0126) .................................................................................................... 285

14.3.4 PIUSTBLREG (0x0B00 0128) ................................................................................................... 286

14.3.5 PIUCMDREG (0x0B00 012A) .................................................................................................... 287

14.3.6 PIUASCNREG (0x0B00 0130) .................................................................................................. 289

14.3.7 PIUAMSKREG (0x0B00 0132) .................................................................................................. 291

14.3.8 PIUCIVLREG (0x0B00 013E) .................................................................................................... 292

14.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) .................... 293

14.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) ........................................................................ 294

14.4 State Transition Flow ............................................................................................................ 295

14.5 Relationships among TPX, TPY, ADIN, and AUDIOIN Pins and States ............................ 297

14.6 Timing ..................................................................................................................................... 298

14.6.1 Touch/release detection timing ................................................................................................. 298

14.6.2 A/D port scan timing .................................................................................................................. 298

14.7 Data Loss Conditions ............................................................................................................ 299

CHAPTER 15 AUDIO INTERFACE UNIT (AIU) ................................................................................ 301

15.1 General ................................................................................................................................... 301

15.2 Register Set ............................................................................................................................ 302

15.2.1 SDMADATREG (0x0B00 0160) ................................................................................................. 303

15.2.2 MDMADATREG (0x0B00 0162) ................................................................................................ 304

15.2.3 DAVREF_SETUP (0x0B00 0164) ............................................................................................. 305

15.2.4 SODATREG (0x0B00 0166) ...................................................................................................... 306

15.2.5 SCNTREG (0x0B00 0168) ........................................................................................................ 307

15.2.6 SCNVC_END (0x0B00 016E) ................................................................................................... 308

15.2.7 MIDATREG (0x0B00 0170) ....................................................................................................... 309

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15.2.8 MCNTREG (0x0B00 0172) ........................................................................................................ 310

15.2.9 DVALIDREG (0x0B00 0178) ..................................................................................................... 311

15.2.10 SEQREG (0x0B00 017A) ........................................................................................................ 312

15.2.11 INTREG (0x0B00 017C) .......................................................................................................... 313

15.2.12 MCNVC_END (0x0B00 017E) ................................................................................................. 314

15.3 Operation Sequence ............................................................................................................. 315

15.3.1 Output (speaker) ........................................................................................................................ 315

15.3.2 Input (microphone) .................................................................................................................... 316

CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) ....................................................................... 317

16.1 General .................................................................................................................................... 317

16.2 Functional Description .......................................................................................................... 317

16.2.1 Automatic keyboard scan mode (Auto Scan mode) .................................................................. 318

16.2.2 Manual keyboard scan mode (Manual Scan mode) .................................................................. 318

16.2.3 Key press detection ................................................................................................................... 318

16.2.4 Scan operation .......................................................................................................................... 319

16.2.5 Reading scanned data ............................................................................................................... 320

16.2.6 Interrupts and status reporting ................................................................................................... 320

16.3 Register Set ............................................................................................................................ 321

16.3.1 KIUDATn (0x0B00 0180 to 0x0B00 018E) ................................................................................ 322

16.3.2 KIUSCANREP (0x0B00 0190) ................................................................................................... 323

16.3.3 KIUSCANS (0x0B00 0192) ........................................................................................................ 324

16.3.4 KIUWKS (0x0B00 0194) ............................................................................................................ 325

16.3.5 KIUWKI (0x0B00 0196) ............................................................................................................. 326

16.3.6 KIUINT (0x0B00 0198) .............................................................................................................. 327

CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) .................................................................. 328

17.1 General .................................................................................................................................... 328

17.2 Register Set Summary ........................................................................................................... 328

17.3 ECU Control Registers .......................................................................................................... 331

17.3.1 INTSTATREG (0x0B00 08F8) ................................................................................................... 331

17.3.2 INTMSKREG (0x0B00 08FA) .................................................................................................... 332

17.3.3 CFG_REG_1 (0x0B00 08FE) .................................................................................................... 333

17.4 ECU Registers ........................................................................................................................ 334

17.4.1 ID_REV_REG (Index: 0x00) ...................................................................................................... 334

17.4.2 IF_STAT_REG (Index: 0x01) ..................................................................................................... 335

17.4.3 PWRRSETDRV (Index: 0x02) ................................................................................................... 336

17.4.4 ITGENCTREG (Index: 0x03) ..................................................................................................... 337

17.4.5 CDSTCHGREG (Index: 0x04) ................................................................................................... 338

17.4.6 CRDSTATREG (Index: 0x05) .................................................................................................... 339

17.4.7 ADWINENREG (Index: 0x06) .................................................................................................... 340

17.4.8 IOCTRL_REG (Index: 0x07) ...................................................................................................... 341

17.4.9 IOADSLBnREG (Index: 0x08, 0x0C) ......................................................................................... 342

17.4.10 IOADSHBnREG (Index: 0x09, 0x0D) ...................................................................................... 342

17.4.11 IOSLBnREG (Index: 0x0A, 0x0E) ............................................................................................ 343

17.4.12 IOSHBnREG (Index: 0x0B, 0x0F) ........................................................................................... 343

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17.4.13 SYSMEMSLnREG (Index: 0x10, 0x18, 0x20, 0x28, 0x30) ...................................................... 344

17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29, 0x31) ........................................................ 344

17.4.15 SYSMEMELnREG (Index: 0x12, 0x1A, 0x22, 0x2A, 0x32) ..................................................... 345

17.4.16 MEMSELn_REG (Index: 0x13, 0x1B, 0x23, 0x2B, 0x33) ........................................................ 345

17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34) ....................................................... 346

17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D, 0x35) ...................................................... 346

17.4.19 DTGENCLREG (Index: 0x16) .................................................................................................. 347

17.4.20 GLOCTRLREG (Index: 0x1E) ................................................................................................. 348

17.4.21 VOLTSENREG (Index: 0x1F) .................................................................................................. 348

17.4.22 VOLTSELREG (Index: 0x2F) .................................................................................................. 349

17.5 Memory Mapping of CompactFlash Card ............................................................................ 350

17.6 Controlling Bus When CompactFlash Card Is Used .......................................................... 352

17.6.1 Controlling bus size ................................................................................................................... 352

17.6.2 Controlling wait .......................................................................................................................... 352

CHAPTER 18 LED CONTROL UNIT (LED) ...................................................................................... 353

18.1 General ................................................................................................................................... 353

18.2 Register Set ............................................................................................................................ 353

18.2.1 LEDHTSREG (0x0B00 0240) .................................................................................................... 354

18.2.2 LEDLTSREG (0x0B00 0242) ..................................................................................................... 355

18.2.3 LEDCNTREG (0x0B00 0248) .................................................................................................... 356

18.2.4 LEDASTCREG (0x0B00 024A) ................................................................................................. 357

18.2.5 LEDINTREG (0x0B00 024C) ..................................................................................................... 358

18.3 Operation Flow ....................................................................................................................... 359

CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) ........................................................................ 360

19.1 General ................................................................................................................................... 360

19.2 Clock Control Logic ............................................................................................................... 360

19.3 Register Set ............................................................................................................................ 361

19.3.1 SIURB_1 (0x0C00 0010: LCR7 = 0, Read) ............................................................................... 362

19.3.2 SIUTH_1 (0x0C00 0010: LCR7 = 0, Write) ............................................................................... 362

19.3.3 SIUDLL_1 (0x0C00 0010: LCR7 = 1) ........................................................................................ 362

19.3.4 SIUIE_1 (0x0C00 0011: LCR7 = 0) ........................................................................................... 363

19.3.5 SIUDLM_1 (0x0C00 0011: LCR7 = 1) ....................................................................................... 364

19.3.6 SIUIID_1 (0x0C00 0012: Read) ................................................................................................ 366

19.3.7 SIUFC_1 (0x0C00 0012: Write) ................................................................................................ 368

19.3.8 SIULC_1 (0x0C00 0013) ........................................................................................................... 371

19.3.9 SIUMC_1 (0x0C00 0014) .......................................................................................................... 372

19.3.10 SIULS_1 (0x0C00 0015) ......................................................................................................... 373

19.3.11 SIUMS_1 (0x0C00 0016) ........................................................................................................ 375

19.3.12 SIUSC_1 (0x0C00 0017) ......................................................................................................... 376

19.3.13 SIURESET_1 (0x0C00 0019) .................................................................................................. 376

19.3.14 SIUACTMSK_1 (0x0C00 001C) .............................................................................................. 377

19.3.15 SIUACTTMR_1 (0x0C00 001E) .............................................................................................. 378

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21

CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) ......................................................................... 379

20.1 General .................................................................................................................................... 379

20.2 Clock Control Logic ............................................................................................................... 379

20.3 Register Set ............................................................................................................................ 380

20.3.1 SIURB_2 (0x0C00 0000: LCR7 = 0, Read) ............................................................................... 381

20.3.2 SIUTH_2 (0x0C00 0000: LCR7 = 0, Write) ............................................................................... 381

20.3.3 SIUDLL_2 (0x0C00 0000: LCR7 = 1) ........................................................................................ 381

20.3.4 SIUIE_2 (0x0C00 0001: LCR7 = 0) ........................................................................................... 382

20.3.5 SIUDLM_2 (0x0C00 0001: LCR7 = 1) ....................................................................................... 383

20.3.6 SIUIID_2 (0x0C00 0002: Read) ................................................................................................. 385

20.3.7 SIUFC_2 (0x0C00 0002: Write) ................................................................................................. 387

20.3.8 SIULC_2 (0x0C00 0003) ........................................................................................................... 390

20.3.9 SIUMC_2 (0x0C00 0004) .......................................................................................................... 391

20.3.10 SIULS_2 (0x0C00 0005) ......................................................................................................... 392

20.3.11 SIUMS_2 (0x0C00 0006) ......................................................................................................... 394

20.3.12 SIUSC_2 (0x0C00 0007) ......................................................................................................... 395

20.3.13 SIUIRSEL_2 (0x0C00 0008) .................................................................................................... 395

20.3.14 SIURESET_2 (0x0C00 0009) .................................................................................................. 396

20.3.15 SIUCSEL_2 (0x0C00 000A) .................................................................................................... 396

20.3.16 SIUACTMSK_2 (0x0C00 000C) .............................................................................................. 397

20.3.17 SIUACTTMR_2 (0x0C00 000E) ............................................................................................... 398

CHAPTER 21 LCD CONTROLLER ..................................................................................................... 399

21.1 Overview ................................................................................................................................. 399

21.1.1 LCD interface ............................................................................................................................. 399

21.2 LCD Module Features ............................................................................................................ 400

21.3 LCD Controller Specification ................................................................................................ 402

21.3.1 Panel configuration and interface .............................................................................................. 402

21.3.2 Controller clocks ........................................................................................................................ 405

21.3.3 Palette ............................................................................................................... ........................ 406

21.3.4 Frame buffer memory and FIFO ................................................................................................ 406

21.3.5 Panel power ON/OFF sequence ................................................................................................ 407

21.3.6 Operation of LCD controller ....................................................................................................... 408

21.4 Register Set ............................................................................................................................ 413

21.4.1 HRTOTALREG (0x0A00 0400) .................................................................................................. 414

21.4.2 HRVISIBREG (0x0A00 0402) .................................................................................................... 414

21.4.3 LDCLKSTREG (0x0A00 0404) .................................................................................................. 415

21.4.4 LDCLKENDREG (0x0A00 0406) ............................................................................................... 415

21.4.5 VRTOTALREG (0x0A00 0408) .................................................................................................. 416

21.4.6 VRVISIBREG (0x0A00 040A) .................................................................................................... 416

21.4.7 FVSTARTREG (0x0A00 040C) ................................................................................................. 417

21.4.8 FVENDREG (0x0A00 040E) ...................................................................................................... 417

21.4.9 LCDCTRLREG (0x0A00 0410) .................................................................................................. 418

21.4.10 LCDINRQREG (0x0A00 0412) ................................................................................................ 419

21.4.11 LCDCFGREG0 (0x0A00 0414) ................................................................................................ 420

21.4.12 LCDCFGREG1 (0x0A00 0416) ................................................................................................ 421

22

User’s Manual U14272EJ3V0UM

21.4.13 FBSTADREG1 (0x0A00 0418) ................................................................................................ 422

21.4.14 FBSTADREG2 (0x0A00 041A) ................................................................................................ 422

21.4.15 FBENDADREG1 (0x0A00 0420) ............................................................................................. 423

21.4.16 FBENDADREG2 (0x0A00 0422) ............................................................................................. 423

21.4.17 FHSTARTREG (0x0A00 0424) ................................................................................................ 424

21.4.18 FHENDREG (0x0A00 0426) .................................................................................................... 424

21.4.19 PWRCONREG1 (0x0A00 0430) .............................................................................................. 425

21.4.20 PWRCONREG2 (0x0A00 0432) .............................................................................................. 426

21.4.21 LCDIMSKREG (0x0A00 0434) ................................................................................................ 427

21.4.22 CPINDCTREG (0x0A00 047E) ................................................................................................ 428

21.4.23 CPALDATREG (0x0A0 0480) .................................................................................................. 429

CHAPTER 22 PLL PASSIVE COMPONENTS ................................................................................... 430

CHAPTER 23 COPROCESSOR 0 HAZARDS ................................................................................... 431

4181 ....................................................................................... 436

APPENDIX A RESTRICTIONS ON V

R

A.1 RSTSW# During HALTimer Operation .................................................................................. 436

A.2 RSTSW# in Hibernate Mode ................................................................................................... 437

APPENDIX B INDEX ............................................................................................................................. 439

User’s Manual U14272EJ3V0UM

23

LIST OF FIGURES (1/3)

Fig. No. Title Page

1-1. Internal Block Diagram ................................................................................................................................ 30

1-2. V

1-3. CPU Registers ............................................................................................................................................ 37

1-4. CPU Instruction Formats (32-Bit Length Instruction) .................................................................................. 38

1-5. CPU Instruction Formats (16-Bit Length Instruction) .................................................................................. 39

1-6. Byte Address in Little-Endian Byte Order .................................................................................................... 41

1-7. Unaligned Word Accessing (Little Endian) .................................................................................................. 42

1-8. External Circuits of Clock Oscillator ............................................................................................................ 48

1-9. Incorrect Connection Circuits of Resonator ................................................................................................ 49

3-1. Index Register ............................................................................................................................................. 69

3-2. Random Register ........................................................................................................................................ 69

3-3. EntryLo0 and EntryLo1 Registers ............................................................................................................... 70

3-4. Context Register ......................................................................................................................................... 71

3-5. PageMask Register ..................................................................................................................................... 72

3-6. Positions Indicated by the Wired Register .................................................................................................. 73

3-7. Wired Register ............................................................................................................................................ 73

3-8. BadVAddr Register ..................................................................................................................................... 74

3-9. Count Register ............................................................................................................................................ 74

3-10. EntryHi Register .......................................................................................................................................... 75

3-11. Compare Register ....................................................................................................................................... 76

3-12. Status Register ............................................................................................................................................ 76

3-13. Status Register Diagnostic Status Field ...................................................................................................... 77

3-14. Cause Register ........................................................................................................................................... 79

3-15. EPC Register (When MIPS16 ISA Is Disabled) .......................................................................................... 81

3-16. EPC Register (When MIPS16 ISA Is Enabled) ........................................................................................... 82

3-17. PRId Register .............................................................................................................................................. 82

3-18. Config Register ........................................................................................................................................... 83

3-19. LLAddr Register .......................................................................................................................................... 84

3-20. WatchLo Register ........................................................................................................................................ 85

3-21. WatchHi Register ........................................................................................................................................ 85

3-22. XContext Register ........................................................................................................ ............................... 86

3-23. Parity Error Register .................................................................................................................................... 87

3-24. Cache Error Register .................................................................................................................................. 87

3-25. TagLo Register ............................................................................................................................................ 88

3-26. TagHi Register ............................................................................................................................................ 88

3-27. ErrorEPC Register (When MIPS16 ISA Is Disabled) .................................................................................. 90

3-28. ErrorEPC Register (When MIPS16 ISA Is Enabled) ................................................................................... 90

4110 CPU Core Internal Block Diagram ................................................................................................. 35

R

4-1. VR4181 Physical Address Space ................................................................................................................ 92

24

User’s Manual U14272EJ3V0UM

LIST OF FIGURES (2/3)

Fig. No. Title Page

5-1. RTC Reset .................................................................................................................................................. 97

5-2. RSTSW Reset ............................................................................................................................................. 98

5-3. Deadman’s Switch Reset ............................................................................................................................ 99

5-4. Software Shutdown ..................................................................................................................................... 100

5-5. HALTimer shutdown ................................................................................................................................... 101

5-6. V

5-7. VR4181 Activation Sequence (When Activation Is NG) .............................................................................. 103

5-8. Cold Reset .................................................................................................................................................. 104

5-9. Soft Reset ................................................................................................................................................... 105

6-1. VR4181 Internal Bus Structure .................................................................................................................... 108

6-2. ROM Read Cycle and Access Parameters ................................................................................................. 114

6-3. Ordinary ROM Read Cycle (WROMA(3:0) = 0101) .................................................................................... 125

6-4. PageROM Read Cycle (WROMA(3:0) = 0011, WPROM(2:0) = 001) ......................................................... 126

6-5. Flash Memory Read Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0101) .......................................................... 127

6-6. Flash Memory Write Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0100) .......................................................... 127

6-7. External EDO DRAM Configuration ............................................................................................................ 128

6-8. SDRAM Configuration ................................................................................................................................. 130

4181 Activation Sequence (When Activation Is OK) ............................................................................... 102

R

8-1. SCK and SI/SO Relationship ...................................................................................................................... 157

9-1. Outline of Interrupt Control .......................................................................................................................... 172

10-1. Transition of VR4181 Power Mode .............................................................................................................. 189

10-2. EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0) ........................................................................... 192

10-3. Activation via Power Switch Interrupt Request (BATTINH = H) .................................................................. 195

10-4. Activation via Power Switch Interrupt Request (BATTINH = L) .................................................................. 195

10-5. Activation via CompactFlash Interrupt Request (BATTINH = H) ................................................................ 196

10-6. Activation via CompactFlash Interrupt Request (BATTINH = L) ................................................................. 196

10-7. Activation via GPIO Activation Interrupt Request (BATTINH = H) .............................................................. 197

10-8. Activation via GPIO Activation Interrupt Request (BATTINH = L) ............................................................... 197

10-9. Activation via DCD Interrupt Request (BATTINH = H) ................................................................................ 199

10-10. Activation via DCD Interrupt Request (BATTINH = L) ................................................................................ 199

10-11. Activation via ElapsedTime Interrupt Request (BATTINH = H) ................................................................... 200

10-12. Activation via ElapsedTime Interrupt Request (BATTINH = L) ................................................................... 200

13-1. GPIO(15:0) Interrupt Request Detecting Logic ........................................................................................... 243

User’s Manual U14272EJ3V0UM

25

LIST OF FIGURES (3/3)

Fig. No. Title Page

14-1. PIU Peripheral Block Diagram .................................................................................................................... 276

14-2. Coordinate Detection Equivalent Circuits .................................................................................................... 277

14-3. Internal Block Diagram of PIU ..................................................................................................................... 277

14-4. Scan Sequencer State Transition Diagram ................................................................................................. 278

14-5. Interval Times and States ........................................................................................................................... 286

14-6. Touch/Release Detection Timing ................................................................................................................ 298

14-7. A/D Port Scan Timing .................................................................................................................................. 298

15-1. Speaker Output and AUDIOOUT Pin .......................................................................................................... 315

15-2. AUDIOIN Pin and Microphone Operation .................................................................................................... 316

16-1. SCANOUT Signal Output Timing ................................................................................................................ 319

17-1. CompactFlash Interrupt Logic ..................................................................................................................... 333

17-2. Mapping of CompactFlash Memory Space ................................................................................................. 350

17-3. Mapping of CompactFlash I/O Space ......................................................................................................... 351

19-1. SIU1 Block Diagram .................................................................................................................................... 360

20-1. SIU2 Block Diagram .................................................................................................................................... 379

21-1. LCD Controller Block Diagram .................................................................................................................... 401

21-2. View Rectangle and Horizontal/Vertical Blank ............................................................................................ 402

21-3. Position of Load Clock (LOCLK) ................................................................................................................. 403

21-4. Position of Frame Clock (FLM) ................................................................................................................... 404

21-5. Monochrome Panel ..................................................................................................................................... 408

21-6. Color Panel in 8-Bit Data Bus ..................................................................................................................... 409

21-7. Load Clock (LOCLK) ................................................................................................................................... 410

21-8. Frame Clock (FLM) ..................................................................................................................................... 410

21-9. LCD Timing Parameters .............................................................................................................................. 411

21-10. FLM Period .................................................................................................................................................. 411

22-1. Example of Connection of PLL Passive Components ................................................................................. 430

A-1. Mask Circuit for RSTSW# Signal ................................................................................................................ 436

A-2. Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM) .............................................................. 437

A-3. Release of Self-Refresh Mode by RSTSW# Signal (SDRAM) .................................................................... 438

26

User’s Manual U14272EJ3V0UM

LIST OF TABLES (1/2)

Table No. Title Page

1-1. Supported PClock and TClock Frequencies ............................................................................................... 31

1-2. Devices Supported by System Bus ............................................................................................................. 31

1-3. GPIO(31:0) Pin Functions ........................................................................................................................... 33

1-4. LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 34

1-5. Functions of LCD Interface Pins when LCD Controller Is Disabled ............................................................34

1-6. System Control Coprocessor (CP0) Register Definitions ........................................................................... 43

Series Processors ............................................................................. 46

1-7. List of Instructions Supported by V

3-1. CP0 Registers ............................................................................................................................................. 68

3-2. Cache Algorithm ......................................................................................................................................... 71

3-3. Mask Values and Page Sizes ..................................................................................................................... 72

3-4. Cause Register Exception Code Field ........................................................................................................ 80

4181 Physical Address Space ................................................................................................................ 93

4-1. V

R

4-2. ROM Address Map ..................................................................................................................................... 93

4-3. Internal I/O Space 1 .................................................................................................................................... 94

4-4. Internal I/O Space 2 .................................................................................................................................... 94

4-5. MBA Bus I/O Space .................................................................................................................................... 95

4-6. DRAM Address Map ................................................................................................................................... 95

R

6-1. Bus Control Registers ................................................................................................................................. 110

4181 EDO DRAM Capacity ..................................................................................................................... 129

6-2. V

R

6-3. Memory Controller Registers ...................................................................................................................... 131

6-4. ISA Bridge Registers ................................................................................................................................... 137

7-1. DCU Registers ............................................................................................................................................ 144

8-1. CSI Registers .............................................................................................................................................. 160

9-1. ICU Registers .............................................................................................................................................. 173

10-1. Overview of Power Modes .......................................................................................................................... 190

10-2. Operations During Reset ............................................................................................................................ 191

10-3. Operations During Shutdown ...................................................................................................................... 193

10-4. PMU Registers ............................................................................................................................................ 208

11-1. RTC Registers ............................................................................................................................................ 216

12-1. DSU Registers ............................................................................................................................................ 230

13-1. Alternate Functions of GPIO(15:0) Pins ...................................................................................................... 236

13-2. Alternate Functions of GPIO(31:16) Pins .................................................................................................... 237

13-3. CSI Interface Signals .................................................................................................................................. 238

13-4. Serial Interface Channel 1 (SIU1) Signals .................................................................................................. 239

User’s Manual U14272EJ3V0UM

27

LIST OF TABLES (2/2)

Table No. Title Page

13-5. Serial Interface Channel 1 (SIU1) Loopback Control .................................................................................. 239

13-6. Serial Interface Channel 2 (SIU2) Signals .................................................................................................. 240

13-7. Serial Interface Channel 2 (SIU2) Loopback Control .................................................................................. 240

13-8. STN Color LCD Interface Signals ............................................................................................................... 241

13-9. External LCD Controller Interface Signals .................................................................................................. 241

13-10. Programmable Chip Select Signals ............................................................................................................ 242

13-11. GIU Registers ........................................................................................................... ................................... 244

14-1. PIU Registers .............................................................................................................................................. 280

14-2. PIU Interrupt Registers ................................................................................................................................ 280

14-3. PIUCNTREG Bit Manipulation and States .................................................................................................. 283

14-4. PIUASCNREG Bit Manipulation and States ................................................................................................ 290

14-5. Detected Data and Page Buffers ................................................................................................................ 293

14-6. A/D Ports and Data Buffers ......................................................................................................................... 294

14-7. Mask Clear During Scan Sequencer Operation .......................................................................................... 295

15-1. AIU Registers .............................................................................................................................................. 302

15-2. AIU Interrupt Registers ................................................................................................................................ 302

16-1. Settings of Keyboard Scan Mode ................................................................................................................ 318

16-2. KIU Registers .............................................................................................................................................. 321

16-3. KIU Interrupt Registers ................................................................................................................................ 321

17-1. ECU Control Registers ................................................................................................................................ 328

17-2. ECU Registers ............................................................................................................................................ 329

18-1. LED Registers ............................................................................................................................................. 353

19-1. SIU1 Registers ............................................................................................................................................ 361

19-2. Correspondence between Baud Rates and Divisors .................................................................................. 365

19-3. Interrupt Function ........................................................................................................................................ 367

20-1. SIU2 Registers ............................................................................................................................................ 380

20-2. Correspondence between Baud Rates and Divisors .................................................................................. 384

20-3. Interrupt Function ........................................................................................................................................ 386

21-1. LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 399

21-2. Redefining LCD Interface Pins When LCD Controller Is Disabled .............................................................. 400

21-3. LCD Controller Parameters ......................................................................................................................... 412

21-4. LCD Controller Registers ............................................................................................................................ 413

23-1. Coprocessor 0 Hazards .............................................................................................................................. 432

23-2. Calculation Example of CP0 Hazard and Number of Instructions Inserted ................................................. 435

28

User’s Manual U14272EJ3V0UM

CHAPTER 1 INTRODUCTION

This chapter describes the outline of the VR4181 (µ PD30181), which is a 64-/32-bit microprocessor.

1.1 Features

The VR4181, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set

computer) architecture developed by MIPS

TM

, is one of the VR-Series microprocessor products manufactured by NEC

Electronics.

The VR4181 contains the VR4110TM CPU core of ultra-low-power consumption with cache memory, high-speed
product-sum operation unit, and memory management unit. It also has interface units for peripheral circuits such as
LCD controller, CompactFlash controller, DMA controller, keyboard interface, serial interface, IrDA interface, touch
panel interface, real-time clock, A/D converter and D/A converter required for the battery-driven portable information
equipment. The features of the VR

4181 are described below.

• Employs 0.25 µ m process

• 64-bit RISC VR4110 CPU core with pipeline clock up to 66 MHz (operation in 32-bit mode is available)

• Optimized 5-stage pipeline

• On-chip instruction and data caches with 4 KB each in size

• Write-back cache for reducing store operation that use the system bus

• 32-bit physical address space and 40-bit virtual address space, and 32 double-entry TLB

• Instruction set: MIPS III (with the FPU, LL and SC instructions left out) and MIPS16

• Supports MADD16 and DMADD16 instructions for executing a multiply-and-accumulate operation of 16-bit data
x 16-bit data + 64-bit data within one clock cycle

• Effective power management features, which include four operating modes, Fullspeed, Standby, Suspend and
Hibernate mode

• On-chip PLL and clock generator

• DRAM interface supporting 16-bit width SDRAM and EDO DRAM

• Ordinary ROM/PageROM/flash memory interface

• UMA based LCD controller

• 4-channel DMA controller

• RTC unit including 3-channel timers and counters

• Two UART-compatible serial interfaces and one clocked serial interface

• IrDA (SIR) interface

• Keyboard scan interface supporting 8 x 8 key matrix

• X-Y auto-scan touch panel interface

• CompactFlash interface compatible with ExCA

• A/D and D/A converters

• Includes ISA-subset bus

• Supply voltage: 2.5 V for CPU core, 3.3 V for I/O

• Package: 160-pin LQFP

User’s Manual U14272EJ3V0UM

29

1.2 Ordering Information

Part number Package Maximum internal

PD30181GM-66-8ED 160-pin plastic LQFP (fine pitch) (24 × 24) 66 MHz

µ

1.3 VR4181 Key Features

CHAPTER 1 INTRODUCTION

operating frequency

Figure 1-1. Internal Block Diagram

32.768
kHz

18.432

MHz

LCD Panel

LCD

controller

Clock

generator

RTC

VR4181

V

CPU core

Keyboard

(8 x 8)

DCU

R

4110

LED

EDO

DRAM/

SDRAM

Host Bridge

Buf

Memory

controller

TM

MBA

GIULED

ROM/

Flash

memory

System bus (ISA)

Bus

control

MBA bus

SIU1SIU2

RS-232-C

driver

PMU

ISA bus

module

ICU

IR

ISA bridge

CSIKIU A/DDSU

ECU

AIU

PIU

Buf

CompactFlash
card

D/A

Speaker

Microphone

Touch panel

Battery monitor

30

User’s Manual U14272EJ3V0UM

CHAPTER 1 INTRODUCTION

1.3.1 CPU core

The VR

4181 integrates an NEC Electronics’ VR4110 CPU core supporting both the MIPS III and MIPS16

instruction sets.

The VR4181 supports the following pipeline clock (PClock) and internal bus clock (TClock) frequencies. The
PClock is set by attaching pull-up or pull-down resistors to the CLKSEL(2:0) pins. The frequency of the TClock, which
is used in MBA bus, is set by PMUDIVREG register in Power Management Unit.

Table 1-1. Supported PClock and TClock Frequencies

PClock frequency TClock frequency

65.4 MHz 65.4/32.7/21.8 MHz

62.0 MHz 62.0/31.0/20.7 MHz

49.1 MHz 49.1/24.6 MHz

The VR4110 core of the VR4181 includes 4 KB of instruction cache and 4 KB of data cache.

The VR4110 core also supports the following power management modes:

• Fullspeed

• Standby

• Suspend

Note

• Hibernate

Note Suspend mode is supported only when the internal LCD controller has been disabled or the LCD panel

has been powered off.

1.3.2 Bus interface

The VR4181 incorporates single bus architecture. All external memory and I/O devices are connected to the same
22-bit address bus and 16-bit data bus. These external address and data bus are together called the system bus.

When the external bus operates at a very high speed, the DRAM data bus must be isolated from other low speed
devices such as ROM array. The VR4181 provides two pins, SYSEN# and SYSDIR, to control the data buffers for this
isolation.

The VR4181 supports the following types of devices connected to the system bus.

Table 1-2. Devices Supported by System Bus

Device Data width
ROM, flash memory 16 bits only
DRAM 16 bits only
CompactFlash 8 or 16 bits
External I/O 8 or 16 bits
External memory 8 or 16 bits

Six of the external bus interface signals, IORD#, IOWR#, IORDY, IOCS16#, MEMCS16# and RESET#, can be
individually defined as general-purpose I/O pins or LCD interface pin if they are not needed by external system
components.

User’s Manual U14272EJ3V0UM

31

CHAPTER 1 INTRODUCTION

1.3.3 Memory interface

4181 provides control for both ROM/flash memory and DRAM. Up to four 16-bit ROM/flash memory banks

The VR
may be supported utilizing either 32-Mbit or 64-Mbit single cycle or page mode devices. Bank mixing is not supported
for ROM/flash memory. When a system implements less than the maximum 4 banks of ROM/flash memory, unused
ROM chip select pins can be defined as general-purpose I/O pins.

The VR4181 also supports up to 2 banks of 1M x 16 or 4M x 16 EDO-type DRAM or SDRAM at bus frequencies of
up to 66 MHz. When both banks are EDO-type DRAM, bank mixing is supported.

1.3.4 DMA controller (DCU)

The VR4181 provides a 4-channel DMA controller to support internal DMA transfers. The 4 channels are allocated
as follows:

• Channel 1 - Audio input

• Channel 2 - Audio output

• Channel 3, 4 - Reserved

1.3.5 Interrupt controller (ICU)

The VR4181 provides an interrupt controller which combines all interrupt request sources into one of the VR4110
core interrupt inputs - NMI and Int(2:0). The interrupt controller also provides interrupt request status reporting.

1.3.6 Real-time clock

The VR4181 includes a real-time clock (RTC), which allows time keeping based on the 32.768 kHz clock as a
source. The RTC operates as long as the VR4181 remains powered.

1.3.7 Audio output (D/A converter)

The VR4181 provides a 1-channel 10-bit D/A converter for generating audio output.

1.3.8 Touch panel interface and audio input (A/D converter)

The VR4181 provides an 8-channel 10-bit A/D converter for interfacing to a touch panel, an external microphone,
and other types of analog input.

1.3.9 CompactFlash interface (ECU)

The VR4181 provides an ExCA-compatible bus controller supporting a single CompactFlash slot. This interface is
shared with the keyboard interface logic and must be disabled when an 8 x 8 key matrix is connected to the VR4181.

1.3.10 Serial interface channel 1 (SIU1)

The VR4181 provides a 16550 UART for implementing an RS-232-C type serial interface. When the serial
interface is not needed, each of the 7 serial interface pins can be individually redefined as general-purpose I/O pins.

1.3.11 Serial interface channel 2 (SIU2)

The serial interface channel 2 is also based on a 16550 UART but only reserves 2 pins for the interface. The serial
interface channel 2 can be configured in one of the following modes:

• Simple 2-wire serial interface using TxD2 and RxD2

• SIR-type IrDA interface using IRDIN and IRDOUT

• Full RS-232-C compatible interface using TxD2, RxD2 and 5 GPIO pins

32

User’s Manual U14272EJ3V0UM

CHAPTER 1 INTRODUCTION

1.3.12 Clocked serial interface (CSI)

4181 provides a clocked serial interface (CSI) which has an option to be configured as general-purpose I/O

The VR
pins. This interface supports slave mode operation only. The clocked serial interface requires allocation of 4 signals;
SI, SO, SCK, and FRM. The clock source for this interface is input on the pin assigned to SCK.

1.3.13 Keyboard interface (KIU)

The VR4181 provides support for an 8 x 8 key matrix. This keyboard interface can only be supported when the
CompactFlash interface is disabled and reconfigured to provide the SCANIN(7:0) inputs and the SCANOUT(7:0)
outputs.

1.3.14 General-purpose I/O

The VR4181 provides total 32 bits of general-purpose I/O. Sixteen of these, GPIO(31:16), are available through
pins allocated to other functions as shown in the following table. The DCD1#/GPIO29 is the only one of the 16 pins
that can cause the system’s waking up from a low power mode if enabled by software. The other pins have no
functions other than those listed below.

The remaining 16 bits of general-purpose I/O, GPIO(15:0), are allocated to pins by default. Each of these pins can
be configured to support a particular interface such as CSI, secondary serial interface (RS-232-C), programmable
chip selects, or color LCD control. Otherwise, each of these pins can be also defined as one of the following:

• General-purpose input

• General-purpose output

• Interrupt request input

• Wake-up input

Table 1-3. GPIO(31:0) Pin Functions

Pin designation Alternate function Pin designation Alt ernat e function
GPIO0 SI GPIO16 IORD#
GPIO1 SO GPIO17 IOWR#
GPIO2 SCK GPIO18 IORDY
GPIO3 PCS0# GPIO19 IOCS16#
GPIO4 −
GPIO5 DCD2# GPIO21 RESET#
GPIO6 RTS2# GPIO22 ROMCS0#
GPIO7 DTR2# GPIO23 ROMCS1#
GPIO8 DSR2# GPIO24 ROMCS2#
GPIO9 CTS2# GPIO25 RxD1
GPIO10 FRM/SYSCLK GPIO26 TxD1
GPIO11 PCS1# GPIO27 RTS1#
GPIO12 FPD4 GPIO28 CTS1#
GPIO13 FPD5 GPIO29 DCD1#
GPIO14 FPD6/CD1# GPIO30 DTR1#
GPIO15 FPD7/CD2# GPIO31 DSR1#

GPIO20

Note

M/UBE#

Note This signal supports input only.

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CHAPTER 1 INTRODUCTION

1.3.15 Programmable chip selects

4181 provides support for 2 programmable chip selects (PCS) which are also available as general-purpose

The VR
I/O pins. Each PCS can decode either I/O or memory accesses and can optionally be qualified to read, write, or both
read and write.

1.3.16 LCD interface

The LCD controller of the VR4181 is Unified Memory Architecture (UMA) based in which the frame buffer is part of
system DRAM. The LCD controller supports monochrome STN LCD panels having 4-bit data bus interfaces and color
STN LCD panels having 8-bit data bus interface. When interfacing to a color LCD panel, general-purpose I/O pins
must be allocated to provide the upper nibble of the 8-bit LCD data bus.

In monochrome mode, the LCD controller supports 1-bpp mode (mono), 2-bpp mode (4 gray levels) and 4-bpp
mode (16 gray levels). In color mode, it supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors).

The LCD controller includes a 256-entry x 18-bit color pallet. In 8-bpp color modes, the pallet is used to select 256
colors out of possible 262,144 colors.

The LCD controller supports LCD panels of up to 320 x 320 pixels. Typical LCD panel horizontal/vertical
resolutions are as follows.

Table 1-4. LCD Panel Resolutions (in Pixels, TYP.)

Horizontal resolution Vertical resolution

320 320
320 240
320 160
240 320
240 240
240 160
160 320
160 240
160 160

The LCD controller also provides power-on and power-down sequence control for the LCD panel via the VPLCD
and VPBIAS pins. Power sequencing is provided to prevent latch-up damage to the panel.

The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM
such as NEC Electronics’ µ PD16661. When the internal LCD controller is disabled, the SHCLK, LOCLK, VPLCD,
and VPBIAS pins are redefined as follows:

Table 1-5. Functions of LCD Interface Pins when LCD Controller Is Disabled

34

Redefined function Default function
LCDCS# SHCLK
MEMCS16# LOCLK
VPGPIO1 VPLCD
VPGPIO0 VPBIAS

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CHAPTER 1 INTRODUCTION

1.3.17 Wake-up events

The VR

4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these

modes, Hibernate is the lowest power mode and results in the powering off of all system components including the

2.5 V logic in the VR4181. The VR4181 3.3 V logic, which includes RTC, PMU, and non-volatile registers, remain
powered during the Hibernate mode, as does the system DRAM. Software can configure the VR4181 waking up from
the Hibernate mode and returning to Fullspeed mode due to any one of the following events:

• Activation of the DCD1# pin

• Activation of the POWER pin

• RTC alarm

• Activation of one of the GPIO(15:0) pins

• Activation of the CF_BUSY# pin (CompactFlash interrupt request (IREQ))

4111TM or the VR4121TM, the VR4181 will wake up after RTC reset without these

Remark Different from the V

R

wake-up events.

1.4 VR4110 CPU Core

Figure 1-2 shows the internal block diagram of the VR4110 CPU core.

In addition to the conventional high-performance integer operation units, this CPU core has the full-associative
format translation lookaside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even)
for one entry. Moreover, it also includes instruction cache, data cache, and bus interface.

Control(o)

Control(i)

Address/Data(o)

Address/Data(i)

Internal clock

Figure 1-2. V

Virtual address bus

Internal data bus

interface

R4110 CPU Core Internal Block Diagram

Bus

Data

cache

(4 KB)

Instruction

cache

(4 KB)

Clock

generator

CP0 CPU

TLB

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CHAPTER 1 INTRODUCTION

(1) CPU

The CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit
integer data path, and multiply-and-accumulate operation unit.

(2) Coprocessor 0 (CP0)

The CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks
whether there is an access between different memory segments (user, supervisor, and kernel) by executing
address translation. The translation lookaside buffer (TLB) translates virtual addresses to physical addresses.

(3) Instruction cache

The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 4 KB.

(4) Data cache

The data cache employs direct mapping, virtual index, physical tag, and writeback. Its capacity is 4 KB.

(5) CPU bus interface

The CPU bus interface controls data transmission/reception between the VR

4110 core and the MBA Host Bridge.
This interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output),
clock signal, and control signals such as interrupt requests.

(6) Clock generator

The following clock inputs are oscillated and supplied to internal units.

• 32.768 kHz clock for RTC unit

Crystal resonator input oscillated via an internal oscillator and supplied to the RTC unit.

• 18.432 MHz clock for serial interface and the VR4181’s reference operating clock

Crystal resonator input oscillated via an internal oscillator, and then multiplied by phase-locked loop (PLL) to
generate a pipeline clock (PClock). The internal bus clock (TClock) is generated from PClock and supplied to
peripheral units.

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1.4.1 CPU registers

4110 core has thirty-two 64-bit general-purpose registers (GPRs).

The VR
In addition, the processor provides the following special registers:

• 64-bit Program Counter (PC)

• 64-bit HI register, containing the integer multiply and divide upper doubleword result

• 64-bit LO register, containing the integer multiply and divide lower doubleword result

Two of the general-purpose registers have assigned functions as follows:

• r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to
be discarded. r0 can also be used as a source when a zero value is needed.

• r31 is the link register used by link instructions, such as JAL (Jump and Link) instruction. This register can be
used for other instructions. However, be careful that use of the register by a link instruction will not coincide
with use of the register for other operations.

The register group is provided within the CP0, to process exceptions and to manage addresses.
CPU registers can operate as either 32-bit or 64-bit registers, depending on the VR4181 processor mode of

operation.

The operation of the CPU registers differs depending on what instructions are executed: 32-bit instructions or

MIPS16 instructions. For details, refer to V

4181 has no Program Status Word (PSW) register as such; this is covered by the Status and Cause

The VR

R4100 Series Architecture User’s Manual.

registers incorporated within the CP0 (see 1.4.4 CP0 registers).

Figure 1-3 shows the CPU registers.

General-purpose registers

r0 = 0

r1
r2

r29
r30

r31 = LinkAddress

Figure 1-3. CPU Registers

0313263

Multiply/divide registers

HI

31

32

LO

Program Counter

31633263

PC

0313263

0

0

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CHAPTER 1 INTRODUCTION

1.4.2 CPU instruction set overview

There are two types of CPU instructions: 32-bit length instructions (MIPS III) and 16-bit length instructions

(MIPS16). Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset.

For details about instruction formats and their fields in each instruction set and operation of each instruction, refer

to VR4100 Series Architecture User’s Manual.

(1) MIPS III instructions

All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three
instruction formats as shown in Figure 1-4: immediate (I type), jump (J type), and register (R type).

Figure 1-4. CPU Instruction Formats (32-Bit Length Instruction)

31 26 25 21 20 16 15 0

op rs rt immediateI - type (Immediate)

31 26 25 0

op targetJ - type (Jump)

31 26 25 21 20 16 15 0

op rs rt saR - type (Register)

11 10 6 5

rd funct

The instruction set can be further divided into the following five groupings:

(a) Load and store instructions move data between the memory and the general-purpose registers. They are all

immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit,
signed immediate offset.

(b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in

registers. They include R-type (in which both the operands and the result are stored in registers) and I-type
(in which one operand is a 16-bit signed immediate value) formats.

(c) Jump and branch instructions change the control flow of a program. Jumps are made either to an absolute

address formed by combining a 26-bit target address with the higher bits of the program counter (J-type
format) or register-specified address (R-type format). The format of the branch instructions is I type.
Branches have 16-bit offsets relative to the program counter. JAL instructions save their return address in
register 31.

(d) System control coprocessor (CP0) instructions perform operations on CP0 registers to control the memory-

management and exception-handling facilities of the processor.

(e) Special instructions perform system calls and breakpoint exceptions, or cause a branch to the general

exception-handling vector based upon the result of a comparison. These instructions occur in both R-type
and I-type formats.

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CHAPTER 1 INTRODUCTION

(2) MIPS16 instructions

All the CPU instructions except for JAL and JALX are 16-bit length when executing MIPS16 instructions, and
they are classified into thirteen instruction formats as shown in Figure 1-5.

Figure 1-5. CPU Instruction Formats (16-Bit Length Instruction)

I-type

RI-type

RR-type

RRI-type

RRR-type

RRI-A-type

Shift-type

I8-type

15

op

10 8 7

op immediate

op funct

RRI immediate

RRR F

RRI-A F

SHIFT F

I8 immediate

rx

10 8 7

rx

10 8 7

rx

10 8 7

rx

10 8 7

rx

10 8 7

rx

10 8 7

funct

immediate

54

ry

54

ry

54

ry

5 4

ry immediate

54

ry Shamt

21

rz

3

21

01011

01115

01115

01115

01115

01115

01115

01115

I8_MOVR32-type

I8_MOV32R-type

I64-type

RI64-type

Immediate(15:0)

10 8 7

I8 r32(4:0)

15 10 8 7 3 2

I8 r32(2:0)funct rz

I64 immediate

I64 immediate

JAL/JALX-type

16 15

JAL

funct

10 8 7

funct

10 8 7

funct

11 10 9 5 4

X

Immediate(20:16)

54

ry

54

r32(4:3)

54

ry

Immediate(25:21)

01115

011

01115

01115

031

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CHAPTER 1 INTRODUCTION

The instruction set can be further divided into the following four groupings:

(a) Load and store instructions move data between memory and general-purpose registers. They include RRI,

RI, I8, and RI64 types.

(b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in

registers. They include RI, RRIA, I8, RI64, I64, RR, RRR, I8_MOVR32, and I8_MOV32R types.

(c) Jump and branch instructions change the control flow of a program. They include JAL/JALX, RR, RI, I8, and I

types.

(d) Special instructions are BREAK and Extend instructions. The BREAK instruction transfers control to an

exception handler. The Extend instruction extends the immediate field of the next instruction. They are RR
and I types. When extending the immediate field of the next instruction by using the Extend instruction, one
cycle is needed for executing the Extend instruction, and another cycle is needed for executing the next
instruction.

1.4.3 Data formats and addressing

The VR4181 uses the following four data formats:

• Doubleword (64 bits)

• Word (32 bits)

• Halfword (16 bits)

• Byte (8 bits)

If the data format is any one of halfword, word, or doubleword, the byte ordering can be set as either big endian or

little endian. However, the VR4181 only support the little-endian order.

Endianness refers to the location of byte 0 within the multi-byte data structure. Figure 1-6 show the configuration.
When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is

compatible with PentiumTM and DEC VAXTM conventions.

In this manual, bit designations are always little endian.

40

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CHAPTER 1 INTRODUCTION

Figure 1-6. Byte Address in Little-Endian Byte Order

(a) Word data

31 24 23 16 15 8 7 0

High-order

address

Low-order

address

15

11

14

10

7

3

6

2

13

9

5

1

(b) Doubleword data

Word Halfword Byte

63 032 31 16 15 8 7

High-order

address

Low-order

address

23

15

22

21

20

19

18

14

13

12

11

10

7

6

5

4

3

Remarks 1. The lowest byte is the lowest address.

2. The address of word data is specified by the lowest byte’s address.

Word

address

12

8

4

0

17

16

9

8

2

1

0

12

8

4

0

Doubleword

address

16

8

0

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CHAPTER 1 INTRODUCTION

The CPU core uses the following byte boundaries for halfword, word, and doubleword accesses:

• Halfword: An even byte boundary (0, 2, 4...)

• Word: A byte boundary divisible by four (0, 4, 8...)

• Doubleword: A byte boundary divisible by eight (0, 8, 16...)

The following special instructions are used to load and store data that are not aligned on 4-byte (word) or 8-byte

(doubleword) boundaries:

• Word access: LWL, LWR, SWL, SWR

• Doubleword access: LDL, LDR, SDL, SDR

These instructions are used in pairs of L and R.
Accessing unaligned data requires one additional instruction cycle (1 PCycle) over that required for accessing

aligned data.

Figure 1-7 shows the access of an unaligned word that has byte address 3.

Figure 1-7. Unaligned Word Accessing (Little Endian)

High-order address

Low-order address

31 24 23 16 15 8 7 0

654

3

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CHAPTER 1 INTRODUCTION

1.4.4 CP0 registers

The CP0 has thirty-two registers, each of which has its own register number.
Table 1-6 shows simple descriptions of each register. For the detailed descriptions of the registers, refer to

CHAPTER 3 CP0 REGISTERS.

Table 1-6. System Control Coprocessor (CP0) Register Definitions

Number Register Usage Description
0 Index M em ory management Programmable pointer to TLB array
1 Random Memory management Pseudo-random pointer to TLB array (read only)
2 EntryLo0 Memory management Lower half of TLB entry for even VPN
3 EntryLo1 Memory management Lower half of TLB entry for odd VPN
4 Context Exception processi ng Pointer to kernel virtual PTE in 32-bit mode
5 PageMask Memory management Page size s pecification
6 Wired Memory management Number of wired TLB entri es
7 −−Reserved for future use
8 BadVAddr Exception processi ng Virtual address where the most recent error occurred
9 Count Exception processing Timer count
10 EntryHi Memory management Higher half of TLB entry (includi ng ASID)
11 Compare Exc eption processing Timer compare value
12 Status Exception processi ng Status indic ation
13 Caus e Exception processing Cause of last exception
14 EPC Exception processi ng Exception P rogram Count er
15 PRI d Memory management Processor revi sion identifier
16 Confi g Memory management Configuration (memory system modes) specification

Note1

17
18 WatchLo Exception processing Memory reference t rap address low bits
19 WatchHi Exception processing Memory reference trap address high bits
20 XCont ext Exception processing Pointer to kernel virtual P T E i n 64-bi t mode
21 to 25 −−Reserved for future use
26
27
28 TagLo Memory management Lower half of cache tag
29 TagHi Memory management Higher half of cache tag
30 ErrorEPC Exception processi ng Error Excepti on P rogram Counter
31 −−Reserved for future use

LLAddr

Parity Error
Cache Error

Note2

Note2

Memory management Physic al address for self diagnostics

Exception processi ng Cache parity bits
Exception processi ng Index and status of cache error

Notes1. This register is defined to maintain compatibility with the VR

meaningless during normal operations.

4100TM. This register is not used in the VR4181

2. This register is defined to maintain compatibility with the V

R

hardware.

User’s Manual U14272EJ3V0UM

4000TM and VR4400TM. This register is

43

CHAPTER 1 INTRODUCTION

1.4.5 Floating-point unit (FPU)

4181 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU

The VR

instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler.

1.4.6 Memory management unit

The VR4181 has a 32-bit physical addressing range of 4 GB. However, since it is rare for systems to implement a
physical memory space as large as that memory space, the CPU provides a logical expansion of memory space by
translating addresses composed in the large virtual address space into available physical memory addresses.

The VR4181 has three operating modes: User, Supervisor, and Kernel. The manner in which memory addresses
are mapped depends on these operating modes.

In addition, the VR4181 supports the 32-bit and 64-bit addressing modes. The manner in which memory
addresses are translated or mapped depends on these addressing modes.

A detailed description of the physical address space is given in CHAPTER 4 MEMORY MANAGEMENT

SYSTEM. For details about the virtual address space, refer to V

R4100 Series Architecture User’s Manual.

(1) Translation lookaside buffer (TLB)

Virtual memory mapping is performed using the translation lookaside buffer (TLB). The TLB translates virtual
addresses to physical addresses. It runs by a full-associative method and has 32 entries, each of which two
successive pages are mapped.
The TLB of the VR

4181 holds both instruction addresses and data addresses so that it is called as joint TLB
(JTLB).
The page size can be configured, on a per-entry basis, to map a page size of 1 KB to 256 KB, in power of four. A
CP0 register stores the size of the page to be mapped, and that size is entered into the TLB when a new entry is
written. Thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be
memory-mapped using only one TLB entry.
Translating a virtual address to a physical address begins by comparing the virtual address from the processor
with the physical addresses in the TLB. There is a match when the virtual page number (VPN) of the address is
the same as the VPN field of an entry, and either the Global (G) bit of the TLB entry is set, or the ASID field of the
virtual address is the same as the ASID field of the TLB entry.
This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and
software is allowed to refill the TLB from a page table of virtual/physical addresses in memory.

1.4.7 Cache

The VR4181 chip incorporates instruction and data caches, which are independent of each other. This
configuration enables high-performance pipeline operations. Both caches have a 64-bit data bus, enabling a one­clock access. These buses can be accessed in parallel. The instruction cache of the VR4181 has a storage capacity
of 4 KB, while the data cache has a capacity of 4 KB.

For details about caches, refer to V

R4100 Series Architecture User’s Manual.

1.4.8 Instruction pipeline

4181 has a 5-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle.

The VR
For details, refer to V

44

R4100 Series Architecture User’s Manual.

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1.4.9 Power modes

4181 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. A

The VR

detailed description of these power modes is also given in CHAPTER 10 POWER MANAGEMENT UNIT (PMU).

(1) Fullspeed mode

This is the normal operation mode.
The VR4181’s default status sets operation under Fullspeed mode. After a reset, the VR4181 returns to Fullspeed
mode.

(2) Standby mode

When a STANDBY instruction has been executed, the processor can be set to Standby mode. During Standby
mode, the pipeline clock (PClock) in the CPU core is held at high level. The peripheral units all operate as they
do during Fullspeed mode. This means that DMA operations are enabled during Standby mode.
During Standby mode, the processor returns to Fullspeed mode if any interrupt request occurs.

(3) Suspend mode

When the SUSPEND instruction has been executed, the processor can be set to Suspend mode. During
Suspend mode, the pipeline clock (PClock) in the CPU core is held at high level. The VR4181 also stops
supplying TClock and PCLK to peripheral units. While in this mode, the register and cache contents are retained.
Contents of DRAM can also be retained by putting DRAM into self-refresh mode.
During Suspend mode, the processor returns to Fullspeed mode if any of power-on factors or some of interrupt
requests occurs.

(4) Hibernate mode

When the HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During
Hibernate mode, clocks other than the RTC clock (32.768 kHz) are held at high level and the PLL stops. While in
this mode, contents of the registers and caches are not retained. Contents of DRAM can be retained by putting
DRAM into self-refresh mode.
Power consumption during Hibernate mode is about 0 W if power to 2.5 V power supply is not applied (it does
not go completely to 0 W due to the existence of a 32.768 kHz oscillator or on-chip peripheral circuits that
operate at 32.768 kHz).
During Hibernate mode, the processor returns to Fullspeed mode if any of power-on factors or some of interrupt
requests occurs.

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CHAPTER 1 INTRODUCTION

1.4.10 Code compatibility

R4110 core is designed in consideration of the program compatibility to other VR-Series processors.

The V
However since it has some differences from other processors on their architecture, it cannot necessarily execute all
programs that can be executed in other VR-Series processors, and also other VR-Series processors cannot
necessarily execute all programs that can be executed in the VR4110 core.

Matters that should be paid attention to when porting programs between the VR4110 core and other VR-Series
processors are listed below.

• A 16-bit length MIPS16 instruction set is added in the VR4110 core.

• Multiply-add instructions (MADD16, DMADD16) are added in the VR4110 core.

• Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the VR4110 core to support

power modes.

• The VR4110 core does not support floating-point instructions since it has no Floating-Point Unit (FPU).

• The VR4110 core does not have the LL bit to perform synchronization of multiprocessing. Therefore, it does not

support instructions that manipulate the LL bit (LL, LLD, SC, SCD).

• The CP0 hazards of the VR4110 core are equally or less stringent than those of the VR4000.

For more information about each instruction, refer to V
manuals of each product other than the V

R4100 Series.

R4100 Series Architecture User’s Manual, and user’s

Instructions supported by each of the VR Series processors are listed below.

Table 1-7. List of Instructions Supported by V

Products

VR4181

4111

VR
Supported instructions
MIPS I AAAAAA
MIPS II AAAAAA
MIPS III AAAAAA

LL bit

N/AN/AAAAA

manipulation
MIPS IV N/A N/A N/A A A A
MIPS16 A A N/A N/A N/A N/A
Multiply-add A

(16 bits)
Floating-point operation N/A N/A AAAA
Power mode transition A A N/A A A N/A

V

4121

R

4122

VR

A

(32 bits)

VR4300

TM

VR4305
VR4310

N/A N/A A

Series Processors

R

TM

VR5000A

TM

TM

TM

VR5432

TM

VR10000
VR12000

TM

TM

N/A

(32 bits)

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1.5 Clock Interface

The VR4181 has the following eight clocks.

• CLKX1, CLKX2 (input)
These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core, serial
interface, and other peripheral units.

• RTCX1, RTCX2 (input)
These are oscillation inputs of 32.768 kHz, and used for PMU, RTC, and so on.

• PClock (internal)
This clock is used to control the pipeline in the VR4110 core, and for units relating to the pipeline. This clock is
generated from the clock input of CLKX1 and CLKX2 pins via the PLL. Its frequency is determined by
CLKSEL(2:0) pins.

• MasterOut (internal)
This is a bus clock of the VR4110 core, and used for interrupt control. This clock operates in frequency of 1/4 of
the TClock frequency. The contents of the CP0’s Count register are incremented synchronously with this clock.

• TClock (internal)
This is an operation clock for internal MBA bus and is supplied to the internal MBA modules (memory controller,
LCD controller, and DMA controller). This clock is generated from PClock and its frequency is 1/1, 1/2, or 1/3 of
the PClock frequency (it is determined by internal register setting). It is set to 1/2 by default.

• PCLK (internal)
This clock is supplied to the internal ISA peripherals. This clock is generated from TClock and its frequency is
determined by internal register setting. PCLK will operate only when accesses to the internal ISA bus occur.

• SYSCLK (internal, output)
This clock is used as the external ISA bus clock. It is also supplied to the internal CompactFlash controller. This
clock is generated from PCLK and its frequency is determined by internal register setting. SYSCLK will operate
only when accesses to the external ISA bus occur.

• SDCLK (output)
This clock is supplied to SDRAM. This clock operates in the same frequency as that of TClock. SDCLK will
operate only when accesses to SDRAM occur.

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CHAPTER 1 INTRODUCTION

Figure 1-8 shows the external circuits of the clock oscillator.

Figure 1-8. External Circuits of Clock Oscillator

(a) Crystal oscillation (b) External clock

VR4181

GND_OSC

Note 1

Note 2

External
clock

Open

VR4181

Note 1

Note 2

Notes 1. CLKX1, RTCX1

2. CLKX2, RTCX2

Cautions1. When using the clock oscillator, wire as follows in the area enclosed by the broken line in

the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a

signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as GND.

Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. Ensure that no load such as wiring capacity is applied to the CLKX2 or RTCX2 pin when
inputting an external clock.

Figure 1-9 shows examples of the incorrect connection circuit of the resonator.

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User’s Manual U14272EJ3V0UM

CHAPTER 1 INTRODUCTION

Figure 1-9. Incorrect Connection Circuits of Resonator

(a) Connection circuit wiring is too long.

Note 1

(c) A high fluctuating current flows near a signal line.

Note 1

Note 2

Note 3 Note 3

Note 3

Note 2

(b) There is another signal line crossing.

Note 1

(d) A current flows over the ground line of the
oscillator
(The potentials of points A, B, and C change).

DD

V

Note 2

Large
current

(e) A signal is fetched.

Note 2

Note 1

Note 3

Note 3

Note 1

ABC

Note 2

Notes 1. CLKX2, RTCX2

2. CLKX1, RTCX1

3. GND_OSC

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49

2.1 Pin Configuration

• 160-pin plastic LQFP (fine pitch) (24 × 24)

FPD0

FPD1

FPD2

FPD3

GPIO12/FPD4

GPIO13/FPD5

GPIO14/FPD6/CD1#

GPIO15/FPD7/CD2#

UBE#/GPIO20/M

IOWR#/GPIO17

160

159

158

157

156

155

154

153

152

GND_AD
GND_TP

TPX0
TPX1
TPY0
TPY1

VDD_TP

ADIN0
ADIN1

ADIN2
AUDIOIN
VDD_AD

AUDIOOUT

IORDY/GPIO18

IOCS16#/GPIO19

RESET#/GPIO21

ROMCS3#
ROMCS2#/GPIO24
ROMCS1#/GPIO23
ROMCS0#/GPIO22

SYSEN#

SYSDIR

MEMWR#

MEMRD#
GND_LOGIC
VDD_LOGIC

LDQM/LCAS#

UDQM/UCAS#

SDRAS#

CAS#

RAS0#/SDCS0#

GND_IO

VDD_IO

RAS1#/SDCS1#

CLKEN

DATA0
DATA1
DATA2
DATA3
DATA4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

414243444546474849505152535455565758596061626364656667686970717273747576777879

151

CHAPTER 2 PIN FUNCTIONS

IORD#/GPIO16

FLM/MIPS16EN

VDD_LOGIC

GND_LOGIC

LOCLK/MEMCS16#

SHCLK/LCDCS#

VPBIAS/VPGPIO0

VPLCD/VPGPIO1

VDD_IO

GND_IO

GPIO0/SI

GPIO1/SO

GPIO2/SCK

GPIO3/PCS0#

GPIO4

GPIO5/DCD2#

GND_LOGIC

GPIO6/RTS2#

GPIO7/DTR2#

GPIO8/DSR2#

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

GPIO9/CTS2#

GPIO10/FRM/SYSCLK

GPIO11/PCS1#

IRDOUT/TxD2

IRDIN/RxD2

RxD1/GPIO25

TxD1/GPIO26/CLKSEL0

130

129

128

127

126

125

124

RTS1#/GPIO27/CLKSEL1

CTS1#/GPIO28

DCD1#/GPIO29

123

122

121

80

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

DTR1#/GPIO30/CLKSEL2
DSR1#/GPIO31
POWER
RSTSW#
RTCRST#
POWERON
MPOWER
BATTINH/BATTINT#
VDD_LOGIC
GND_LOGIC
CF_AEN#/SCANIN0
CF_DIR/SCANIN1
CF_DEN#/SCANIN2
CF_VCCEN#/SCANIN3
CF_IOIS16#/SCANIN4
CF_WAIT#/SCANIN5
CF_RESET/SCANIN6
CF_REG#/SCANIN7
VDD_IO
GND_IO
CF_BUSY#/SCANOUT0
CF_CE1#/SCANOUT1
CF_CE2#/SCANOUT2
CF_STSCHG#/SCANOUT3
CF_IOR#/SCANOUT4
CF_IOW#/SCANOUT5
CF_OE#/SCANOUT6
CF_WE#/SCANOUT7
LEDOUT
GND_IO
GND_IO
VDD_PLL
GND_PLL
VDD_OSC
CLKX1
CLKX2
RTCX2
RTCX1
GND_OSC
GND_IO

DATA5

Remark # indicates active low.

50

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

ADD0

ADD1

ADD2

ADD3

DATA14

DATA15

VDD_IO

GND_IO

SDCLK

ADD4

User’s Manual U14272EJ3V0UM

ADD5

VDD_LOGIC

GND_LOGIC

ADD6

ADD7

ADD8

ADD9

ADD10

ADD11

GND_IO

ADD12

VDD_IO

ADD13

ADD14

ADD15

ADD16

ADD17

ADD18

ADD19

ADD20

ADD21

Pin Identification

CHAPTER 2 PIN FUNCTIONS

ADD(21:0) : Address Bus
ADIN(2:0) : Analog Data Input
AUDIOIN : Audio Input
AUDIOOUT : Audio Output
BATTINH : Battery Inhibit
BATTINT# : Battery Interrupt
CAS# : Column Address Strobe
CD1#, CD2# : Card Detect for CompactFlash
CF_AEN# : Address Enable for CompactFlash Buffer
CF_BUSY# : Ready/Busy/Interrupt Request for CompactFlash
CF_CE(2:1)# : Card Enable for CompactFlash
CF_DEN# : Data Enable for CompactFlash Buffer
CF_DIR : Data Direction for CompactFlash Buffer
CF_IOIS16# : I/O is 16 bits for CompactFlash
CF_IOR# : I/O Read Strobe for CompactFlas h
CF_IOW# : I/O Write Strobe for CompactFlash
CF_OE# : Output Enable for CompactFlash
CF_REG# : Register Memory Access for CompactFlash
CF_RESET : Reset f or CompactFlash
CF_STSCHG# : Status Change of CompactFlash
CF_VCCEN# : V
CF_WAIT# : Wait Input for CompactFlash
CF_WE# : Write Enable for CompactFlash
CLKEN : Clock Enable for SDRAM
CLKSEL(2:0) : Clock Select
CLKX1, CLKX2 : Clock Input
CTS1#, CTS2# : Clear to Send
DATA(15:0) : Data Bus
DCD1#, DCD2# : Data Carrier Detect
DSR1#, DSR2# : Data Set Ready
DTR1#, DTR2# : Data Terminal Ready
FLM : First Line Clock f or LCD
FPD(7:0) : Screen Data of LCD
FRM : Clocked Serial Frame
GND_AD : Ground for A/D and D/A Converter
GND_IO : Ground for I/O
GND_LOGIC : Ground for Logic
GND_OSC : Ground for Oscillator
GND_PLL : Ground for PLL
GND_TP : Ground for Touch Panel
GPIO(31:0) : General Purpose I/ O
IOCS16# : I/O 16-bit Bus Siz ing
IORD# : I/O Read
IORDY : I/O Ready
IOWR# : I/O Write
IRDIN : IrDA Data Input
IRDOUT : IrDA Data Output
LCAS# : Lower Column Address Strobe
LCDCS# : Chip Select f o r L CD

CC

Enable for CompactFlash

LDQM : Lower Byte Enable for SDRAM
LEDOUT : LED Output
LOCLK : Load Clock for LCD
M : LCD Modulation Clock
MEMCS16# : Memory 16-bit Bus Sizing
MEMRD# : Memory Read
MEMWR# : Memory Write
MIPS16EN : MIPS16 Enable
MPOWER : Main Power
PCS(1:0)# : Programmable Chip Select
POWER : Power Switch
POWERON : P o wer On State
RAS(1:0)# : Row Address Strobe for DRAM
RESET# : Reset Output
ROMCS(3:0)# : Chip Select f or ROM
RSTSW# : Reset Switch
RTCRST# : Real-t i me Cl o ck Reset
RTCX1, RTCX2 : Real-time Clock Input
RTS1#, RTS2# : Request to Send
RxD1, RxD2 : Re ceive Data
SCANIN(7:0) : Scan Data Input
SCANOUT(7:0) : Scan Data Output
SCK : CSI (Clocked Serial Interface) Clock
SDCLK : Operation Clock for SDRAM
SDCS(1:0)# : Chip Select for SDRAM
SDRAS# : Row Address Strobe for SDRAM
SHCLK : Shift Clock for LCD
SI : Clocked Serial Data Input
SO : Clocked Serial Data Output
SYSCLK : Sy s tem Clock for System Bus
SYSDIR : System Data Direction
SYSEN# : Sy s tem Data Enable
TPX(1:0) : Touch Panel Data of X
TPY(1:0) : Touch Panel Data of Y
TxD1, TxD2 : Transmit Data
UBE# : Upper Byte Enable for System Bus
UCAS# : Upper Column Address Strobe for DRAM
UDQM : Upper Byte Enable for SDRAM
VDD_AD : Power Supply for A/D and D/A Converter
VDD_IO : Power Supply for I/O
VDD_LOGIC : Power Supply for Logic
VDD_OSC : Power Supply for Oscillator
VDD_PLL : Power Supply for PLL
VDD_TP : Power Supply f or Touch Panel
VPBIAS : Bias Power Control for LCD
VPGPIO(1:0) : General Purpose Output for LCD Panel Power

Control

VPLCD : Logic Power Control for LCD

Remark # indicates active low.

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CHAPTER 2 PIN FUNCTIONS

2.2 Pin Function Description

Remark # indicates active low.

2.2.1 System bus interface signals

Signal name I/O Description of funct i on

ADD(21:0)

DATA(15:0) I/O Data bus.

IORD#/GPIO16 I/O System bus I/O read signal output or general-purpose I/O.

IOWR#/GPIO17 I/O System bus I/O write signal output or general -purpose I/O.

IORDY/GPIO18 I/O System bus I/O channel ready i nput or general -purpose I/O.

IOCS16#/GPIO19 I/O Bus sizing request input for system bus I/O or general-purpose I/O.

UBE#/GPIO20/M I/O System bus upper by te enable output, general-purpose input, or LCD modul ation

RESET#/GPIO21 I/O System bus reset out put or general-purpose I/O.

Note

Output Address bus.

Used to specify addres s for the DRAM, ROM, flas h memory, or system bus (ISA).

Used to transmit and receive data between the V
memory, or system bus.

It is active when t he V
when configured as IORD#.

It is active when t he V
when configured as IOWR#.

Set this signal as active when system bus controller is ready to be accessed by the
V

4181 when configured as IORDY.

R

Set this signal as active when system bus I/O accesses data in 16-bit width, if
configured as IOCS16#.

output.
During system bus accesses, this signal is active when the high-order byte is valid on
the data bus.

It is active when t he V
RESET#.

4181 and DRAM, ROM, flash

R

4181 accesses the system bus to read data from an I/O port

R

4181 accesses the system bus to write data to an I/O port

R

4181 resets the system bus controller when configured as

R

(1/2)

Note The VR

4181 utilizes different addressings depending on the types of the external accesses.
During ROM accesses, bits 22 to 1 of the internal address lines are output to the ADD(21:0) pins (the
minimum transfer data width is a half word (1 word = 32 bits)).
During accesses other than ROM accesses, bits 21 to 0 of the internal address lines are output to the
ADD(21:0) pins (the minimum transfer data width is 1 byte).

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User’s Manual U14272EJ3V0UM

CHAPTER 2 PIN FUNCTIONS

Signal name I/O Description of funct i on

SYSDIR

SYSEN#

SDCS(1:0)#/RAS(1:0)# Output SDRAM chip select for bank 0 and bank 1 or EDO DRAM row address strobes.
CAS# Output SDRAM c ol um n address strobe. Leave unconnect ed when using EDO DRAM.
SDRAS# Output SDRAM row address s trobe. Leave unconnected when using EDO DRA M .
UDQM/UCAS# Output S DRA M upper byte enable or EDO DRAM upper byte col um n address strobe.
LDQM/LCAS# Output SDRAM lower byte enable or EDO DRAM lower byte column address strobe.
SDCLK Output SDRAM operating clock.
CLKEN Output SDRA M clock enable output (CKE).
ROMCS3# Output ROM chip select output for bank 3.
ROMCS2#/GPIO24 I/O ROM chip select out put for bank 2, or general-purpose I/O.
ROMCS1#/GPIO23 I/O ROM chip select out put for bank 1, or general-purpose I/O.
ROMCS0#/GPIO22 I/O ROM chip select out put for bank 0, or general-purpose I/O.
MEMRD# Output Memory read signal f or ROM and system bus.
MEMWR# Output M em ory write signal for ROM, DRAM and system bus.

Note

Note

Output Data bus isolati on buffer direction control. This signal is valid only when ROM , ISA,

or CompactFlash acces ses are enabled.
This becomes low level during ROM , ISA, or CompactFlas h read cycle, or becomes
high level during ROM, ISA, or CompactFlash write cycle.

Output Data bus isolati on buffer enable. This signal is valid only when ROM, ISA, or

CompactFlash acces ses are enabled.
This becomes active during ROM or ISA cycle.

(2/2)

Note The SYSEN# and SYSDIR signals control a buffer which is used to isolate SDRAM data bus from the bus of

other low speed devices. By isolating the high-speed data bus of SDRAM, the load of the data bus between

4181 and SDRAM is reduced.

the VR

When the EXBUFFEN bit of the XISACTL register is cleared to 0, the SYSEN# and SYSDIR signals start their

operation. These signals keep low level until EXBUFFEN bit is cleared to 0 after a reset.

When an isolation buffer is used, SYSEN# and SYSDIR signals function as follows;

SYSEN# SYSDIR Bus operation

0 0 External ISA, Compact F l ash, or ROM read cycle
0 1 External ISA, CompactFlash, or flash memory mode write cycle
1Don’t care External Buffer Disable

DRAM read/write cycle or Hibernate mode

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CHAPTER 2 PIN FUNCTIONS

2.2.2 LCD interface signals

Signal name I/O Description of funct i on
SHCLK/LCDCS# Output LCD shift clock output or chip select for external LCD controller.
LOCLK/MEMCS16# I/O LCD load clock output or bus sizing request input for system bus memory access.

When using as MEMCS16#, the ex ternal agent must activat e this signal at the
system bus memory access in 16-bit width.

FLM/MIPS16EN I/O The function of this pin differs dependi ng on the operating status.

<During RTC reset (input)>
This signal enables use of M I PS16 instructions.

0: Disable use of MIPS 16 i nstructions
1: Enable use of MIPS16 instructions

<During normal operation (output)>

LCD first line clock output.
FPD(7:4)/GPIO(15:12)
FPD(3:0)

Note

VPLCD/VPGPIO1 Output LCD logic power control. This signal may be defined as a general-purpose out put

VPBIAS/VPGPIO0 Output LCD bias power control. This signal may be defined as a general-purpose output

Note

See

Output

2.2.11 General-purpose I/O signals

Output LCD screen data.

when an external LCD controller is used.

when an external LCD controller is used.

in this section.

Note Connection between FPD(7:0) of the VR

width as below.
For details, refer to CHAPTER 21 LCD CONTROLLER.

VR4181 LCD Panel Data (4-bit width) LCD Panel Data (8-bit wi dth)
FPD0 Data Line 0 Data Line 4
FPD1 Data Line 1 Data Line 5
FPD2 Data Line 2 Data Line 6
FPD3 Data Line 3 Data Line 7
FPD4 − Data Line 0
FPD5 − Data Line 1
FPD6 − Data Line 2
FPD7 − Data Line 3

4181 and LCD panel data lines differs depending on the panel data

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User’s Manual U14272EJ3V0UM

CHAPTER 2 PIN FUNCTIONS

2.2.3 Initialization interface signals

Signal name I/O Description of funct i on
POWER Input VR4181 activation signal.
RSTSW# Input VR4181 reset signal.
RTCRST# Input Reset signal for i nt e rnal Real -t i me clock and internal logic. When power is first

supplied to the system, the external agent must activate this signal.

POWERON Output This signal indicates that the VR4181 is ready to operate. It bec omes active when a

power-on factor is detected and bec om es inactive when the BATTINH/BATTINT#
signal check has been com pl eted.

MPOWER Output This signal indic ates that the VR4181 is operating. This signal i s inactive during

Hibernate mode. During this signal being inactive, turn off t he 2.5 V power supply.

2.2.4 Battery monitor interface signals

Signal name I/O Description of funct i on
BATTINH/BATTINT# Input The func t i on of this pin differs depending on the s t ate of the MPOWER pin.

<When MPOWER = 0>
BATTINH signal
Enables or disables acti vation on power application.

1: Enable activation
0: Disable activati on

<When MPOWER = 1>
BATTINT# signal
This is an interrupt signal t hat is input when remaining battery power i s low during
normal operations. The external agent checks the remaining battery power and
activates this signal if voltage suff i cient for operations cannot be suppl i ed.

2.2.5 Clock interface signals

Signal name I/O Description of funct i on
RTCX(2:1) − Connections to 32.768 kHz crystal resonator.
CLKX(2:1) − Connections to 18.432 MHz cryst al resonator.

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CHAPTER 2 PIN FUNCTIONS

2.2.6 Touch panel interface and audio interface signals

Signal name I/O Description of funct i on

TPX(1:0) I/O Touch panel X coordinate data. They use the voltage applied t o t he X coordinate

and the voltage input to the Y coordinate to detect which coordi nates on the touch
panel are being pressed.

TPY(1:0) I/O Touch panel Y coordinate data. They use the voltage applied t o t he Y coordinate

and the voltage input to the X coordinate to detect which coordi nates on the touch

panel are being pressed.
ADIN(2:0) Input General-purpose A/D data inputs.
AUDIOIN Input Audio input.
AUDIOOUT Output Audio output.

2.2.7 LED interface signals

Signal name I/O Description of funct i on

LEDOUT Output This is an output signal for lighti ng LE Ds.

2.2.8 CompactFlash interface and keyboard interface signals

Signal name I/O Description of funct i on
CF_WE#/SCANOUT7 Output CompactFlash write enable output or keyboard scan data output.
CF_OE#/SCANOUT6 Output CompactFlash output enable or keyboard scan data output.
CF_IOW#/SCANOUT5 Output CompactFlash I/O wri t e strobe output or keyboard scan data output.
CF_IOR#/SCANOUT4 Output CompactFlash I/O read strobe output or keyboard scan data output .
CF_STSCHG#/SCANOUT3 I/O CompactFlas h status changed input or keyboard s can data output.
CF_CE(2:1)#/

SCANOUT(2:1)
CF_BUSY#/SCANOUT0 I/ O CompactFlash ready/busy/i nt errupt request indication input or k eyboard scan data

CF_REG#/SCANIN7 I/O CompactFlash register select output or keyboard scan data input .
CF_RESET/SCANIN6 I/O Compact F lash reset output or keyboard scan data input .
CF_WAIT#/SCANIN5 Input Compact F l ash wait input or keyboard scan dat a i nput.
CF_IOIS16#/SCANIN4 Input CompactF l ash I/O 16-bit bus input or keyboard scan data input.
CF_VCCEN#/SCANIN3 I/O CompactFlash VCC enable output or keyboard scan data i nput.
CF_DEN#/SCANIN2 I/O CompactFlash data buffer enabl e output or keyboard scan data input.
CF_DIR/SCANIN1 I/O Compac tFlash data direction cont rol out put or keyboard scan data input.
CF_AEN#/SCANIN0 I/O CompactF l ash address buffer enable output or keyboard scan data input.

Output CompactFlash c ard enabl e outputs or keyboard scan data out put s.

output.

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CHAPTER 2 PIN FUNCTIONS

2.2.9 Serial interface channel 1 signals

Signal name I/O Description of funct i on
RxD1/GPIO25 I/O Serial channel 1 receive data i nput or general-purpose I/O.
TxD1/GPIO26/CLKSEL0 I / O The function of this pin differs depending on the operating st atus.

<During RTC reset (input)>
This signal is used to set CPU core operation clock frequency

<During normal operation (input/output)>
Serial channel 1 transmit data output or general-purpose I/O.

RTS1#/GPIO27/CLKSEL1 I/O The function of this pin differs depending on the operating status.

<During RTC reset (input)>
This signal is used to set CPU core operation clock frequency

<During normal operation (input/output)>

Serial channel 1 request to send output or general-purpose I/O.
CTS1#/GPIO28 I/O Serial channel 1 clear to send input or general-purpose I/O.
DCD1#/GPIO29 I/O Serial channel 1 dat a carrier detect input or general-purpose I/O.
DTR1#/GPIO30/CLKSEL2 I/O The function of this pin differs depending on the operating status.

<During RTC reset (input)>

This signal is used to set CPU core operation clock frequency

<During normal operation (input/output)>

Serial channel 1 data terminal ready output or general-purpose I/O.
DSR1#/GPIO31 I/ O Serial channel 1 Data set ready input or general-purpose I/O.

Note

Note

Note

.

.

.

Note CLKSEL(2:0) signals are used to set the frequency of the CPU core operation clock (PClock). These signals

are sampled when the RTCRST# signal goes high.
The relationship between the CLKSEL(2:0) pin settings and clock frequency is shown below.

CLKSEL(2:0) CPU core operation frequency (PClock)

111 Reserved (98.1 MHz)
110 Reserved (90.6 MHz)
101 Reserved (84.1 MHz)
100 Reserved (78.5 MHz)
011 Reserved (69.3 MHz)
010 65.4 MHz
001 62.0 MHz
000 49.1 MHz

TClock is generated from PClock and its frequency is always 1/2 of the PClock frequency after RTC reset.

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CHAPTER 2 PIN FUNCTIONS

2.2.10 IrDA interface signals

Signal name I/O Description of funct i on

IRDIN/RxD2 Input IrDA receive data input or serial channel 2 receive data input.

Connect this pin to GND (digit al ) via resistor when an IrDA receive component is
connected.

IRDOUT/TxD2 Output IrDA transm i t data output or serial channel 2 transm i t data output.

2.2.11 General-purpose I/O signals

Signal name I/O Description of funct i on

See

GPIO(31:25) I/O
GPIO(24:16) I/O
GPIO15/FPD7/CD2# I/O General-purpose I/O, LCD screen data output, or CompactFl ash card detect 2 input.
GPIO14/FPD6/CD1# I/O General-purpose I/O, LCD screen data output, or CompactFl ash card detect 1 input.
GPIO13/FPD5 I/O General-purpose I/O or LCD screen data output.
GPIO12/FPD4 I/O General-purpose I/O or LCD screen data output.
GPIO11/PCS1# I/O General-purpose I/O or programmable chip select 1.
GPIO10/FRM/SYSCLK I/O General-purpose I/O, serial frame input f or clocked serial interface, or external bus

GPIO9/CTS2# I/O General-purpose I/O or seri al channel 2 clear to send output.
GPIO8/DSR2# I/O General-purpose I/O or serial channel 2 data set ready input.
GPIO7/DTR2# I/O General-purpose I/O or serial channel 2 data term i nal ready input.
GPIO6/RTS2# I/O General-purpose I/O or seri al channel 2 request to send output.
GPIO5/DCD2# I/O General-purpose I/O or serial c hannel 2 data carrier detect input.
GPIO4 I/O General-purpose I/O.
GPIO3/PCS0# I/O General-purpose I/O or programmable chip selec t 0.
GPIO2/SCK I/O General -purpose I/O or serial clock input for clocked serial i nt erface.
GPIO1/SO I/O General-purpos e I/O or serial data output signal f or clocked serial interfac e.
GPIO0/SI I /O General-purpose I/O or serial data input signal for clocked seri al i nterface.

2.2.9 Serial interface channel 1 signals

See

2.2.1 System bus interface signals

system clock output.

in this section

in this section.

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User’s Manual U14272EJ3V0UM

2.2.12 Dedicated VDD/GND signals

CHAPTER 2 PIN FUNCTIONS

Signal name Power

supply
VDD_PLL 2.5 V Power supply dedicated for the PLL analog block .
GND_PLL 2.5 V Ground dedicated for the PLL analog bloc k.
VDD_TP 3.3 V Power supply dedicated for the touch panel interface.
GND_TP 3. 3 V Ground dedicated for the touc h panel i nterface.
VDD_AD 3.3 V Power supply dedicated for the A/D and D/A converters. The voltage applied to t hi s

pin becomes the maximum value for the A/D and D/A interf ace signals.

GND_AD 3.3 V Ground dedicat ed for the A/D and D/A converters . The voltage applied to this pin

becomes the minimum v al ue for the A/D and D/A interface signals.
VDD_OSC 3.3 V Power supply dedic ated for the oscillator.
GND_OSC 3.3 V Ground dedicated for the oscillator.
VDD_LOGIC 2.5 V Ordinary power supply of 2.5 V
GND_LOGIC 2.5 V Ordinary ground of 2.5 V
VDD_IO 3.3 V Ordinary power supply of 3.3 V
GND_IO 3.3 V Ordinary ground of 3.3 V

Description of funct i on

Caution The VR4181 has two types of power supplies. The 3.3 V power supply should be turned on at first.

Turn on/off the 2.5 V power supply depending on the status of the MPOWER pin.

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin Status in Specific Status

(1/3)

Signal Name During RTC

Reset

After RTC Reset After Reset by

Deadman’s

During Suspend

Mode

Switch or

RSTSW

ADD(21:0) Hi-Z 0 0

Note 1

DATA(15:0) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
MEMRD# Hi-Z 1 1 1 Hi-Z
MEMWR# Hi-Z 1 1 1 1

Note2

SDCS(1:0)#/RAS(1:0)# Hi-Z 1 1
UDQM/UCAS# Hi-Z 1 1
LDQM/LCAS# Hi-Z 1 1

1/0
1/0
1/0

Note2

Note2

CAS# Hi-Z 1 1 0 0
SDRAS# Hi-Z 1 1 0 0
SDCLK Hi-Z Run 0 0 0
CLKEN Hi-Z 1 1 1 0
SYSDIR Hi-Z 0 0 0 0
SYSEN# Hi-Z 0 0 0 0

1/

IORD#/GPIO16 − Hi-Z Hi-Z
IOWR#/GPIO17 − Hi-Z Hi-Z
IORDY/GPIO18 − Hi-Z Hi-Z
IOCS16#/GPIO19 − Hi-Z Hi-Z
UBE#/GPIO20/M − Hi-Z Hi-Z
RESET#/GPIO21 − Hi-Z Hi-Z
ROMCS(2:0)#/GPIO(24:22) − Hi-Z Hi-Z

Note 1

1/

Note 1
Note 1 Note 3
Note 1 Note 3

1/

Note 1

/0 Hi-Z/

Note 1

1/

Note 1

ROMCS3# Hi-Z Hi-Z 1 1 Hi-Z
SHCLK/LCDCS# Hi-Z 0 0/1 0/1 0/Hi-Z
LOCLK/MEMCS16# Hi-Z 0 0/− 0/− 0/−
FLM/MIPS16EN

Note 4

0000
FPD(3:0) Hi-Z 0 0 0 0
VPLCD/VPGPIO1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
VPBIAS/VPGPIO0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
POWER −−−−−
RTCRST# −−−−−
RSTSW# −−−−−

During

Hibernate Mode

or Shutdown by

HALTimer

0

Note2

1/0

Note2

1/0

Note2

1/0

Hi-Z/

Note 3

Hi-Z/

Note 3

/0

Note 3

0/

Note 3

Hi-Z/

Note 3

Notes1. Maintains the state of the previous Fullspeed mode.

2. The state depends on the MEMCFG_REG register setting.

3. The state depends on the GPHIBSTH/GPHIBSTL register setting.

4. The input level is sampled to determine the MIPS16 instruction mode.

Remark 0: low level, 1: high level, Hi-Z: high impedance

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Signal Name During RTC

Reset

POWERON −−000
MPOWER 00110
BATTINH/BATTINT# −−−−−
RTCX2, RTCX1 −−−−−
CLKX2, CLKX1 −−−−−
TPX(1:0) − 11
TPY(1:0) − Hi-Z Hi-Z
ADIN(2:0) −−−−−
AUDIOIN −−−−−
AUDIOOUT − 00
CF_WE#/SCANOUT7 Hi-Z Hi-Z Hi-Z
CF_OE#/SCANOUT6 Hi-Z Hi-Z Hi-Z
CF_IOW#/SCANOUT5 Hi-Z Hi-Z Hi-Z
CF_IOR#/SCANOUT4 Hi-Z Hi-Z Hi-Z
CF_STSCHG#/SCANOUT3 Hi-Z Hi-Z Hi-Z
CF_CE(2:1)#/

SCANOUT(2:1)
CF_BUSY#/SCANOUT0 Hi-Z Hi-Z Hi-Z
CF_REG#/SCANIN7 Hi-Z −
CF_RESET/SCANIN6 Hi-Z −
CF_WAIT#/SCANIN5 −−
CF_IOIS16#/SCANIN4 −−
CF_VCCEN#/SCANIN3 Hi-Z −
CF_DEN#/SCANIN2 Hi-Z −
CF_DIR/SCANIN1 Hi-Z −
CF_AEN#/SCANIN0 Hi-Z −

Hi-Z Hi-Z Hi-Z

After RTC Reset After Reset by

Deadman’s

Switch or

RSTSW

Note 1 Note 1 Note 2/Note 1
Note 1 Note 1 Note 3/Note 1
Note 1 Note 1
Note 1 Note 1
Note 1 Note 1 Note 4/Note 1
Note 1 Note 1
Note 1 Note 1
Note 1 Note 1

During Suspend

Mode

Note 1
Note 1

Note 1
Note 1 Note 2
Note 1 Note 2
Note 1 Note 2
Note 1 Note 2
Note 1 Note 1
Note 1 Note 2

Note 1 Note 1

During

Hibernate Mode

or Shutdown by

HALTimer

1

Hi-Z

0

/Hi-Z
/Hi-Z
/Hi-Z
/Hi-Z
/Hi-Z
/Hi-Z

/Hi-Z

−

−

1/

Note 1

1/

Note 1

1/

Note 1

Notes1. Maintains the state of the previous Fullspeed mode.

2. When CF wake-up is enabled: Outputs high level.

When CF wake-up is disabled: Becomes high impedance.

3. When CF wake-up is enabled: Outputs low level.
When CF wake-up is disabled: Becomes high impedance.

4. When CF wake-up is enabled: Outputs low level.
When CF wake-up is disabled: Outputs high level.

Remark 0: low level, 1: high level, Hi-Z: high impedance

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(3/3)

Signal Name During RTC

Reset

RxD1/GPIO25 − Hi-Z Hi-Z
TxD1/GPIO26/CLKSEL0
RTS1#/GPIO27/CLKSEL1
CTS1#/GPIO28 − Hi-Z Hi-Z
DCD1#/GPIO29 − Hi-Z Hi-Z
DTR1#/GPIO30/CLKSEL2
DSR1#/GPIO31 − Hi-Z Hi-Z
IRDIN/RxD2 −−−−−
IRDOUT/TxD2 Hi-Z Hi-Z 1
GPIO(15:14)/FPD(7:6)/

CD(2:1)#
GPIO(13:12)/FPD(5:4) − Hi-Z Hi-Z
GPIO11/PCS1# − /Hi-Z Hi-Z Hi-Z/1
GPIO10/FRM/SYSCLK − /Hi-Z Hi-Z Hi-Z

GPIO9/CTS2# − Hi-Z Hi-Z
GPIO8/DSR2# − Hi-Z Hi-Z
GPIO7/DTR2# − Hi-Z Hi-Z
GPIO6/RTS2# − Hi-Z Hi-Z
GPIO5/DCD2# − Hi-Z Hi-Z
GPIO4 − Hi-Z Hi-Z
GPIO3/PCS0# − /Hi-Z Hi-Z Hi-Z/1
GPIO2/SCK − Hi-Z Hi-Z
GPIO1/SO − Hi-Z Hi-Z
GPIO0/SI − Hi-Z Hi-Z
LEDOUT Hi-Z 1

Note 3
Note 3

Note 3

− Hi-Z Hi-Z

After RTC Reset After Reset by

Deadman’s

Switch or

RSTSW

Hi-Z Hi-Z
Hi-Z Hi-Z

Hi-Z Hi-Z

Note 1 Note 1 Note 1

During Suspend

Mode

Note 1 Note 1/Note 2
Note 1 Note 1/Note 2
Note 1 Note 1/Note 2
Note 1 Note 1/Note 2
Note 1 Note 1/Note 2
Note 1 Note 1/Note 2
Note 1 Note 1/Note 2

Note 1

/0/

Note 1

Note 1

/0

Note 1

/1

Note 1

/0

Note 1

Note 1 Note 2/Note 1
Note 1 Note 2/Note 1
Note 1 Note 2/Note 1
Note 1 Note 2/Note 1
Note 1 Note 2/Note 1
Note 1 Note 2

/1

Note 1

Note 1 Note 2/Note 1
Note 1 Note 2/Note 1
Note 1 Note 2/Note 1

During

Hibernate Mode

or Shutdown by

HALTimer

Hi-Z

Note 2/Note 1

Note 2/Note 1

/Hi-Z

Note 2

Note 2/Note 1

Hi-Z

/Hi-Z

Note 2

/

Notes1. Maintains the state of previous Fullspeed mode.

2. The state depends on the GPHIBSTH/GPHIBSTL register setting.

3. The input level is sampled to determine the CPU core operation frequency.

Remark 0: low level, 1: high level, Hi-Z: high impedance

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2.4 Recommended Connection of Unused Pins and I/O Circ uit Types

Pin Name Recommended Connection When Not Used I/O Ci rcuit Type
ADD(21:0) − A
DATA(15:0) − A
MEMRD# − A
MEMWR# − A
SDCS(1:0)#/RAS(1:0)# − A
UDQM/UCAS# − A
LDQM/LCAS# − A
CAS# Leave open A
SDRAS# Leave open A
SDCLK Leave open A
CLKEN Leave open A
SYSDIR Leave open A
SYSEN# Leave open A
IORD#/GPIO16 Connect to VDD_IO or GND_IO via resistor A
IOWR#/GPIO17 Connect to VDD_IO or GND_IO v i a resistor A
IORDY/GPIO18 Connect to VDD_IO or GND_IO via resistor A
IOCS16#/GPIO19 Connect to VDD_IO or GND_IO via resistor A
UBE#/GPIO20/M Connect to VDD_IO or GND_IO v i a resistor A
RESET#/GPIO21 Connect t o VDD_IO or GND_IO v i a res i s tor A
ROMCS(2:0)#/GPIO(24:22) Connect to VDD_IO or GND_IO via resistor A
ROMCS3# − A
SHCLK/LCDCS# Leav e open A
LOCLK/MEMCS16# Leave open A
FLM/MIPS16EN Connect to VDD_IO or GND_IO via resistor A
FPD(3:0) Leave open A
VPLCD/VPGPIO1 Leave open A
VPBIAS/VPGPIO0 Leav e open A
POWER Connect to GND_IO via resistor A
RTCRST# − A
RSTSW# − A
POWERON Leave open A
MPOWER − A
BATTINH/BATTINT# − A
TPX(1:0) − B
TPY(1:0) − C

(1/3)

Remark No specification (−) in the Recommended Connection When Not Used column indicates that the pin is

always connected.

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Pin Name Recommended Connection When Not Used I/O Ci rcuit Type
ADIN(2:0) Connect to GND_AD D
AUDIOIN Connect to GND_AD D
AUDIOOUT Leave open E
CF_WE#/SCANOUT7 Leave open A
CF_OE#/SCANOUT6 Leave open A
CF_IOW#/SCANOUT5 Leave open A
CF_IOR#/SCANOUT4 Leave open A
CF_STSCHG#/SCANOUT3 Connect to VDD_IO via resistor A
CF_CE(2:1)#/SCANOUT(2:1) Leave open A
CF_BUSY#/SCANOUT0 Connec t to VDD_IO via resist or A
CF_REG#/SCANIN7 Leave open A
CF_RESET/SCANIN6 Leave open A
CF_WAIT#/SCANIN5 Connect to VDD_IO via resist or A
CF_IOIS16#/SCANIN4 Connect to VDD_IO via resistor A
CF_VCCEN#/SCANIN3 Leave open A
CF_DEN#/SCANIN2 Leave open A
CF_DIR/SCANIN1 Leave open A
CF_AEN#/SCANIN0 Leave open A
RxD1/GPIO25 Connect to VDD_IO or GND_IO via resis tor A
TxD1/GPIO26/CLKSEL0 Connect to VDD_IO or GND_IO via resistor A
RTS1#/GPIO27/CLKSEL1 Connect to VDD_IO or GND_IO via resistor A
CTS1#/GPIO28 Connect to VDD_IO or GND_IO via resi stor A
DCD1#/GPIO29 Connect to VDD_IO or GND_IO via resistor A
DTR1#/GPIO30/CLKSEL2 Connect to VDD_IO or GND_IO via resistor A
DSR1#/GPIO31 Connect to VDD_IO or GND_IO via resistor A
IRDIN/RxD2 Connect to VDD_IO or GND_IO via resistor A
IRDOUT/TxD2 Leave open A
GPIO(15:14)/FPD(7:6)/CD(2:1)# Connect to VDD_IO or GND_IO via resistor A
GPIO(13:12)/FPD(5:4) Connect to VDD_IO or GND_IO via resistor A
GPIO11/PCS1# Connect to VDD_IO or GND_IO via resistor A
GPIO10/FRM/SYSCLK Connect to VDD_IO or GND_IO via resistor A
GPIO9/CTS2# Connect to VDD_IO or GND_IO via resistor A
GPIO8/DSR2# Connect to VDD_IO or GND_IO vi a resistor A
GPIO7/DTR2# Connect t o VDD_IO or GND_IO via resistor A
GPIO6/RTS2# Connect to VDD_IO or GND_IO via resistor A
GPIO5/DCD2# Connect to VDD_IO or GND_IO via resistor A
GPIO4 Connect to VDD_IO or GND_IO via resistor A

(2/3)

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Pin Name Recommended Connection When Not Used I/O Ci rcuit Type
GPIO3/PCS0# Connect t o VDD_IO or GND_IO via resistor A
GPIO2/SCK Connect to VDD_IO or GND_I O via resistor A
GPIO1/SO Connect to VDD_IO or GND_IO via resistor A
GPIO0/SI Connect to VDD_IO or GND_IO via resistor A
LEDOUT Leave open A

(3/3)

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2.5 Pin I/O Circuits

Type A Type C

V

Data

DD

P-ch

IN/OUT

Data

V

P-ch

DD

IN/OUT

Output

disable

Input

enable

Type B

Data

Output

disable

N-ch

Output

N-ch

disable

P-ch

+

N-ch

N-ch

V

P-ch

−

V

ref

DD

Input

IN/OUT

enable

N-ch

Type D

P-ch

IN

+

−

V

ref

N-ch

P-ch

N-ch

+

−

V

ref

Type E

Analog

output

OUT

voltage

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3.1 Coprocessor 0 (CP0)

The Coprocessor 0 (CP0), which is also called as System Control Coprocessor, is implemented as an integral part
of the CPU, and supports memory management, address translation, exception handling, and operation mode
control.

Memory management, address translation, and operation mode control are provided by a block called memory
management unit (MMU). The MMU contains a 32-entry TLB (translation lookaside buffer) that is used when
translating virtual addresses to physical addresses.

The CP0 has registers shown in Table 3-1 that are used to set various modes for memory management and
exception handling and to indicate statuses of the processor. Each CP0 register has a unique number that is used
as an operand to specify a CP0 register to be accessed.

Caution When accessing the CP0 registers, some instructions require consideration of the interval time

until the next instruction is executed, because there is a delay from when the contents of the
CP0 register change to when this change is reflected in the CPU operation. This time lag is
called a CP0 hazard. For details, refer to CHAPTER 23 COPROCESSOR 0 HAZARDS.

For details about functions of the CP0, refer to V

R4100 Series Architecture User’s Manual.

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Table 3-1. CP0 Registers

Number Register Usage Description
0 Index M em ory management Programmable pointer to TLB array
1 Random Memory management Pseudo-random pointer to TLB array (read only)
2 EntryLo0 Memory management Lower half of TLB entry for even VPN
3 EntryLo1 Memory management Lower half of TLB entry for odd VPN
4 Context Exception processi ng Pointer to kernel virtual PTE in 32-bit mode
5 PageMask Memory management Page size s pecification
6 Wired Memory management Number of wired TLB entri es
7 −−Reserved for future use
8 BadVAddr Exception processi ng Virtual address where the most recent error occurred
9 Count Exception processing Timer count
10 EntryHi Memory management Higher half of TLB entry (includi ng ASID)
11 Compare Exc eption processing Timer compare value
12 Status Exception processi ng Status indic ation
13 Caus e Exception processing Cause of last exception
14 EPC Exception processi ng Exception P rogram Count er
15 PRI d Memory management Processor revi sion identifier
16 Confi g Memory management Configuration (memory system modes) specification

Note1

17
18 WatchLo Exception processing Memory reference t rap address low bits
19 WatchHi Exception processing Memory reference trap address high bits
20 XCont ext Exception processing Pointer to kernel virtual P T E i n 64-bi t mode
21 to 25 −−Reserved for future use
26
27
28 TagLo Memory management Lower half of cache tag
29 TagHi Memory management Higher half of cache tag
30 ErrorEPC Exception processi ng Error Excepti on P rogram Counter
31 −−Reserved for future use

LLAddr

Parity Error
Cache Error

Note2

Note2

Memory management Physic al address for self diagnostics

Exception processi ng Cache parity bits
Exception processi ng Index and status of cache error

Notes1. This register is defined to maintain compatibility with the VR

4000 and VR4400. This register is meaningless

during normal operations.

2. This register is defined to maintain compatibility with the VR4100. This register is not used in the VR4181
hardware.

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3.2 Details of CP0 Registers

3.2.1 Index register (0)

The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The

most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.

The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI)

instructions.

The contents of the Index register are undefined after a reset so that it must be initialized by software.

Figure 3-1. Index Register

31

30 5 4 0

P 0 Index

P: Indicates whether probing is successful or not. It is set to 1 if the latest TLBP instruction fails. It is

cleared to 0 when the TLBP instruction is successful.
Index: Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction.
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

3.2.2 Random register (1)

The Random register is a read-only register. The low-order 5 bits are used in referencing a TLB entry. This
register is decremented each time an instruction is executed. The values that can be set in the register are as
follows:

• The lower bound is the content of the Wired register.

• The upper bound is 31.

The Random register specifies the entry in the TLB that is affected by the TLBWR instruction. The register is
readable to verify proper operation of the processor.

The Random register is set to the value of the upper bound upon Cold Reset. This register is also set to the upper
bound when the Wired register is written. Figure 3-2 shows the format of the Random register.

Figure 3-2. Random Register

31

0 Random

54 0

Random: TLB random index
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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3.2.3 EntryLo0 (2) and EntryLo1 (3) registers

The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages
and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible.
They are used to access the built-in TLB. When a TLB read/write operation is carried out, the EntryLo0 and EntryLo1
registers hold the contents of the low-order 32 bits of TLB entries at even and odd addresses, respectively.

The contents of these registers are undefined after a reset so that they must be initialized by software.

Figure 3-3. EntryLo0 and EntryLo1 Registers

(a) 32-bit mode

31 28 27 6 5 3 2 1 0

PFN C D V G0EntryLo0

31 28 27 6 5 3 2 1 0

PFN C D V G0EntryLo1

(b) 64-bit mode

63 28 27 6 5 3 2 1 0

PFN C D V G0EntryLo0

63 28 27 6 5 3 2 1 0

PFN C D V G0EntryLo1

PFN: Page frame number; high-order bits of the physical address.
C: Specifies the TLB page attribute (see Table 3-2).
D: Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is actually

a write-protect bit that software can use to prevent alteration of data.

V: Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid

exception (TLBL or TLBS) occurs.

G: Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during

TLB lookup.

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the
cache is used, whether the page attribute is “cached” or “uncached” is selected by algorithm.

Table 3-2 lists the page attributes selected according to the value in the C bits.

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Table 3-2. Cache Algorithm

C bit value Cache algorithm
0 Cached
1 Cached
2 Uncached
3 Cached
4 Cached
5 Cached
6 Cached
7 Cached

3.2.4 Context register (4)

The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array
on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss,
the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register
is used by the TLB Refill exception handler for loading TLB entries.

The Context register duplicates some of the information provided in the BadVAddr register, but the information is
arranged in a form that is more useful for a software TLB exception handler.

Figure 3-4. Context Register

(a) 32-bit mode

242531 4 3

PTEBase BadVPN2 0

0

(b) 64-bit mode

24

PTEBase BadVPN2 0

02563 4 3

PTEBase: The PTEBase field is a base address of the PTE entry table.
BadVPN2: This field holds the value (VPN2) obtained by halving the virtual page number of the most recent

virtual address for which translation failed.

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The PTEBase field is used by software as the pointer to the base address of the PTE table in the current user
address space.

The 21-bit BadVPN2 field contains bits 31 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format can directly address
the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value produces the
correct PTE reference address.

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3.2.5 PageMask register (5)

The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison
mask that sets the page size for each TLB entry, as shown in Table 3-3. Five page sizes can be selected between 1
KB and 256 KB.

TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets
of comparison are masked during address translation.

The contents of the PageMask register are undefined after a reset so that it must be initialized by software.

Figure 3-5. PageMask Register

31 19 18 11 10 0

MASK 00

MASK: Page comparison mask, which determines the virtual page size for the corresponding entry.
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

Table 3-3 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves
unexpectedly.

Table 3-3. Mask Values and Page Sizes

Page size Bit

18 17 16 15 14 13 12 11
1 KB 00000000
4 KB 00000011
16 KB 00001111
64 KB 00111111
256 KB 1 1111111

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3.2.6 Wired register (6)

The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as
shown in Figure 3-6. Wired entries cannot be overwritten by a TLBWR instruction, but by a TLBWI instruction.
Random entries can be overwritten by both instructions.

Figure 3-6. Positions Indicated by the Wired Register

TLB

31

Range specified by

the Random register

Value in the Wired register

Range of Wired

entries

0

The Wired register is set to 0 upon Cold Reset. Writing this register also sets the Random register to the value of
its upper bound (see 3.2.2 Random register (1)).

Figure 3-7. Wired Register

31 5 4 0

0 Wired

Wired: TLB wired boundary
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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3.2.7 BadVAddr register (8)

The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that

failed to have a valid translation, or that had an addressing error.

Caution This register saves no information after a bus error exception, because it is not an address error

exception.

Figure 3-8. BadVAddr Register

(a) 32-bit mode

031

BadVAddr

(b) 64-bit mode

063

BadVAddr

BadVAddr:Most recent virtual address for which an addressing error occurred, or for which address

translation failed.

3.2.8 Count register (9)

The read/write Count register acts as a timer. It is incremented in synchronization with the MasterOut clock (1/8,
1/12, or 1/16 frequencies of the PClock), regardless of whether instructions are being executed, retired, or any
forward progress is actually made through the pipeline.

This register is a free-running type. When the register reaches all ones, it rolls over to zero and continues
counting. This register is used for self-diagnostic test, system initialization, or the establishment of inter-process
synchronization.

Figure 3-9. Count Register

031

Count

Count: Up-to-date count value that is compared with the value of the Compare register.

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3.2.9 EntryHi register (10)

The EntryHi register is write-accessible. It is used to access the built-in TLB. The EntryHi register holds the high­order bits of a TLB entry for TLB read and write operations. If a TLB Refill, TLB Invalid, or TLB Modified exception
occurs, the EntryHi register holds the high-order bit of the TLB entry. The EntryHi register is also set with the virtual
page number (VPN2) for a virtual address where an exception occurred and the ASID. See VR4100 Series
Architecture User’s Manual for details of the TLB exception.

The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the
TLB entry as the ASID of the virtual address during address translation.

The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions.

The contents of the EntryHi register are undefined after a reset so that it must be initialized by software.

Figure 3-10. EntryHi Register

(a) 32-bit mode

31 11 10 8 7 0

VPN2 0 ASID

(b) 64-bit mode

63 62 61 11 1040 39 8 7 0

Fill VPN2R 0 ASID

VPN2: Virtual page number divided by two (mapping to two pages)
ASID: Address space ID. An 8-bit ASID field that allows multiple processes to share the TLB; each

process has a distinct mapping of otherwise identical virtual page numbers.

R: Space type (00 → user, 01 → supervisor, 11 → kernel). Matches bits 63 and 62 of the virtual

address.
Fill: Reserved. Ignored on write. When read, returns zero.
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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3.2.10 Compare register (11)

The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own.

When the value of the Count register (see 3.2.8 Count register (9)) equals the value of the Compare register, the
IP7 bit in the Cause register is set. This causes an interrupt as soon as the interrupt is enabled. Writing a value to
the Compare register, as a side effect, clears the timer interrupt request.

For diagnostic purposes, the Compare register is a read/write register. Normally, this register should be only used
for a write.

The contents of the Compare register are undefined after a reset.

Figure 3-11. Compare Register

031

Compare

Compare: Value that is compared with the count value of the Count register.

3.2.11 Status register (12)

The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic
states of the processor.

Figure 3-12. Status Register (1/2)

292827262524 1615 8765 321031

0

0 RE DS IM UX KSU

CU0

4

EXL

IEKX SX

ERL

CU0: Enables/disables the use of the coprocessor (1 → Enabled, 0 → Disabled).

CP0 can be used in Kernel mode at all times.

RE: Enables/disables reversing of the endian setting in User mode (0 → Disabled, 1 → Enabled). This

bit must be set to 0 since the VR4181 supports the little-endian order only.
DS: Diagnostic Status field (see Figure 3-13).
IM: Interrupt mask field used to enable/disable interrupts (0 → Disabled, 1 → Enabled). This field

consists of 8 bits that are used to control eight interrupts. The bits are assigned to interrupts as

follows:

IM7: Masks a timer interrupt.
IM(6:2): Mask ordinary interrupts (Int(4:0)

Note

). However, Int(4:3)

Note

never occur in the VR4181.

IM(1:0): Mask software interrupts.

76

Note Int(4:0) are internal signals of the VR4110 CPU core. For details about connection to

the on-chip peripheral units, refer to CHAPTER 9 INTERRUPT CONTROL UNIT
(ICU).

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CHAPTER 3 CP0 REGISTERS

Figure 3-12. Status Register (2/2)

KX: Enables 64-bit addressing in Kernel mode (0 → 32-bit, 1 → 64-bit). 64-bit operations are always

valid in Kernel mode.
SX: Enables 64-bit addressing and operation in Supervisor mode (0 → 32-bit, 1 → 64-bit).
UX: Enables 64-bit addressing and operation in User mode (0 → 32-bit, 1 → 64-bit).
KSU: Sets and indicates the operating mode (10 → User, 01 → Supervisor, 00 → Kernel).
ERL: Sets and indicates the error level (0 → Normal, 1 → Error).
EXL: Sets and indicates the exception level (0 → Normal, 1 → Exception).
IE: Sets and indicates interrupt enabling/disabling (0 → Disabled, 1 → Enabled).
0: Reserved for future use. Write 0 in a write operation. When this bit is read, 0 is read.

Figure 3-13 shows the details of the Diagnostic Status (DS) field. All DS field bits other than the TS bit are

writable.

Figure 3-13. Status Register Diagnostic Status Field

161718192021222324

0 BEV TS SR 0 CH CE DE

BEV: Specifies the base address of a TLB Refill exception vector and common exception vector (0 →

Normal, 1 → Bootstrap).
TS: Occurs the TLB to be shut down (read-only) (0 → Not shut down, 1 → Shut down). This bit is used

to avoid any problems that may occur when multiple TLB entries match the same virtual address.

After the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut

down even if a TLB entry matching a virtual address is marked as being invalid (with the V bit

cleared).
SR: Occurs a Soft Reset or NMI exception (0 → Not occurred, 1 → Occurred).
CH: CP0 condition bit (0 → False, 1 → True). This bit can be read and written by software only; it

cannot be accessed by hardware.
CE, DE: These are prepared to maintain compatibility with the VR4100, and are not used in the VR4181

hardware.
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The Status register has the following fields where the modes and access statuses are set.

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(1) Interrupt enable

Interrupts are enabled when all of the following conditions are true:

• IE bit is set to 1.

• EXL bit is cleared to 0.

• ERL bit is cleared to 0.

• The appropriate bit of the IM field is set to 1.

(2) Operating modes

The following Status register bit settings are required for User, Kernel, and Supervisor modes.

• The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0.

• The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0.

• The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1.

Access to the kernel address space is allowed when the processor is in Kernel mode.
Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode.
Access to the user address space is allowed in any of the three operating modes.

(3) Addressing modes

The following Status register bit settings select 32- or 64-bit operation for each of User, Kernel, and Supervisor
operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit
addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently.

• 64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel
mode. If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address
space.

• 64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1. If this bit is set, an
XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space.

• 64-bit addressing and operations are enabled for User mode when UX bit = 1. If this bit is set, an XTLB Refill
exception occurs if a TLB miss occurs in the User mode address space.

(4) Status after reset

The contents of the Status register are undefined after Cold Resets, except for the following bits in the Diagnostic
Status field.

• TS and SR bits are cleared to 0.
SR bit is 0 after Cold Reset, and is 1 after Soft Reset or NMI.

• ERL and BEV bits are set to 1.

78

Remark Cold Reset and Soft Reset are resets for the CPU core (see 5.3 Reset of CPU Core). For the

reset of all the VR

4181 including peripheral units, refer to CHAPTER 5 INITIALIZATION

INTERFACE and CHAPTER 10 POWER MANAGEMENT UNIT (PMU).

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CHAPTER 3 CP0 REGISTERS

3.2.12 Cause register (13)

The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code
indicates one of the causes (see Table 3-4). Other bits hold the detailed information of the specific exception. All
bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 bits are used for
software interrupts.

Figure 3-14. Cause Register

827 16 15 6721031 30 29 28

BD 0 CE 0 IP(7:0) 0 ExcCode 0

BD: Indicates whether the most recent exception occurred in the branch delay slot (1 → In delay slot, 0

→ Normal).

CE: Indicates the coprocessor number in which a Coprocessor Unusable exception occurred.

This field will remain undefined for as long as no exception occurs.

IP: Indicates whether an interrupt is pending (1 → Interrupt pending, 0 → No interrupt pending).

IP7: A timer interrupt.
IP(6:2): Ordinary interrupts (Int(4:0)

Note

). However, Int(4:3)

Note

never occurs in the VR4181.

IP(1:0): Software interrupts. Only these bits cause an interrupt exception, when they are set

to 1 by means of software.

Note Int(4:0) are internal signals of the VR4110 CPU core. For details about connection to

the on-chip peripheral units, refer to CHAPTER 9 INTERRUPT CONTROL UNIT
(ICU).

ExcCode: Exception code field (refer to Table 3-4 for details).
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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Table 3-4. Cause Register Exception Code Field

Exception code Mnemonic Description
0 Int Interrupt exception
1 Mod TLB Modified exception
2 TLBL TLB Refill exception (load or fetch)
3 TLBS TLB Refill exception (store)
4 AdEL Address Error exception (load or fetch)
5 AdES Address Error exception (store)
6 IBE Bus Error ex ception (instruction fetch)
7 DBE Bus E rror exception (data load or store)
8 Sys System Call exception
9 Bp Breakpoint excepti on
10 RI Reserved Instruction exception
11 CpU Coprocessor Unusable exception
12 Ov Integer Overflow exception
13 Tr Trap exception
14 to 22  Reserved for future use
23 WATCH Watch exception
24 to 31  Reserved for future use

The VR4181 has eight interrupt request sources, IP7 to IP0. They are used for the purpose as follows.
For the detailed description of interrupts of the CPU core, refer to V

R4100 Series Architecture User’s Manual.

(1) IP7

This bit indicates whether there is a timer interrupt request.
It is set when the values of the Count register and Compare register match.

(2) IP6 to IP2

IP6 to IP2 reflect the state of the interrupt request signals of the CPU core.

(3) IP1 and IP0

These bits are used to set/clear a software interrupt request.

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3.2.13 Exception Program Counter (EPC) register (14)

The Exception Program Counter (EPC) is a read/write register that contains the address at which processing
resumes after an exception has been serviced. The contents of this register change depending on whether
execution of MIPS16 instructions is enabled or disabled. Setting the MIPS16EN pin after RTC reset specifies
whether execution of the MIPS16 instructions is enabled or disabled.

When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the EPC
register:

• Virtual address of the instruction that caused the exception

• Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with
the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1)

When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the EPC

register during a 32-bit instruction execution:

• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs

• Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception
occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction, and
the BD bit in the Cause register is set to 1)

When the 16-bit instruction is executed, either of the following addresses is contained in the EPC register:

• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs

• Virtual address of the immediately preceding Extend or jump instruction and ISA mode at which an exception
occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction or in
the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1)

The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception-

causing instruction contained in the EPC register in the event of another exception.

The EPC register never indicates the address of the instruction in a branch delay slot.

Figure 3-15. EPC Register (When MIPS16 ISA Is Disabled)

(a) 32-bit mode

031

EPC

(b) 64-bit mode

063

EPC

EPC: Restart address (virtual) after exception processing.

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Figure 3-16. EPC Register (When MIPS16 ISA Is Enabled)

(a) 32-bit mode

1

031

EPC EIM

EPC: Bits 31 to 1 of restart address (virtual) after exception processing.
EIM: ISA mode at which an exception occurs (1 → When MIPS16 SIA instruction is executed, 0 →

When MIPS III ISA instruction is executed).

(b) 64-bit mode

1

063

EPC EIM

EPC: Bits 63 to 1 of restart address (virtual) after exception processing.
EIM: ISA mode at which an exception occurs (1 → When MIPS16 SIA instruction is executed, 0 →

When MIPS III ISA instruction is executed).

3.2.14 Processor Revision Identifier (PRId) register (15)

The 32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying the

implementation and revision level of the CPU and CP0.

Figure 3-17. PRId Register

31 16 15 8 7 0

0 Imp Rev

Imp: CPU core processor ID number (0x0C for the VR4181)
Rev: CPU core processor revision number
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The processor revision number is stored as a value in the form y.x, where y is a major revision number in bits 7 to

4 and x is a minor revision number in bits 3 to 0.

The processor revision number can distinguish CPU core revisions of the VR4181, however there is no guarantee
that changes to the CPU core will necessarily be reflected in the PRId register, or that changes to the revision
number necessarily reflect real CPU core changes. Therefore, create a program that does not depend on the
processor revision number field.

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3.2.15 Config register (16)

The Config register specifies various configuration options selected on the VR

4181.

Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and
are included in the Config register as read-only status bits for the software to access. Other configuration options
(AD, EP, and K0 fields) can be read/written and controlled by software; on Cold Reset these fields are undefined.
Since only a subset of the VR4000 SeriesTM options are available in the VR4181, some bits are set to constants (e.g.,
bits 14 and 13) that were variable in the VR4000 Series. The Config register should be initialized by software before
caches are used.

The contents of the Config register are undefined after a reset so that it must be initialized by software.

Caution Be sure to set the EP field and the AD bit to 0. If they are set with any other values, the

processor may behave unexpectedly.

Figure 3-18. Config Register (1/2)

31 30 28 27 24 23 22 21 2019 18 17 16 15 14 13 12 11 9 8 6 5 3 2 0

M16

0EC EPAD0

010BE10CS IC DC 0 K0

EC: System clock ratio (read only)

0 → Processor clock frequency divided by 2
1 → Processor clock frequency divided by 3
2 → Processor clock frequency divided by 4
3 to 7 → Reserved

EP: Transfer data pattern (cache write-back pattern) setting

0 → DD: 1 word per 1 cycle
Others → Reserved

AD: Accelerate data mode

0 → VR4000 Series compatible mode
1 → Reserved

M16: MIPS16 ISA mode enable/disable indication (read only)

0 → MIPS16 instruction cannot be executed
1 → MIPS16 instruction can be executed.

BE: BigEndianMem (Endian mode indication)

0 → Little endian
1 → Reserved

CS: Cache size mode indication (n = IC, DC)

0 → Reserved

(n+10)

1 → 2

IC: Instruction cache size indication. 2

bytes

(IC+10)

bytes in the VR4181.
2 → 4 KB
Others → Reserved

DC: Data cache size indication. 2

(DC+10)

bytes in the VR4181.
2 → 4 KB
Others → Reserved

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CHAPTER 3 CP0 REGISTERS

Figure 3-18. Config Register (2/2)

K0: kseg0 cache coherency algorithm

2 → Uncached

Others → Cached
1: 1 is returned when read.
0: 0 is returned when read.

3.2.16 Load Linked Address (LLAddr) register (17)

The read/write Load Linked Address (LLAddr) register is not used with the VR

4181 processor except for diagnostic
purpose, and serves no function during normal operation. The LLAddr register is implemented just for compatibility
between the VR4181 and VR4000 or VR4400.

The contents of the LLAddr register are undefined after a reset.

Figure 3-19. LLAddr Register

31 0

PAddr: 32-bit physical address

PAddr

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3.2.17 WatchLo (18) and WatchHi (19) registers

4181 processor provides a debugging feature to detect references to a selected physical address; load and

The VR

store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception.

The contents of these registers are undefined after a reset so that they must be initialized by software.

Figure 3-20. WatchLo Register

321031

PAddr0 0 R W

PAddr0: Specifies physical address bits 31 to 3.
R: Specifies detection of watch address references when load instructions are executed (1 → Detect,

0 → Not detect).

W: Specifies detection of watch address references when store instructions are executed (1 → Detect,

0 → Not detect).

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

Figure 3-21. WatchHi Register

031

0

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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CHAPTER 3 CP0 REGISTERS

3.2.18 XContext register (20)

The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating
system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system
loads the untranslated data from the PTE into the TLB to handle the software error.

The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode.

The XContext register duplicates some of the information provided in the BadVAddr register, and puts it in a form
useful for the XTLB exception handler.

This register is included solely for operating system use. The operating system sets the PTEBase field in the
register, as needed.

Figure 3-22. XContext Register

32 035 34 3363 4 3

PTEBase R BadVPN2 0

PTEBase: Base address of the PTE entry table.
R: Space type (00 → User, 01→ Supervisor, 11 → Kernel). The setting of this field matches virtual

address bits 63 and 62.

BadVPN2: The value (VPN2) obtained by halving the virtual page number of the most recent virtual address

for which translation failed.

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format may be used directly
to address the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value
produces the appropriate PTE reference address.

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3.2.19 Parity Error register (26)

The Parity Error (PErr) register is a readable/writable register. This register is defined to maintain software-

compatibility with the VR

4100, and is not used in hardware because the VR4181 has no parity.

Figure 3-23. Parity Error Register

08731

0 Diagnostic

Diagnostic:8-bit self diagnostic field.
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

3.2.20 Cache Error register (27)

The Cache Error register is a readable/writable register. This register is defined to maintain software-compatibility

with the VR

4100, and is not used in hardware because the VR4181 has no parity.

Figure 3-24. Cache Error Register

31 0

0

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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3.2.21 TagLo (28) and TagHi (29) registers

The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag during cache
initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and MTC0
instructions.

The contents of these registers are undefined after a reset.

Figure 3-25. TagLo Register

(a) When used with data cache

31 10 9 8 7 6

PTagLo

VDW 0

0

(b) When used with instruction cache

31 10 9 8

PTagLo

V0

0

PTagLo: Specifies physical address bits 31 to 10.
V: Valid bit
D: Dirty bit. However, this bit is defined only for the compatibility with the VR4000 Series processors,

and does not indicate the status of cache memory in spite of its readability and writability. This bit

cannot change the status of cache memory.
W: Writeback bit (set if cache line has been updated)
0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

Figure 3-26. TagHi Register

31 0

0

0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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3.2.22 ErrorEPC register (30)

The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the

Program Counter value at which the Cold Reset, Soft Reset, or NMI exception has been serviced.

The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after
servicing an error. The contents of this register change depending on whether execution of MIPS16 instructions is
enabled or disabled. Setting the MIPS16EN pin after RTC reset specifies whether the execution of MIPS16
instructions is enabled or disabled.

When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the ErrorEPC
register:

• Virtual address of the instruction that caused the exception

• Virtual address of the immediately preceding branch or jump instruction, when the instruction associated with
the error exception is in a branch delay slot, and the BD bit in the Cause register is set to 1

When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the ErrorEPC

register during a 32-bit instruction execution:

• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs

• Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception
occurs when the instruction associated with the error exception is in a branch delay slot, and the BD bit in the
Cause register is set to 1

When the 16-bit instruction is executed, either of the following addresses is contained in the ErrorEPC register:

• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs

• Virtual address of the immediately preceding jump instruction or Extend instruction and ISA mode at which an
exception occurs when the instruction associated with the error exception is in a branch delay slot of the jump
instruction or is the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1

The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This
prevents the processor when other exceptions occur from overwriting the address of the instruction in this register
that causes an error exception.

The ErrorEPC register never indicates the address of the instruction in a branch delay slot.

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CHAPTER 3 CP0 REGISTERS

Figure 3-27. ErrorEPC Register (When MIPS16 ISA Is Disabled)

(a) 32-bit mode

ErrorEPC

(b) 64-bit mode

ErrorEPC

ErrorEPC: Virtual restart address after Cold reset, Soft reset, or NMI exception.

Figure 3-28. ErrorEPC Register (When MIPS16 ISA Is Enabled)

031

063

(a) 32-bit mode

1031

ErrorEPC ErIM

ErrorEPC: Bits 31 to 1 of virtual restart address after Cold reset, Soft reset, or NMI exception.
ErIM: ISA mode at which an error exception occurs (1 → MIPS16 ISA, 0 → MIPS III ISA).

(b) 64-bit mode

1063

ErrorEPC ErIM

ErrorEPC: Bits 63 to 1 of virtual restart address after Cold reset, Soft reset, or NMI exception.
ErIM: ISA mode at which an error exception occurs (1 → MIPS16 ISA, 0 → MIPS III ISA).

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CHAPTER 4 MEMORY MANAGEMENT SYSTEM

4.1 Overview

The VR4181 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to
translate virtual addresses into physical addresses.

Virtual addresses are translated into physical addresses using an on-chip TLB. The on-chip TLB is a full­associative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. The TLB
is accessed through the CP0 registers. Note that the virtual address space includes areas that are translated to
physical addresses without using a TLB, and areas where the use of cache memory can be selected.

The VR4181 has three operating modes: User, Supervisor, and Kernel; the manner in which memory addresses
are mapped depends on these operating modes. In addition, the VR4181 supports the 32-bit and 64-bit addressing
modes; the manner in which memory addresses are translated or mapped depends on these addressing modes.

For details about the memory management system and virtual address space, refer to V

Architecture User’s Manual.

R4100 Series

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CHAPTER 4 MEMORY MANAGEMENT SYSTEM

4.2 Physical Address Space

Using a 32-bit address, the processor physical address space encompasses 4 GB. The VR4181 uses this 4 GB

physical address space as shown in Figure 4-1.

Figure 4-1. V

0xFFFF FFFF

0x2000 0000

0x1FFF FFFF

0x1800 0000

0x17FF FFFF

0x1400 0000

0x13FF FFFF

0x1000 0000

0x0FFF FFFF

0x0D00 0000

0x0CFF FFFF

0x0C00 0000

0x0BFF FFFF

0x0B00 0000

0x0AFF FFFF

0x0A00 0000

0x09FF FFFF

R4181 Physical Address Space

(Mirror image of 0x0000 0000 to 0x1FFF FFFF area)

ROM space (including a boot ROM)

External system bus I/O space (ISA I/O)

External system bus memory space (ISA memory)

RFU

Internal ISA I/O space 1

Internal ISA I/O space 2

MBA bus I/O space

92

RFU

0x0400 0000

0x03FF FFFF

DRAM space

0x0000 0000

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Table 4-1. VR4181 Physical Address Space

Physical address S pace Capacity (bytes)
0xFFFF FFFF to 0x2000 0000 Mirror image of 0x1FFF FFFF to 0x0000 0000 3.5 G
0x1FFF FFFF to 0x1800 0000 ROM space 128 M
0x17FF FFFF to 0x1400 0000 External system bus I/O space (ISA I/O) 64 M
0x13FF FFFF to 0x1000 0000 External system bus memory space (ISA memory) 64 M
0x0FFF FFFF to 0x0D00 0000 Space reserved for future us e 48 M
0x0CFF FFFF to 0x0C00 0000 Internal ISA I /O space 1 16 M
0x0BFF FFFF to 0x0B00 0000 Internal ISA I/O spac e 2 16 M
0x0AFF FFFF to 0x0A00 0000 MBA bus I/O space 16 M
0x09FF FFFF to 0x0400 0000 Space reserved for future use 96 M
0x03FF FFFF to 0x0000 0000 DRAM (SDRAM) space 64 M

4.2.1 ROM space

The ROM space mapping differs depending on the capacity of the ROM being used. The ROM capacity is set via

the ROMs(1:0) bits in the BCUCNTREG1 reg ister.

The physical addresses of the ROM space are listed below.

Table 4-2. ROM Address Map

Physical address When using 32-Mbit ROM When using 64-Mbit ROM
0x1FFF FFFF to 0x1FC0 0000 Bank 3 (ROMCS3#) Bank 3 (ROMCS3#)
0x1FBF FFFF to 0x1F80 0000 Bank 2 (ROMCS2#)
0x1F7F FFFF to 0x1F40 0000 Bank 1 (ROMCS1#) Bank 2 (ROMCS 2#)
0x1F3F FFFF to 0x1F00 0000 Bank 0 (ROMCS0#)
0x1EFF FFFF to 0x1E80 0000 Reserved for future use Bank 1 (ROMCS1#)
0x1E7F FFFF to 0x1E00 0000 Bank 0 (ROMCS0#)

4.2.2 External system bus space

The following two types of system bus space are available.

• External system bus I/O space
This corresponds to the ISA’s I/O space.

• External system bus memory space
This corresponds to the ISA’s memory space.

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4.2.3 Internal I/O space

R4181 has three internal I/O spaces. Each of these spaces is described below.

The V

CHAPTER 4 MEMORY MANAGEMENT SYSTEM

Table 4-3. Internal I/O Space 1

Physical address Internal I/O
0x0C00 001F to 0x0C00 0010 SIU1
0x0C00 000F to 0x0C00 0000 SIU2

Table 4-4. Internal I/O Space 2

Physical address Internal I/O
0x0B00 09FF to 0x0B00 0900 CS I
0x0B00 08FF to 0x0B00 0800 ECU
0x0B00 07FF to 0x0B00 0400 Reserved for future use
0x0B00 03FF to 0x0B00 0300 GIU
0x0B00 02FF to 0x0B00 02D0 Reserved for future use
0x0B00 02CF to 0x0B00 02C0 ISA Bri dge
0x0B00 02BF to 0x0B00 02A0 PIU-2
0x0B00 029F to 0x0B00 0280 Reserved for future use
0x0B00 027F to 0x0B00 0260 A/D test
0x0B00 025F to 0x0B00 0240 LED
0x0B00 023F to 0x0B00 01E0 Reserved for future us e
0x0B00 01DF to 0x0B00 01C0 RTC-2
0x0B00 01BF to 0x0B00 01A0 Reserved for future use
0x0B00 019F to 0x0B00 0180 KIU
0x0B00 017F to 0x0B00 0160 AIU
0x0B00 015F to 0x0B00 0140 Reserved for future use
0x0B00 013F to 0x0B00 0120 PIU-1
0x0B00 011F to 0x0B00 0100 Reserved for future use
0x0B00 00FF to 0x0B00 00E0 DS U
0x0B00 00DF to 0x0B00 00C0 RTC-1
0x0B00 00BF to 0x0B00 00A0 PMU
0x0B00 009F to 0x0B00 0080 ICU-3
0x0B00 007F to 0x0B00 0000 Reserved for future use

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Table 4-5. MBA Bus I/O Space

Physical address Internal I/O
0x0A00 06FF to 0x0A00 0600 DCU-2
0x0A00 05FF to 0x0A00 0500 Reserved for future use
0x0A00 04FF to 0x0A00 0400 LCD controller
0x0A00 03FF to 0x0A00 0300 Mem ory controller
0x0A00 02FF to 0x0A00 0220 Reserved for future use
0x0A00 021F to 0x0A00 0200 ICU-2
0x0A00 01FF to 0x0A00 00A0 Reserved for future use
0x0A00 009F to 0x0A00 0080 ICU-1
0x0A00 007F to 0x0A00 0050 Reserved for future use
0x0A00 004F to 0x0A00 0020 DCU-1
0x0A00 001F to 0x0A00 0000 MBA Host Bridge

4.2.4 DRAM space

The DRAM space differs depending on the capacity of the DRAM being used. The DRAM capacity is set via the

B1Config(1:0) bits in the MEMCFG_REG register.

The physical addresses of the DRAM space are listed below.

Table 4-6. DRAM Address Map

Physical address When using 16-Mbit DRAM When using 64-Mbit DRAM
0x00FF FFFF to 0x0080 0000 Reserved f or f uture use Bank 1 (SDCS 1#/RAS1#)
0x007F FFFF to 0x0040 0000 Bank 0 (SDCS0#/RAS0#)
0x003F FFFF to 0x0020 0000 Bank 1 (SDCS1#/RAS1#)
0x001F FFFF to 0x0000 0000 Bank 0 (SDCS0#/RAS0#)

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CHAPTER 5 INITIALIZATION INTERFACE

This chapter describes the reset signal descriptions and types, signal- and timing-related dependence, and the

initialization sequence during each mode that can be selected by the user.

A detailed description of the operation during and after a reset and its relationships to the power modes are also

provided in CHAPTER 10 POWER MANAGEMENT UNIT (PMU).

Remark # that follows signal names indicates active low.

5.1 Reset Function

There are five ways to reset the VR4181. Each is summarized below.

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5.1.1 RTC reset

During power-on, set the RTCRST# pin as active. After waiting about 600 ms for the 32.768 kHz oscillator to begin
oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the RTC
unit to begin counting. Then, the states of the MIPS16EN and CLKSEL(2:0) pins are read after one RTC cycle. Next,

4181 asserts the POWERON pin and checks the state of the BATTINH/BATTINT# signal. If it is at high level,

the VR
the VR4181 asserts the MPOWER pin and activates the external agent’s DC/DC converter. After the stabilization time
period (about 350 ms) of the DC/DC converter, the VR4181 begins PLL oscillation and starts all clocks (a period of
about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation).

An RTC reset does not save any of the status information and it completely initializes the processor’s internal
state. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all
guaranteed.

After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset
when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on
Initialization).

After power-on, the processor’s pin statuses are undefined since the RTCRST# is asserted, until the 32.768 kHz
clock oscillator starts oscillation. The pin statuses after oscillation starts are described in CHAPTER 2 PIN
FUNCTIONS in this document.

RTCRST# (Input)

POWER (Input)

POWERON (Output)

MPOWER (Output)

ColdReset# (Internal)

Reset# (Internal)

PLL (Internal)

RTC (Internal,

32.768 kHz)

L

Undefined

> 600 ms

Stable oscillation

Figure 5-1. RTC Reset

> 32 ms

350 ms

Undefined

16 ms

Stable oscillation

16MasterClock

Note

Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.

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5.1.2 RSTSW reset

After the RSTSW# pin becomes active and then becomes inactive 100

s later, the VR4181 starts PLL oscillation

µ

and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL
oscillation).

An RSTSW reset basically initializes the entire internal state except for the RTC timer, the GIU, and the PMU. The
VR4181 has function to preserve DRAM data during RSTSW reset. For detail, refer to CHAPTER 10 POWER
MANAGEMENT UNIT (PMU).

After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset
when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on

Initialization).

Figure 5-2. RSTSW Reset

RSTSW# (Input)

POWER (Input)

MPOWER (Output)

ColdReset# (Internal)

Reset# (Internal)

PLL (Internal)

RTC (Internal,

32.768 kHz)

L

H

Stable oscillation

Stable oscillation

Undefined

> 3RTC

16 ms

16MasterClock

Stable oscillation

Note

Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.

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5.1.3 Deadman’s Switch reset

After the Deadman’s Switch unit is enabled, if the Deadman’s Switch is not cleared within the specified time

period, the VR

4181 immediately enters to reset status. Setting and clearing of the Deadman’s Switch is performed by

software.

A Deadman’s Switch reset initializes the entire internal state except for the RTC timer, the GIU, and the PMU.
Since the DRAM is not switched to self-refresh mode, the contents of DRAM after a Deadman’s Switch reset are not
at all guaranteed.

After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset
occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization).

Figure 5-3. Deadman’s Switch Reset

RSTSW# (Input)

POWER (Input)

MPOWER (Output)

ColdReset# (Internal)

Reset# (Internal)

PLL (Internal)

RTC (Internal,

32.768 kHz)

H

L

H

Stable oscillation

Stable oscillation

Undefined

16 ms

16MasterClock

Stable oscillation

Note

Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.

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5.1.4 Software shutdown

When the software executes the HIBERNATE instruction, the VR

4181 sets the MPOWER pin as inactive, then
enters reset status. Recovery from reset status occurs when the POWER pin or DCD# signal is ass erted or when an
unmasked wake-up interrupt request is occurred.

A reset by software shutdown initializes the entire internal state except for the RTC timer, the GIU, and the PMU.

After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset
occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization).

Cauiton The V

Fullspeed mode. To preserve DRAM data, software must set the DRAM to self-refresh mode. For
details, refer to CHAPTER 10 POWER MANAGEMENT UNIT (PMU).

POWER (Input)

POWERON (Output)

MPOWER (Output)

ColdReset# (Internal)

Reset# (Internal)

PLL (Internal)

R4181 does not set the DRAM to self-refresh mode at the transition to Hibernate mode from

Figure 5-4. Software Shutdown

Stable oscillation

Stopped

Undefined

RTC (Internal,

32.768 kHz)
Stable oscillation

> 32 ms

Note1

Notes1. Wait time for activation. It can be changed by setting the PMUWAITREG register.

2. MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock

frequency.

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16 ms

16MasterClock

Note2