NEC UPG153TB-E3 Datasheet

DATA SHEET

GaAs INTEGRATED CIRCUIT

µµµµ

PG153TB

L-BAND SPDT SWITCH

DESCRIPTION

The µPG153TB is an L-band SPDT (Single Pole Double Throw) GaAs FET switch which was developed for digital
cellular or cordless telephone application. The device can operate from 100 MHz to 2.5 GHz, having the low
insertion loss. It housed in an original 6-pin super minimold package that is smaller than usual 6-pin minimold easy
to install and contributes to miniaturizing the system.

FEATURES

• Low Insertion Loss : L

• High Linearity Switching: P

INS

= 0.7 dB TYP. @V

in (1 dB)

= +33.0 dBm TYP. @V

• Small 6-pin super minimold package (Size: 2.0 × 1.25 × 0.9 mm)

CONT

= +3.0 V/0 V, f = 2 GHz

CONT

= +3.0 V/0 V, f = 2 GHz

APPLICATIONS

• L, S-band digital cellular or cordless telephone

• PCS, WLAN, and WLL applications

ORDERING INFORMATION

Part Number Marking Package Supplying Form

µ

PG153TB-E3 G1J 6-pin super minimold Embossed tape 8 mm wide.

Pin 1, 2, 3 face to tape perf oration side.
Qty 3 kp/reel.

Remark

To order evaluation samples, please contact your local NEC sales office. (Part number for sample
order:

PG153TB)

µ

ABSOLUTE MAXIMUM RATINGS (TA = +25°C)

Parameter Symbol Ratings Unit
Control Voltage 1, 2 V
Input Power P
Total Power Dissipat i on P
Operating Temperature T
Storage Temperature T

Condition 2.5 ≤ | V

Note

CONT1

CONT1, 2

– V

in

tot

A

stg

CONT2

–6.0 to +6.0

–45 to +85 °C

–55 to +150 °C

| ≤ 6.0 V

Note

+33 dBm

0.15 W

V

Remarks 1.

Mounted on a 50 × 50 × 1.6 mm double copper clad epoxy glass PWB, T
Operation in excess of any one of these parameters may result in permanent damage.

2.

Caution The IC must be handled with care to prevent static discharge because its circuit is composed of

GaAs MES FET.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. P13632EJ2V0DS00 (2nd edition)
Date Published September 1999 N CP(K)
Printed in Japan

The mark shows major revised points.

A

= +85°C

1998, 1999©

µµµµ

PG153TB

PIN CONNECTIONS

Pin No. Connection Pin No. Connection

1OUT14V

CONT2

2GND5 IN
3OUT26V

CONT1

RECOMMENDED OPERATING CONDITIONS (TA = +25°C)

Parameter Symbol MIN. TYP. MAX. Unit
Control Voltage (Low) V
Control Voltage (High) V

CONT

CONT

–0.2 0 +0.2 V
+2.5 +3.0 +5.3 V

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified, TA = +25°C, V

CONT1

Off chip DC blocking capacitors value; 51 pF)

Parameter S ymbol Test Conditions MIN. TYP. MAX. Unit
Insertion Loss L

INS

Isolation ISL

Input Return Loss RL
Output Return Loss RL
Input Power at 0.1 dB

Compression Point
Input Power at 1 dB

Compression Point

Note 2

Note 2

Switching Speed t
Control Current I

in (0.1 dB)

P

in (1 dB)

P

CONT

sw

f = 100 M to 1.0 GHz
f = 2.0 GHz
f = 2.5 GHz
f = 100 M to 2.0 GHz 10 13
f = 1.0 GHz 15 18.5
f = 2.5 GHz

in

f = 100 M to 2.0 GHz 11 15

out

f = 100 M to 2.0 GHz 11 15
f = 2.0 GHz

f = 2.0 GHz 31 33

V

= 3 V, V

CONT

= 3 V/0 V

CONT2

= 0 V or V

(Top View) (Bottom View)

3 4

2 5

CONT1

G1J

= 0 V, V

1 6

−

−

−

CONT2

0.50 0.65

0.70 0.90

0.90

4 3

5 2

6 1

= 3 V, ZO = 50 Ω,

Note 1

−

−

−

Note 1

−

10

−

−

−

−

29

−

−

−

−

30
20 50

−

dB

dB

dB
dB

dBm

dBm

ns

A

µ

Notes 1.

Characteristic for reference at f = 2.0 to 2.5 GHz

in (0.1 dB)

P

2.

1 dB than that of linear range. All other characteristics are measured in linear range.

Cautions 1. When the

No. 3 (OUT2) and No. 5 (IN). The value of DC blocking capacitors should be chosen to
accommodate the frequency of operation, band width, switching speed and the condition
with actual board of your system.
The range of recommended DC blocking capacitor value is less than 100 pF.

2. The distance between IC’s GND pin and ground pattern of substrate should be as shorter as
possible to avoid parasitic parameters.

2

in (1 dB)

or P

is measured the input power level when the insertion loss increases more 0.1 dB or

PG153TB is used, it is necessary to use DC blocking capacitors for No. 1 (OUT1),

µµµµ

Data Sheet P13632EJ2V0DS00

TYPICAL CHARACTERISTICS (ON)

CONT

TEST CONDITIONS: V

= 3 V/0 V, Pin = 0 dBm, TA = +25 °C

µµµµ

PG153TB

IN

IN-OUT1 INPUT RETURN LOSS vs. FREQUENCY

CH1 S

11

(dB)

in

Input Return Loss RL

MARKER 1
1 GHz

0

–10
–20
–30
–40

START 0.300 000 000 GHz

10 dB/REF 0 dB

1

2

Frequency f (GHz)

OUT1
OUT2

50 Ω

3

STOP 3.300 000 000 GHz

1: –22.622 dB

1 GHz

2: –28.228 dB

1.5 GHz

3: –27.318 dB

2 GHz

4: –18.235 dB

2.5 GHz

4

IN-OUT1 ISOLATION vs. FREQUENCY

CH1 S12log MAGlog MAG 10 dB/REF 0 dB

MARKER 1
1 GHz

0

–10

Isolation ISL (dB)

–20
–30
–40

START 0.300 000 000 GHz

1

2

Frequency f (GHz)

1: –18.937 dB

1 GHz

2: –15.032 dB

1.5 GHz

3: –12.119 dB

2 GHz

4: –10.675 dB

2.5 GHz

3

STOP 3.300 000 000 GHz

4

IN-OUT1 INSERTION LOSS vs. FREQUENCY

CH1 S21log MAG 1 dB/REF 0 dB

1: –0.764 dB

1 GHz

2: –0.957 dB

1.5 GHz

3

3: –1.215 dB

2 GHz

4: –1.516 dB

2.5 GHz

4

4

(dB)

INS

Insertion Loss L

MARKER 1
1 GHz

0

–1
–2
–3
–4

START 0.300 000 000 GHz

1

2

STOP 3.300 000 000 GHz

Frequency f (GHz)

Caution This data is including loss of the test fixture.

IN-OUT1 OUTPUT RETURN LOSS vs. FREQUENCY

CH1 S22log MAG 10 dB/REF 0 dB

1: –24.057 dB
2: –37.231 dB

(dB)

out

Output Return Loss RL

MARKER 1
1 GHz

0

–10
–20
–30
–40

START 0.300 000 000 GHz

1

2

STOP 3.300 000 000 GHz

Frequency f (GHz)

3

3: –25.963 dB
4: –19.332 dB

4

4

1 GHz

1.5 GHz
2 GHz

2.5 GHz

Data Sheet P13632EJ2V0DS00

3