NEC UPD98401AGD-MML Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD98401A

ATM SAR CHIP

DESCRIPTION

The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor, network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions of the AAL-5 SAR sublayer and ATM layer.

The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software.

Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your system.

PD98401A User’s Manual: S12054E

µµµµ

FEATURES

• Conforms to ATM Forum

• AAL-5 SAR sublayer and ATM layer functions

• Hardware support of AAL-5 processing

• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function

• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic

• Supports up to 32K virtual channels (VC)

• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to

set different transmission rate for each VC

• Interface and commands for controlling PHY device

• Employs “UTOPIA interface” as cell data interface with PHY device

- Octet-level handshake

- Cell-level handshake

• 32-bit general-purpose bus interface

• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)

• JTAG boundary scan test function (IEEE1149.1)

• CMOS technology

• +5 V single power source

Remark

In this document, an active low pin is indicated by

_B (_B after a pin name).

×××

Document No. S12100EJ3V0DS00 (3rd edition) Date Published February 1999 N CP(K) Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1997©

ORDERING INFORMATION

Part Number Package

PD98401AGD-MML 208-pin plastic QFP (fine pitch) (28 × 28 mm)

SYSTEM CONFIGURATION

ATM interface card

PD98402A

Control memory

PD98401A

Bus interface

Reception

PMD

Transmission

ATM network

µµµµ

PD98401A

BLOCK DIAGRAM

System port

DMA controller and host interface

I/O bus

Receive data FIFO

Reception controller

Sequencer

Transmission controller

Transmit data FIFO

(10 cells)

PHY interface reception block

Control memory interface

PHY interface transmission block

PHY device transmission block

Control memory

PHY device reception block

Data Sheet S12100EJ3V0DS00

PIN CONFIGURATION

µµµµ

PD98401A

PHY interface

Bus interface

Rx7-Rx0 RCLK RENBL_B RSOC EMPTY_B/RxCLAV Tx7-Tx0 TCLK TENBL_B TSOC FULL_B/TxCLAV

PHRW_B PHOE_B PHCE_B PHINT_B

AD31-AD0 PAR3-PAR0 OE_B

SIZE2-SIZE0 DR/W_B ATTN_B GNT_B RDY_B ABRT_B ERR_B

SR/W_B SEL_B ASEL_B CLK RST_B INTR_B

Master

Slave Power supply

CD31-CD0

CPAR3-CPAR0

CA17-CAD

CWE_B

COE_B

CBE_B3-CBE_B0

INITD

DBVC

DBMD

DBML DBMF

DBMR

JDO

JDI

JCK

JMS

JRST_B

TRF_B

GND

Control memory interface

Bus monitoring

JTAG boundary scan interface

Test pin (fixed to low level)

Data Sheet S12100EJ3V0DS00

PIN CONFIGURATION (Top View)

µµµµ

PD98401A

208-pin plastic QFP (fine pitch) (28

VDDDBVC

DBMR

GND

VDDJRST_B

JMS

JDI

JDO

GND

VDDJCK

208

207

206

205

204

203

202

201

200

199

198

197

GND

GND AD31 AD30 AD29 AD28 AD27

GND AD26 AD25 AD24 AD23 AD22

GND

V AD21 AD20 AD19 AD18 AD17

GND AD16 AD15 AD14 AD13

GND

AD12

RST_B

GND

CLK

GND

V AD11 AD10

AD9 AD8 AD7

GND

AD6 AD5 AD4 AD3 AD2 AD1

AD0 PAR3 PAR2

GND GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

28 mm)

××××

GND

VDDDBMF

196

195

194

DBML

DBMD

193

192

GND

VDDTRF_B

191

190

189

INTID

COE_B

CWE_B

CBE_B0

CBE_B1

VDDGND

188

187

186

185

184

183

182

PD98401AGD-MML

CBE_B2

CBE_B3

CA0

181

180

179

CA1

178

CA2

177

CA3

176

GND

175

VDDCA4

174

173

CA5

172

CA6

171

CA7

170

CA8

169

CA9

168

CA10

GND

167

166

VDDCA11

CA12

165

164

163

CA13

CA14

162

161

100

CA15

CA16

160

159

101

102

CA17

158

157

103

104

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

GND GND CPAR0 CPAR1 CPAR2 CPAR3 GND CD0 CD1 CD2 CD3 CD4 CD5 CD6

V GND CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 GND

V CD16 CD17 CD18 CD19 CD20

V GND CD21 CD22 CD23 CD24 CD25 CD26 CD27 GND

V CD28 CD29 CD30 CD31 PHRW_B PHOE_B PHINT_B GND GND

GND

PAR1

PAR0

OE_B

SIZE1

SIZE0

SIZE2

GND_B

ATTN_B

DR/W_B

RDY_B

ABRT_B

SEL_B

ERR_B

SR/W_B

INTR_B

ASEL_B

GND

Rx7

Rx6

Rx5

Rx4

Rx3

GND

Data Sheet S12100EJ3V0DS00

Rx2

Rx1

Rx0

RCLK

TSOC

RSOC

RENBL_B

TENBL_B

FULL_B/TxCLAV

EMPTY_B/RxCLAV

GND

TCLK

Tx7

Tx6

Tx5

Tx4

Tx3

Tx2

Tx1

Tx0

PHCE_B

µµµµ

PD98401A

PIN NAMES

ABRT_B : Abort PHCE_B : PHY Chip Enable AD31_AD0 : Address/Data PHINT_B : PHY Interrupt ASEL_B : Slave Address Select PHOE_B : PHY Output Enable ATTN_B : Attention/Burst Frame PHRW_B : PHY Read/Write CA17-CA0 : Control Memory Address RCLK : Receive Clock CBE_B3_CBE_B0 : Local Port Byte Enable RDY_B : Target Ready CD31-CD0 : Control Memory Data RENBL_B : Receive Enable CLK : Clock RSOC : Receive Start Cell COE_B : Control Memory Output Enable RST_B : Reset CPAR3-CPAR0 : Control Memory Parity Rx7-Rx0 : Receive Data Bus CWE_B : Control Memory Write Enable SLE_B : Slave Select DBMD : DMA Bus Monitor Data SIZE2-SIZE0 : Burst Size DBMF : DMA Bus Monitor First SR/W_B : Slave Read/Write DBML : DMA Bus Monitor Last TCLK : Transmit Clock DBVC : DMA Bus Monitor VC TENBL_B : Transmit Enable DBMR : DMA Bus Monitor Remaining TSOC : Transmit Start of Cell DR/W_B : DMA Read/Write TRF_B : Delay Select EMPTY_B/RxCLAV: PHY Output Buffer Empty Tx7-Tx0 : Transmit Data Bus ERR_B : Error V FULL_B/TxCLAV : PHY Buffer Ful GND : Ground GNT_B : Grant INITD : Initialization Disable INTR_B : Interrupt JCK : JTAG Test Pin JDI : JTAG Test Pin JDO : JTAG Test Pin JMS : JTAG Test Pin JRST_B : JTAG Test Pin OE_B : Output Enable PAR3-PAR0 : Bus Parity

: Power Supply

Data Sheet S12100EJ3V0DS00

µµµµ

PD98401A

CONTENTS

1. PIN FUNCTION ..................................................................................................................................... 7

1.1 PHY Device Interface Pin ............................................................................................................. 7

1.2 Bus Interface Pins ........................................................................................................................ 9

1.3 Bus Monitor Pins........................................................................................................................ 12

1.4 Control Memory Interface Pins.................................................................................................. 13

1.5 JTAG Boundary Scan Pins........................................................................................................ 14

1.6 Test Pin........................................................................................................................................ 14

1.7 Power Supply and Ground Pins................................................................................................14

1.8 Pin Status During and After Reset............................................................................................15

2. DIFFERENCES FROM

2.1 Additional Functions..................................................................................................................16

2.2 Differences from

3. ELECTRICAL SPECIFICATIONS...................................................................................................... 17

4. PACKAGE DRAWINGS ...................................................................................................................... 33

5. RECOMMENDED SOLDERING CONDITIONS..................................................................................34

PD98401....................................................................................................16

µµµµ

PD98401 (NEASCOT-S10TM)........................................................................ 16

µµµµ

Data Sheet S12100EJ3V0DS00

1. PIN FUNCTION

µµµµ

PD98401A

The µPD98401A is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are V

and GND pins.

1.1 PHY Device Interface Pin

PHY device interfaces include a UTOPIA interface through which the µPD98401A transfers ATM cells with a PHY

device, and a PHY control interface by which the µPD98401A controls the PHY device.

(1) UTOPIA interface

Pin Name Pin No. I/ O I/O Level Function

Rx7-Rx4 Rx3-Rx0

RSOC 86 I TTL Receive Start Cell.

RENBL_B 85 O CMOS Receive Enable.

EMPTY_B/ RxCLAV

RCLK 84 O CMOS Receive Clock.

Tx7-Tx0 95 - 102 O CMOS Transmit Data Bus.

TSOC 89 O CMOS Transmit Start of Cell .

74 - 77 80 - 83

87 I TTL PHY Output Buffer Em pt y/Rx Cell Available.

I TTL Receive Data Bus.

Rx7 through Rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a PHY device. The

PD98401A loads data in at the ris i ng edge of RCLK.

The RSOC signal is input in sy nchronization with the fi rst byte of the cell data from a PHY device. This signal remains high while the first byte of the header is input t o Rx7 through Rx0.

The RENBL_B signal indicat es to a PHY device that the is ready to receive data in t he next cl ock cycle. This signal goes high during and after reset.

This signal notifies the transferred in the receive FIFO and that no receive data can be supplied to the PHY device. When the UTOPIA interface is in the octet-level handshake mode, this signal serves as EMPTY_B, indicating that the data on Rx7 t hrough Rx0 are invalid in the current clock cycle. In the cell-level handshake mode, it serves as RxCLAV, indicating that there is no cell to be supplied next after the transfer of the current cell is completed.

This is a synchroniz ation cloc k used t o transf er cell dat a with the P HY cell device at the recieve side. The system clock input to the CLK pin is output from this pi n as is, immediately after reset.

Tx7 through Tx0 constitute an 8-bit out put bus which outputs transmit data in byte format to a PHY dev ic e. The the rising edge of TCLK.

The TSOC signal is output in synchronization with the f irst byte of transmit cell data.

PD98401A that there is no cell data to be

PD98401A

PD98401A outputs data at

(1/2)

Data Sheet S12100EJ3V0DS00

Pin Name Pin No. I/ O I/O Level Function

TENBL_B 90 O CMOS Transmit Enabl e.

The TENBL_B signal indicates t o a PHY device that data has been output to Tx7 through Tx0 in the current clock cycle. This signal remains high during reset and after res et.

FULL_B/ TxCLAV

TCLK 92 O CMOS Transmit Clock.

88 I TTL PHY Buffer Full/Tx Cell Available.

The FULL_B signal notifies t he PHY device is full and t hat the device can receive no m ore data.

When the UTOPIA interface is in the octet -level handshake mode, the PHY device inputs an inact ive lev el to receiv e cell of data. I n the cell level handshake mode, this signal indicates that t he PHY device can receive all the next one cell of data after the current cell has been completely transferred

This is a synchroniz ation cloc k used t o transf er cell dat a with the P HY device at the transmission side. The system clock input to the CLK pin is output from this pi n as is.

PD98401A that the input buffer of the

µµµµ

PD98401A

(2/2)

(2) PHY device control interface

Pin Name Pin No. I/ O I/O Level Function

PHRW_B 109 O CMOS P HY Read/Write.

PD98401A indicates the direction in which the PHY device is

The

controlled, by using PHRW_B. This signal goes low aft er reset.

1: Read 0: Write

PHOE_B 108 O CMOS PHY Output Enable.

PD98401A enables output from the PHY device by making

The

PHOE_B low

PHCE_B 103 O CMOS PHY Chip Enable.

PD98401A makes PHCE_B low to access a PHY device. This

The

signal goes high after reset.

PHINT_B 107 I TTL PHY Interrupt.

This is an interrupt input signal from a PHY device. The PHY dev ice indicates to the inputting a low level to PHI NT_B. This signal goes high aft er reset.

PD98401A that it has an interrupt source, by

Data Sheet S12100EJ3V0DS00

µµµµ

PD98401A

1.2 Bus Interface Pins

The bus interface is a general-purpose bus interface compatible with most generally used I/O buses (such as PCI,

S bus, GIO, and AP bus).

Pin Name Pin No. I/ O I/O Level Function

(1/3)

AD31-AD27 AD26-AD22 AD21-AD17 AD16-AD13 AD12 AD11-AD7 AD6-AD0

PAR3 PAR2 PAR1 PAR0

OE_B 56 I TTL Output Enable.

SIZE2 SIZE1 SIZE0

3 - 7

9 - 13 16 - 20 22 - 25

28 35 - 39 42 - 48

I/O

3-state

I/O

3-state

O CMOS Burst Size.

TTL in

CMOS out

TTL in

CMOS out

Address/Data. AD31 through AD0 constitute a 32-bit address/data bus . These pins

are I/O pins multiplex ing an address bus and a data bus. At the first clock of input/out put, AD31 through AD0 transfer an address . They transfer data at the second c lock and onward. The AD bus goes into a high-impedance state when the bus.

Bus Parity. PAR pins indicate the parit y of AD31 through AD0. A parity check

mode is set by GMR. Enabl ing or disabli ng parit y, odd or ev en parit y, and word or byte parity can be specified. If byte parity is specified, PAR3 indicates the parit y of AD31 t hrough AD24, and PA R0 indic ates the parity of AD7 through AD0. If word parity is specified, PAR3 serves as an input/output pin. It serves as an output pin when an address is output and when data is written, and as an input pin when data is read.

When the go into a high-impedance state. Pull up these pi ns when they are not used.

When this pin is low, the PAR3 through PAR0 as 3-state I/O pins. Thes e pins go into a highimpedance state while a high level is being input to OE _B. This pin is an option pin. Fix this pin to low level in a system where it is not necessary to forcibly set the bus of the impedance state by controlling this pin.

SIZE2 through SIZE0 indicate the s ize of the current DMA transfer. These pins are used to interface a bus (such as S bus) requiring c lear burst size.

PD98401A does not access t he bus, PAR3 t hrough PAR0

PD98401A does not access the

PD98401A uses AD31 through AD0 and

PD98401A in a high-

SIZE2 SIZE1 SIZE0 Function

0 0 0 1-word transfer 0 0 1 2-word burst 0 1 0 4-word burst 0 1 1 8-word burst 1 0 0 16-word burst 1 0 1 12-word burst 1 1 0 Undefined 1 1 1 Reception side byte alignment

Data Sheet S12100EJ3V0DS00

Pin Name Pin No. I/ O I/O Level Function

DR/W_B 62 O CMOS DMA Read/Write.

DR/W_B indicates the direction of DMA access .

1: Read access 0: Write access

This pin is set to 1 after reset.

ATTN_B 63 O CMOS Attention/Burst Frame (DMA request).

PD98401A makes the ATTN_B signal low when it performs a

The

DMA operation. The ATTN_B signal becomes inactive at the rising edge of CLK when the data to be transferred by means of DMA has decreased to 1 word.

GNT_B 64 I TTL Grant.

The GNT_B signal inputs a low level when t he bus arbiter grants the

PD98401A use of the bus in respons e to a DMA request from the

PD98401A. The µPD98401A recognizes that it has been granted

use of the bus and starts DM A operation when the GNT_B signal goes low (active). Make sure that the GNT_B signal falls at least one system clock cycle after the rising of the ATTN_B signal. The GNT_B signal must be returned to the high (inactive) level before the

PD98401A makes the ATTN_B signal low (active) t o issue the next

DMA cycle request.

RDY_B 65 I TTL Target Ready.

RDY_B indicates to the device is ready for input/out put. During the DM A read operat ion of t he

PD98401A, the RDY_B signal i s made low if valid data is on AD31

through AD0. During the DMA write operation of the

is made low if the target dev i ce is ready for receiving dat a. The sampling timing of the RDY_B and ABRT_B signals of the

PD98401A can be advanced by one clock (early mode) by using an

internal register (GMR register).

ABRT_B 66 I TTL Abort.

ABRT_B is used to abort t he DMA transfer cycle. If this signal goes low while data is being transferred in the DMA cycle, DMA transfer is aborted in that cycle, and the ATTN_B signal is briefly deasserted inactive. After that, the again, and resumes burst transfer from the data at which the DMA transfer was aborted. While a low level is input to ABRT_B, the RDY_B signal is ignored. The user can advance the sam pling timing of the RDY_B and ABRT_B signals of the (early mode) by using an internal register (GMR regis ter). Pul l up thi s pin when it is not used.

ERR_B 67 I TTL Error.

This pin is used by a device that manages the bus to stop the operation of the on the system bus.

When a low level is input to thi s pin, the operations, sets the system bus error bit (bit 25) of the GSR register (when not masked), and generates an interrupt. Pull up this pi n when it is not used.

PD98401A in the DMA cycle that the target

PD98401A asserts the ATTN_B si gnal ac ti ve

PD98401A when occurrence of an error is det ected

µµµµ

PD98401A

PD98401A, the RDY_B signal

PD98401A by one clock

PD98401A stops all bus

(2/3)

Data Sheet S12100EJ3V0DS00

Pin Name Pin No. I/ O I/O Level Function

SR/W_B 68 I TTL Slave Read/Write.

The SR/W_B signal determines the direction in which the slave is accessed.

1: Read access 2: Write access

SEL_B 69 I TTL Slave Select.

This signal goes low (ac tive) when the slave. The SEL_B signal must goes low as soon as or after the ASEL_B signal has gone low. An inactiv e period of at least 2 system clock cycles must be inserted between when the SEL_B signal has become inactive and when it becomes active again.

ASEL_B 70 I TTL Slave Address Select.

The ASEL_B signal is us ed to selec t the direct address regist er of the

PD98401A.

When a low level is input to ASEL_B, the bus at the first ris i ng edge of CLK.

CLK 32 I T T L Clock.

This pin inputs the system clock. Input a c lock in a range of 8 to 33 MHz.

RST_B 29 I TTL Reset.

PD98401A (on starting, etc.). A fter

INTR_B 71 O Nch open-

drain output

The RST_B signal initializ es the reset, the input to RST_B, the internal state machine and registers of the

PD98401A are reset, and all 3-state signals go into a high-

impedance state. The reset input is async hronous. When this signal is input during operation, the operat ing st atus at t hat t ime i s l ost . Hol d RST_B low at least for the durat ion of one clock. Aft er reset, do not access the

Interrupt. This is an open-drain signal and must be pulled up. INTR_B informs the CPU that the interrupt bit (unmas ked) of the GSR

PD98401A can start normal operati on. When a low lev el is

PD98401A for at least 20 clock cycles.

µµµµ

PD98401A

PD98401A is accessed as a

PD98401A samples the AD

(3/3)

Data Sheet S12100EJ3V0DS00

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