NEC UPD3778CY Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3778

10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

The µPD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to

electrical signal and has the function of color separation.

µ

PD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register.

The And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners and so on.

FEATURES

• Valid photocell : 10600 pixels × 3

• Photocell's pitch : 4 µm

• Photocell size : 4 × 4 µm

• Line spacing : 48 µm (12 lines) Red line-Green line, Green line-Blue line

• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

• Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side)

1200 dpi US letter (8.5” × 11”) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate : 5 MHz MAX.

• Power supply : +12 V

• On-chip circuits : Reset feed-through level clamp circuits

Voltage amplifiers

2

ORDERING INFORMATION

Part Number Package

µ

PD3778CY CCD linear image sensor 32-pin plastic DIP (400 mil)

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S14374EJ1V0DS00 (1st edition) Date published July 1999 N CP(K) Printed in Japan

©

1999

2

V (

BLOCK DIAGRAM

Data Sheet S14374EJ1V0DS00

OUT

1

Blue)

OUT

2

Green)

OUT

3

Red)

30

31

32

φ

V

OD

GND GND

1

1629

........

D14

........

D14

........

D14

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

CCD analog shift register

D64

CCD analog shift register

D64

CCD analog shift register

(Blue)

Transfer gate

Photocell

S1

S2

(Green)

Transfer gate

Photocell

S1

S2

(Red)

Transfer gate

S10599

S10600

S10599

S10600

S10599

S10600

D65

D66

2

22

D67

φ

19

1

φ

TG1

18

(Blue)

φ

TG2

17

(Green)

φ

TG3

15

(Red)

14

φ

2

φ

3

CLB

2

φ

RB

11

φ

µ

PD3778

1

PIN CONFIGURATION (Top View)

CCD linear image sensor 32-pin plastic DIP (400 mil)

•µPD3778CY

1

φ

Reset gate clock

Reset feed-through level clamp clock

φ

RB

CLB

2

1

3

µ

PD3778

OUT

3GND

V

32

V

31

1

V

30

Output signal 3 (Red)Ground

OUT

2

Output signal 2 (Green)

OUT

1

Output signal 1 (Blue)

No connection

No connection NC

Shift register clock 1

Shift register clock 2

Transfer gate clock 3 (for Red)

Ground

φ

GND

NC

φ

TG3

4

5

6

ICInternal connection

7

ICInternal connection

8

9

10

11

1

ICInternal connection

12

ICInternal connection

13

2

14

15

16

Red

10600

Green

10600

Blue

10600

V

29

NC

28

IC

27

IC

26

NC

25

NC No connection

24

NC No connection

23

φ

22

21

IC Internal connection

20

IC Internal connection

φ

19

φ

18

φ

17

Output drain voltage

OD

No connection

Internal connection

No connection

Shift register clock 2

2

1

Shift register clock 1 Transfer gate clock 1

TG1

(for Blue) Transfer gate clock 2

TG2

(for Green)

Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.

Data Sheet S14374EJ1V0DS00

3

µ

PD3778

PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM

(Line spacing)

4 m

2 m

µ

Aluminum shield

µ

4 m

2

m

µ

Channel stopper

µ

4 m

µ

4 m

µ

Blue photocell array

Green photocell array

Red photocell array

12 lines (48 m)

µ

12 lines (48 m)

µ

4

Data Sheet S14374EJ1V0DS00

µ

PD3778

ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)

Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage V Reset gate clock voltage V Reset feed-through level clamp clock voltage V Transfer gate clock voltage V

φ

1, Vφ2 –0.3 to +8 V

φ

RB –0.3 to +8 V

φ

CLB –0.3 to +8 V

φ

TG1

to V

φ

TG3 –0.3 to +8 V

Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level V Shift register clock low level V Reset gate clock high level V Reset gate clock low level V Reset feed-through level clamp clock high level V Reset feed-through level clamp clock low level V Transfer gate clock high level V Transfer gate clock low level V Data rate f

φ

1H, Vφ2H 4.5 5.0 5.5 V

φ

1L, Vφ2L –0.3 0 +0.5 V

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

CLBH 4.5 5.0 5.5 V

φ

CLBL –0.3 0 +0.5 V

φ

TG1H

to V

φ

TG3H 4.5 V

φ

TG1L

to V

φ

TG3L –0.3 0 +0.5 V

φ

RB – 1.0 5.0 MHz

Note

φ

1H

Note

V

φ

1H

V

Note When Transfer gate clock high level (V

Image lag can increase.

Data Sheet S14374EJ1V0DS00

φ

TG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H),

5

ELECTRICAL CHARACTERISTICS

µ

PD3778

TA = +25 °C, VOD = 12 V, data rate (f

φ

RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,

light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage Vsat 2.0 2.5 – V Saturation exposure Red SER 0.694 lx•s

Green SEG 0.757 lx•s

Blue SEB 1.250 lx•s Photo response non-uniformity PRNU VOUT = 1.0 V 6 20 % Average dark signal ADS Light shielding 0.2 4.0 mV Dark signal non-uniformity DSNU Light shielding 1.5 4.0 mV Power consumption PW 400 600 mW Output impedance ZO 0.5 1 kΩ Response Red RR 2.52 3.60 4.68 V/lx•s

Green RG 2.31 3.30 4.29 V/lx•s

Blue RB 1.40 2.00 2.60 V/lx•s Image lag IL VOUT = 1.0 V 2.0 10.0 % Offset level Output fall delay time Total transfer efficiency TTE VOUT = 1.0 V, 92 98 %

Register imbalance RI VOUT = 1.0 V 0 1.0 4.0 % Response peak Red 630 nm

Dynamic range DR1 Vsat /DSNU 1666 times

Reset feed-through noise Random noise (CDS) σ CDS Light shielding – 1.0 – mV

Note1

VOS 4.0 6.0 7.0 V

Note2

Green 540 nm

Blue 460 nm

Note1

td VOUT = 1.0 V 50 ns

data rate = 5 MHz

DR2 Vsat /σ CDS 2500 times RFTN Light shielding –1000 –300 +500 mV

Notes 1. Refer to TIMING CHART 2.

2. When each fall time of

6

φ

1 and φ2 (t2, t1) is the TYP. value (refer to TIMING CHART 2).

Data Sheet S14374EJ1V0DS00

INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

Shift register clock pin capacitance 1 C

Shift register clock pin capacitance 2 C

Reset gate clock pin capacitance C Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance C

Remark Pins 11 and 19 (φ1), 14 and 22 (φ2) are each connected inside of the device.

φ

1

φ

1 11 400 pF

19 400 pF

φ

2

φ

2 14 400 pF

22 400 pF

φ

RB

C

φ

CLB

φ

TG

φ

RB 2 15 pF

φ

CLB 3 15 pF

φ

TG1 18 120 pF

φ

TG2 17 120 pF

φ

TG3 15 120 pF

µ

PD3778

Data Sheet S14374EJ1V0DS00

7

8

12345678910111213

141615

6162636465

66

10663

10664

10665

10666

10667

10668

10669

V

OUT

1 to

V

OUT

3

CLB

φ

RB

φ

2

φ

1

φ

TG1 to

φ

TG3

φ

NoteNote

Invalid photocell

(3 pixels)

Invalid photocell

(2 pixels)

Valid photocell

(10600 pixels)

Optical black

(49 pixels)

1

2

3

4

5

6

7

8

TIMING CHART 1 (for each color)

Data Sheet S14374EJ1V0DS00

Note Input the

φ

RB and

φ

CLB pulses continuously during this period, too.

µ

PD3778