The µPD31172 (commercial name: VRC4172) is a companion chip designed for NEC’s µPD30121 microprocessor
(commercial name: VR4121).
The VRC4172 has the following functions available on chip: a USB host controller, an IEEE1284 parallel controller,
a 16550 serial controller, a PS/2 controller, general-purpose ports (GPIO), programmable chip select (PCS), and a
PWM controller (a duty modulated light pulse generation function for LCD backlighting).
The VRC4172 can be directly connected to the VR4121, allowing a reduction in the man-hours required for
development of a Windows™ CE system.
Detailed function descriptions are provided in the following user’s manual. Be sure to read it before
designing.
RC
•
V
4172 User’s Manual (U14386E)
FEATURES
• Directly connectable to VR4121
• On-chip USB host controller
• USB ports: 2
• Compliant with the USB OpenHCI specifications, release 1.0
• Communicates with USB device asynchronously with host CPU
• Full-speed (12 Mbps) and low-speed (1.5 Mbps) modes supported
• System clock: 48 MHz
• On-chip PS/2 controller
• On-chip IEEE1284 parallel controller
• On-chip 16550 serial controller
• General-purpose ports (GPIO): 24
• On-chip PWM controller
• Duty modulated light pulse generation function for LCD backlighting
• Internal maximum operating frequency: 48 MHz
• Power supply voltage: VDD = 3.3 V ± 0.3 V
• Package: 208-pin plastic FBGA
TM
TM
APPLICATIONS
Battery-driven portable information devices
•
Peripheral devices for PCs, etc.
•
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14388EJ2V0DS00 (2nd edition)
Date Published May 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
ORDERING INFORMATION
Part NumberPackageInternal Maximum Operating Frequency
ACK#:AcknowledgeMRAS (0:1)#:DRAM Row Address Strobe
AD (0:24):Address BusOCI (1:2):Over Current Interrupt
ARBCLKSEL:Arbitration Clock SelectPE:Paper End
AUTOFEED#:AutofeedPPON (1:2):Port Power ON
BUSAK (0:1)#:Bus AcknowledgePS2CLK:PS2 Clock
BUSCLK:System Bus ClockPS2DATA:PS2 Data
BUSRQ (0:1)#:Bus RequestPS2INT:PS2 Interrupt
BUSY:BusyRD#:Read
CD (0:7):Centronics DataRESET:Reset
CKE:Clock EnableRI#:Ring Indicator
CLKOUT48M:Clock Out of 48 MHzROMCS (2:3)#:ROM Chip Select
CTS#:Clear to SendRTS#:Request to Send
DATA (0:31):Data BusRXD:Receive Data
DCD#:Data Carrier DetectColumn Address Strobe for
DIR1284:Direction of 1284
DN (1:2):USB D
DP (1:2):USB D+SELECT:Select
DSR#:Data Set ReadySELECTIN#:Select in
DTR#:Data Terminal ReadySMI#:USB System Interrupt
ERROR#:ErrorRow Address Strobe for
EXCS (0:5)#:External CS
GND:GroundSTROBE#:Strobe
GPIO (0:23):General Purpose I/OTXD:Transmit Data
HOLDAK#:Hold AcknowledgeUCAS#:Upper Column Address Strobe
HOLDRQ#:Hold RequestLower Byte of Upper Column
IEN:USB Input Enable
INIT#InitializeUSBINT#:USB Interrupt
INTRP:InterruptUSBRST#:USB Reset
IOCHRDY:I/O Channel ReadyUpper Byte of Upper Column
IOCS16#:IO Chip Select 16
IOR#:I/O ReadVDD:Power Supply Voltage
IOW#:I/O WriteWAKE:Wake Up Interrupt
IRQ:I/O RequestWR#:Write
LCAS#:Lower Column Address StrobeXIN48M:Clock In of 48 MHz
LCDBAK:LCD Back LightXOUT48M:Clock Out of 48 MHz
LCDCS#:LCD Chip Sel ect
LCDRDY:LCD Ready
−
SCAS#:
SDRAM
SCLK:SDRAM Clock
SRAS#:
SDRAM
ULCAS#:
Address Strobe
UUCAS#:
Address Strobe
Remark
# indicates active low.
Data Sheet U14388EJ2V0DS00
5
INTERNAL BLOCK DIAGRAM AND EXTERNAL BLOCK CONNECTION EXAMPLE
1.1Pin Function List .......................................................................................................................................8
1.2Special Status Pins .................................................................................................................................11
1.3External Processing of Pins and Drive Capacity.................................................................................. 13
1.4Recommended Connection of Unused Pins......................................................................................... 15
Signal NameI/OFunction
SCLKI/OThis i s the SDRAM operating clock .
AD (0:24)I/OThese form a 25-bit address bus.
DATA (0:31)I/OThese form a 32-bit data bus.
LCDCS#InputThis is the LCD chip sel ec t signal. This signal becomes active when the VR4121 accesses the
LCD using the AD or data bus.
RD#I/O
WR#I/O
LCDRDYOutputT hi s is the LCD ready signal. Thi s signal becomes acti ve when a state is entered whereby t he
ROMCS (2:3)#I/OThis is an SDRAM chip select signal.
CKEI/OThis is t he SDRAM clock enable si gnal .
UUCAS#I/OThi s is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins.
ULCAS#I/OThis is an SDRAM DQM signal. This signal controls the I/ O buf fers for the DATA (16:23) pins.
MRAS (0:1)#I/ OThis is an SDRAM chip select s i gnal .
UCAS#I/OThis is an S DRA M DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins.
LCAS#I/OThis is an SDRAM DQM si gnal . This signal controls t he I/O buffers for the DATA (0:7) pins.
IOR#InputThis is the system bus I/O read signal. This signal becomes active when any resource except
IOW#Input
RESETInputThis is the system bus reset signal.
IOCS16#OutputThi s is the dynamic bus-s i zing request signal.
IOCHRDYOutputT hi s is the system bus ready signal.
HOLDRQ#OutputThis is the system bus access right request signal.
HOLDAK#InputThis is the system bus access enable signal.
SRAS#I/OThis is the SDRAM RAS signal.
SCAS#I/OThis is the SDRAM CAS signal.
BUSRQ (0:1)#InputThis is a signal input f rom the external bus master requesting access to the system bus.
BUSAK (0:1)#OutputThis is a signal out put t o t he external bus master permitting access t o t he system bus.
INTRPOutputThis is an interrupt request signal from the 16550 serial controller or the I EEE1284 parallel
IRQOutputThis is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the
USBINT#OutputThis is an interrupt request signal f rom the USB host controller.
PS2INTOutputThis is an interrupt request signal from the PS/2 c ont rol l er.
BUSCLKInputThis is the system bus clock.
ARBCLKSELInputThis is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal)
Output: This signal becomes ac tive when the VRC4172 accesses SDRAM.
•
R
Input:This signal becomes ac tive when the V
•
host bridge.
Output: This signal becomes ac tive when the VRC4172 writes data to SDRAM.
•
Input: This signal becomes active when the V
•
bridge.
RC
V
4172 can acknowledge an access t o the LCD area from the VR4121.
the USB inside the V
This is the system bus I/O write signal. This signal becomes active when
the USB inside the V
controller.
IEEE1284 parallel controll er.
(1: Internal clock us ed, 0: BUSCLK used)
RC
4172 is accessed.
RC
4172 is accessed.
4121 reads data from the VRC4172’s PCI
R
4121 writes data to the VRC4172’s PCI host
any
resource except
PD31172
8
Data Sheet U14388EJ2V0DS00
µµµµ
PD31172
(2) USB Interface Signals
Signal NameI/OFunction
DP (1:2)I /OThis i s the positive data s i gnal .
DN (1:2)I/OThis is the negativ e data signal.
PPON (1:2)OutputThis is the USB route-hub-port power supply control si gnal .
OCI (1:2)InputThis is the US B route-hub-port over-current status signal. Make this s i gnal active when the
current flowing through the Vbus l i ne of the USB exceeds the ref erence value.
IENInputThis is the USB buf fer input enable signal. Make t hi s signal active when the i nput signal to the
USB port is validated.
WAKEOutputThis is a wakeup interrupt request signal .
SMI#OutputThis is a system interrupt request signal.
USBRST#InputThis is the reset signal for the USB cloc k.
(3) IEEE1284 Interface Signals
Signal NameI/OFunction
CD (0:7)I/OThese are data signals
STROBE#I/OThis is the data s t robe signal.
ACK#I/OThis i s the acknowledge signal.
BUSYI/OThis is the busy signal.
PEI/OThi s is the paper-end signal.
SELECTI/OThis is t he s el ec t signal.
AUTOFEED#I/OThis is the aut of eed signal.
SLECTIN#I/OThis is t he s el ect input signal.
ERROR#I/OThis is the fault signal.
INIT#I / OThis is the initialization signal.
DIR1284OutputThis signal outputs the transfer direction status.
(4) RS-232-C Interface Signals
Signal NameI/OFunction
RXDInputThis is the receive data signal.
CTS#I nputThis is the transmit enable signal.
DSR#InputThis is the data set ready s i gnal .
TXDOutputThi s i s the transmit data signal.
RTS#OutputThis is the transmit request signal.
DTR#OutputThis is the t erm i nal equi pm ent ready signal.
DCD#InputThis is the carrier detection signal.
RI#InputThis is the c al l di s pl ay signal.
Data Sheet U14388EJ2V0DS00
9
(5) PS/2 Interface Signals
Signal NameI/OFunction
PS2CLKI/OThis is t he PS/2 clock signal .
PS2DATAI/OThis is the PS/2 data s i gnal .
(6) General-Purpose Port Signals
Signal NameI/OFunction
GPIO (0:23)I/OThes e are general -purpose I/O signals.
(7) General-Purpose Chip Select Signals
Signal NameI/OFunction
EXCS (0:5)#OutputThese are general-purpose chip select signal s.
(8) LCD Interface Signals
Signal NameI/OFunction
LCDBAKOutputThese are signals f or controlling the LCD backlighting.
µµµµ
PD31172
(9) Clock Signals
Signal NameI/OFunction
XIN48MInputThis is the 48 MHz oscillator input pin. Connect to one side of a cryst al res onator.
XOUT48MOutputThis is the 48 MHz oscillator output pin. Connect to the ot her side of the crystal resonat or.
CLKOUT48MOutputThis is the 48 MHz cloc k output for the FIR of the VR4121.
The same specification has been made for these pins in the V
4121. If these pins have been processed in
the VR4121, there is no need to perform this processing in the VRC4172.
In full-speed mode: 50 pF, In low-speed mode: 350 pF
2.
There is no need to perform external processing if no particular external processing has been specified (−).
Data Sheet U14388EJ2V0DS00
13
Signal NameExternal ProcessingDrive CapacityTolerance
PPON (1:2)
OCI (1:2)
IEN
WAKE
SMI#
USBRST#
CD (0:7)
STROBE#Pull up40 pF3 V
ACK#Pull up40 pF3 V
BUSYPul l down40 pF3 V
PEPull down40 pF3 V
SELECTPull down40 pF3 V
AUTOFEED#Pull up40 pF3 V
SELECTIN#Pull up40 pF3 V
ERROR#Pul l up40 pF3 V
INIT#Pull up40 pF3 V
DIR1284
RXD
CTS#
DSR#
TXD
RTS#
DTR#
DCD#
RI#
PS2CLKP ul l up40 pF5 V
PS2DATAPull up40 pF5 V
GPIO (0:23)Pull up/pull down40 pF3 V
EXCS (0:5)#
LCDBAK
CLKOUT48M
−
−−
−−
−
−
−−
−
−
−−
−−
−−
−
−
−
−−
−−
−
−
−
40 pF3 V
3 V
3 V
40 pF3 V
40 pF3 V
3 V
40 pF3 V
40 pF3 V
3 V
3 V
3 V
40 pF3 V
40 pF3 V
40 pF3 V
3 V
3 V
40 pF3 V
40 pF3 V
40 pF3 V
µµµµ
PD31172
(2/2)
Remark
14
There is no need to perform external processing if no particular external processing has been specified (−).
Data Sheet U14388EJ2V0DS00
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