NEC UPD31172F1-48-FN Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD31172

VRC4172

COMPANION CHIP FOR VR4121

DESCRIPTION

The µPD31172 (commercial name: VRC4172) is a companion chip designed for NEC’s µPD30121 microprocessor

(commercial name: VR4121).

The VRC4172 has the following functions available on chip: a USB host controller, an IEEE1284 parallel controller, a 16550 serial controller, a PS/2 controller, general-purpose ports (GPIO), programmable chip select (PCS), and a PWM controller (a duty modulated light pulse generation function for LCD backlighting).

The VRC4172 can be directly connected to the VR4121, allowing a reduction in the man-hours required for development of a Windows™ CE system.

Detailed function descriptions are provided in the following user’s manual. Be sure to read it before designing.

•

4172 User’s Manual (U14386E)

FEATURES

• Directly connectable to VR4121

• On-chip USB host controller

• USB ports: 2

• Compliant with the USB OpenHCI specifications, release 1.0

• Communicates with USB device asynchronously with host CPU

• Full-speed (12 Mbps) and low-speed (1.5 Mbps) modes supported

• System clock: 48 MHz

• On-chip PS/2 controller

• On-chip IEEE1284 parallel controller

• On-chip 16550 serial controller

• General-purpose ports (GPIO): 24

• On-chip PWM controller

• Duty modulated light pulse generation function for LCD backlighting

• Internal maximum operating frequency: 48 MHz

• Power supply voltage: VDD = 3.3 V ± 0.3 V

• Package: 208-pin plastic FBGA

APPLICATIONS

Battery-driven portable information devices

•

Peripheral devices for PCs, etc.

•

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U14388EJ2V0DS00 (2nd edition) Date Published May 2000 N CP(K) Printed in Japan

The mark shows major revised points.

ORDERING INFORMATION

Part Number Package Internal Maximum Operating Frequency

PD31172F1-48-FN 208-pin plastic FBGA (15 × 15) 48 MHz

PIN CONFIGURATION

208-pin plastic FBGA (15 × 15)

•

PD31172F1-48-FN

Bottom View Top View

17 16 15 14 13 12 11 10

µµµµ

PD31172

9 8 7 6 5 4 3 2 1

ABCDEFGHJKLMNPRTU UTRPNMLKJHGFEDCBA

Index mark

Data Sheet U14388EJ2V0DS00

µµµµ

PD31172

Symbol Name Symbol Name Symbol Name Symbol Name

A1 GND C2 GND E3 CD3 J15 GND A2 AUTOFEED# C3 STROBE# E4 CD7 J16 UUCAS# A3 PE C4 ACK# E14 GND J17 ROMCS3# A4 INIT# C5 ERROR# E15 PPON1 K1 GPIO14 A5 IOCHRDY C6 AD6 E16 OCI2 K2 GPIO10 A6 AD19 C7 AD7 E17 USBRST# K3 GPIO7 A7 AD20 C8 AD8 F1 GPIO22 K4 GPIO3 A8 AD21 C9 V

F2 GPIO18 K14 EXCS3# A9 AD22 C10 AD9 F3 CD2 K15 EXCS0# A10 AD23 C11 AD10 F4 CD6 K16 SCAS# A11 AD24 C12 AD11 F14 SCLK K17 SRAS# A12 A13

Reserved Reserved

Note 1

C13 LCDBAK F15 PPON2 L1 GPIO13

C14 SMI# F16 LCAS# L2 GPIO9 A14 DP1 C15 USBINT# F17 MRAS0# L3 GPIO6 A15 DN2 C16 GND G1 GPIO21 L4 GPIO2 A16 DP2 C17 RD# G2 GPIO17 L14 EXCS4# A17 LCDRDY D1 GND G3 CD1 L15 EXCS1# B1 PS2CLK D2 SELECTIN# G4 CD5 L16 B2 V B3 V

D3 DIR1284 G14

D4 PS2INT G15

Reserved Reserved

Note 1

L17 GND M1 GPIO12

Reserved (0)

B4 BUSY D5 SELECT G16 UCAS# M2 GPIO8 B5 GND D6 AD0 G17 MRAS1# M3 GPIO5 B6 AD12 D7 AD1 H1 GPIO20 M4 GPIO1 B7 AD13 D8 AD2 H2 GPIO16 M14 EXCS5# B8 AD14 D9 GND H3 CD0 M15 EXCS2# B9 AD15 D10 AD3 H4 CD4 M16 B10 AD16 D11 AD4 H14

Reserved

Note 1

M17 CKE

Reserved (0)

B11 AD17 D12 AD5 H15 ARBCLKSEL N1 RESET B12 AD18 D13 V

H16 ULCAS# N2 BUSRQ0# B13 GND D14 IEN H17 ROMCS2# N3 GPIO4 B14 DN1 D15 WAKE J1 GPIO15 N4 GPIO0 B15 V B16 GND D17 LCDCS# J3 V

D16 OCI1 J2 GPIO11 N14 GND

N15 DSR# B17 WR# E1 GPIO23 J4 GND N16 RXD C1 PS2DATA E2 GPIO19 J14 V

N17 RI#

Note 2

Notes 1.

Remark

Either leave pins A12, A13, G14, G15, and H14 open, or input 0 V. Always input 0 V to pins L16 and M16.

# indicates active low.

Data Sheet U14388EJ2V0DS00

µµµµ

Symbol Name Symbol Name Symbol Name Symbol Name

P1 HOLDRQ# R1 HOLDAK# T1 BUSCLK U1 IOCS16# P2 BUSAK0# R2 GND T2 GND U2 IRQ P3 BUSRQ1# R3 BUSAK1# T3 V P4 GND R4 DATA23 T4 V P5 DATA31 R5 DATA22 T5 DATA15 U5 GND P6 DATA30 R6 V

T6 DATA14 U6 DATA7 P7 DATA29 R7 DATA21 T7 GND U7 DATA6 P8 DATA28 R8 DATA20 T8 DATA13 U8 DATA5 P9 V

R9 GND T9 DATA12 U9 DATA4 P10 DATA27 R10 DATA19 T10 DATA11 U10 DATA3 P11 DATA26 R11 DATA18 T11 DATA10 U11 DATA2 P12 DATA25 R12 V

T12 GND U12 DATA1 P13 DATA24 R13 DATA17 T13 DATA9 U13 DATA0 P14 CLKOUT48M R14 DATA16 T14 DATA8 U14 GND P15 DCD# R15 CTS# T15 V P16 TXD R16 GND T16 V P17 INTRP R17 XOUT48M T17 XIN48M U17 GND

U3 IOR# U4 IOW#

U15 DTR# U16 RTS#

PD31172

Remark

# indicates active low.

Data Sheet U14388EJ2V0DS00

µµµµ

PD31172

PIN IDENTIFICATION

ACK#: Acknowledge MRAS (0:1)#: DRAM Row Address Strobe AD (0:24): Address Bus OCI (1:2): Over Current Interrupt ARBCLKSEL: Arbitration Clock Select PE: Paper End AUTOFEED#: Autofeed PPON (1:2): Port Power ON BUSAK (0:1)#: Bus Acknowledge PS2CLK: PS2 Clock BUSCLK: System Bus Clock PS2DATA: PS2 Data BUSRQ (0:1)#: Bus Request PS2INT: PS2 Interrupt BUSY: Busy RD#: Read CD (0:7): Centronics Data RESET: Reset CKE: Clock Enable RI#: Ring Indicator CLKOUT48M: Clock Out of 48 MHz ROMCS (2:3)#: ROM Chip Select CTS#: Clear to Send RTS#: Request to Send DATA (0:31): Data Bus RXD: Receive Data DCD#: Data Carrier Detect Column Address Strobe for DIR1284: Direction of 1284 DN (1:2): USB D DP (1:2): USB D+ SELECT: Select DSR#: Data Set Ready SELECTIN#: Select in DTR#: Data Terminal Ready SMI#: USB System Interrupt ERROR#: Error Row Address Strobe for EXCS (0:5)#: External CS GND: Ground STROBE#: Strobe GPIO (0:23): General Purpose I/O TXD: Transmit Data HOLDAK#: Hold Acknowledge UCAS#: Upper Column Address Strobe HOLDRQ#: Hold Request Lower Byte of Upper Column IEN: USB Input Enable INIT# Initialize USBINT#: USB Interrupt INTRP: Interrupt USBRST#: USB Reset IOCHRDY: I/O Channel Ready Upper Byte of Upper Column IOCS16#: IO Chip Select 16 IOR#: I/O Read VDD: Power Supply Voltage IOW#: I/O Write WAKE: Wake Up Interrupt IRQ: I/O Request WR#: Write LCAS#: Lower Column Address Strobe XIN48M: Clock In of 48 MHz LCDBAK: LCD Back Light XOUT48M: Clock Out of 48 MHz LCDCS#: LCD Chip Sel ect LCDRDY: LCD Ready

−

SCAS#:

SDRAM

SCLK: SDRAM Clock

SRAS#:

SDRAM

ULCAS#:

Address Strobe

UUCAS#:

Address Strobe

Remark

# indicates active low.

Data Sheet U14388EJ2V0DS00

INTERNAL BLOCK DIAGRAM AND EXTERNAL BLOCK CONNECTION EXAMPLE

4172

48 MHz

DRAM controller

USB host

Internal PCI bus

controller (OpenHCI 1.0)

SDRAM

PCI bus controller

2 ports

µµµµ

PD31172

4121

System bus

IEEE1284 parallel controller

16550 serial controller

PS/2 controller

PWM controller

PCS (6 bits)

GPIO (24 bits)

PMU

ICU

. . . .

RS-232-C driver

LCD backlight

Data Sheet U14388EJ2V0DS00

µµµµ

PD31172

CONTENTS

1. PIN FUNCTIONS................................................................................................................................... 8

1.1 Pin Function List .......................................................................................................................................8

1.2 Special Status Pins .................................................................................................................................11

1.3 External Processing of Pins and Drive Capacity.................................................................................. 13

1.4 Recommended Connection of Unused Pins......................................................................................... 15

2. ELECTRICAL SPECIFICATIONS...................................................................................................... 16

3. PACKAGE DRAWING....................................................................................................................... 38

4. RECOMMENDED SOLDERING CONDITIONS................................................................................ 39

Data Sheet U14388EJ2V0DS00

µµµµ

1. PIN FUNCTIONS

1.1

Pin Function List

(1) System bus interface signals

Signal Name I/O Function SCLK I/O This i s the SDRAM operating clock . AD (0:24) I/O These form a 25-bit address bus. DATA (0:31) I/O These form a 32-bit data bus. LCDCS# Input This is the LCD chip sel ec t signal. This signal becomes active when the VR4121 accesses the

LCD using the AD or data bus.

RD# I/O

WR# I/O

LCDRDY Output T hi s is the LCD ready signal. Thi s signal becomes acti ve when a state is entered whereby t he

ROMCS (2:3)# I/O This is an SDRAM chip select signal. CKE I/O This is t he SDRAM clock enable si gnal . UUCAS# I/O Thi s is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins. ULCAS# I/O This is an SDRAM DQM signal. This signal controls the I/ O buf fers for the DATA (16:23) pins. MRAS (0:1)# I/ O This is an SDRAM chip select s i gnal . UCAS# I/O This is an S DRA M DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins. LCAS# I/O This is an SDRAM DQM si gnal . This signal controls t he I/O buffers for the DATA (0:7) pins. IOR# Input This is the system bus I/O read signal. This signal becomes active when any resource except

IOW# Input

RESET Input This is the system bus reset signal. IOCS16# Output Thi s is the dynamic bus-s i zing request signal. IOCHRDY Output T hi s is the system bus ready signal. HOLDRQ# Output This is the system bus access right request signal. HOLDAK# Input This is the system bus access enable signal. SRAS# I/O This is the SDRAM RAS signal. SCAS# I/O This is the SDRAM CAS signal. BUSRQ (0:1)# Input This is a signal input f rom the external bus master requesting access to the system bus. BUSAK (0:1)# Output This is a signal out put t o t he external bus master permitting access t o t he system bus. INTRP Output This is an interrupt request signal from the 16550 serial controller or the I EEE1284 parallel

IRQ Output This is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the

USBINT# Output This is an interrupt request signal f rom the USB host controller. PS2INT Output This is an interrupt request signal from the PS/2 c ont rol l er. BUSCLK Input This is the system bus clock. ARBCLKSEL Input This is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal)

Output: This signal becomes ac tive when the VRC4172 accesses SDRAM.

•

Input: This signal becomes ac tive when the V

•

host bridge.

Output: This signal becomes ac tive when the VRC4172 writes data to SDRAM.

•

Input: This signal becomes active when the V

•

bridge.

4172 can acknowledge an access t o the LCD area from the VR4121.

the USB inside the V This is the system bus I/O write signal. This signal becomes active when

the USB inside the V

controller.

IEEE1284 parallel controll er.

(1: Internal clock us ed, 0: BUSCLK used)

4172 is accessed.

4121 reads data from the VRC4172’s PCI

4121 writes data to the VRC4172’s PCI host

any

resource except

PD31172

Data Sheet U14388EJ2V0DS00

µµµµ

PD31172

(2) USB Interface Signals

Signal Name I/O Function DP (1:2) I /O This i s the positive data s i gnal . DN (1:2) I/O This is the negativ e data signal. PPON (1:2) Output This is the USB route-hub-port power supply control si gnal . OCI (1:2) Input This is the US B route-hub-port over-current status signal. Make this s i gnal active when the

current flowing through the Vbus l i ne of the USB exceeds the ref erence value.

IEN Input This is the USB buf fer input enable signal. Make t hi s signal active when the i nput signal to the

USB port is validated. WAKE Output This is a wakeup interrupt request signal . SMI# Output This is a system interrupt request signal. USBRST# Input This is the reset signal for the USB cloc k.

(3) IEEE1284 Interface Signals

Signal Name I/O Function CD (0:7) I/O These are data signals STROBE# I/O This is the data s t robe signal. ACK# I/O This i s the acknowledge signal. BUSY I/O This is the busy signal. PE I/O Thi s is the paper-end signal. SELECT I/O This is t he s el ec t signal. AUTOFEED# I/O This is the aut of eed signal. SLECTIN# I/O This is t he s el ect input signal. ERROR# I/O This is the fault signal. INIT# I / O This is the initialization signal. DIR1284 Output This signal outputs the transfer direction status.

(4) RS-232-C Interface Signals

Signal Name I/O Function RXD Input This is the receive data signal. CTS# I nput This is the transmit enable signal. DSR# Input This is the data set ready s i gnal . TXD Output Thi s i s the transmit data signal. RTS# Output This is the transmit request signal. DTR# Output This is the t erm i nal equi pm ent ready signal. DCD# Input This is the carrier detection signal. RI# Input This is the c al l di s pl ay signal.

Data Sheet U14388EJ2V0DS00

(5) PS/2 Interface Signals

Signal Name I/O Function PS2CLK I/O This is t he PS/2 clock signal . PS2DATA I/O This is the PS/2 data s i gnal .

(6) General-Purpose Port Signals

Signal Name I/O Function GPIO (0:23) I/O Thes e are general -purpose I/O signals.

(7) General-Purpose Chip Select Signals

Signal Name I/O Function EXCS (0:5)# Output These are general-purpose chip select signal s.

(8) LCD Interface Signals

Signal Name I/O Function LCDBAK Output These are signals f or controlling the LCD backlighting.

µµµµ

PD31172

(9) Clock Signals

Signal Name I/O Function XIN48M Input This is the 48 MHz oscillator input pin. Connect to one side of a cryst al res onator. XOUT48M Output This is the 48 MHz oscillator output pin. Connect to the ot her side of the crystal resonat or. CLKOUT48M Output This is the 48 MHz cloc k output for the FIR of the VR4121.

Data Sheet U14388EJ2V0DS00

µµµµ

1.2 Special Status Pins

Signal Name After Res et When HOLDAK# = 1 SCLK Hi-Z Hi-Z AD (0:24) Hi-Z Hi-Z DATA (0:31) Hi-Z Hi-Z LCDCS# RD# Hi-Z Hi-Z WR# Hi-Z Hi-Z LCDRDY Hi-Z Hi-Z ROMCS (2:3)# Hi-Z Hi-Z CKE Hi-Z Hi-Z UUCAS# Hi-Z Hi-Z ULCAS# Hi-Z Hi-Z MRAS (0:1)# Hi-Z Hi-Z UCAS# Hi-Z Hi-Z LCAS# Hi-Z Hi-Z IOR# IOW# RESET IOCS16# Hi-Z Hi-Z IOCHRDY Hi-Z Hi-Z HOLDRQ# 1 1 HOLDAK# SRAS# Hi-Z Hi-Z SCAS# Hi-Z Hi-Z BUSRQ (0:1)# BUSAK (0:1)# 1 Normal operation INTRP 0 Normal operation IRQ 0 Normal operation USBINT# 1 Normal operation PS2INT 0 Normal operation BUSCLK ARBCLKSEL DP (1:2) 1 Normal operation DN (1:2) 0 Normal operation PPON (1:2) 0 Normal operation OCI (1:2) IEN WAKE 0 Normal operati on

−−

PD31172

(1/2)

Remark

0: Low level, 1: High level, Hi-Z: High impedance

Data Sheet U14388EJ2V0DS00

Signal Name After Res et When HOLDAK# = 1 SMI# 1 Normal operation USBRST# CD (0:7) Hi-Z Normal operation STROBE# Hi-Z Normal operation ACK# Hi-Z Normal operation BUSY Hi-Z Normal operation PE Hi-Z Normal operation SELECT Hi-Z Normal operation AUTOFEED# Hi-Z Normal operation SELECTIN# Hi-Z Normal operation ERROR# Hi-Z Normal operation INIT# Hi-Z Normal operation DIR1284 0 Normal operation RXD CTS# DSR# TXD 1 Normal operation RTS# 1 Normal operati on DTR# 1 Normal operation DCD# RI# PS2CLK 0 Normal operation PS2DATA Hi-Z Normal operation GPIO (0:23) Hi-Z Normal operation EXCS (0:5)# 1 Normal operation LCDBAK 0 Normal operation CLKOUT48M 1 Normal operation

−−

µµµµ

PD31172

(2/2)

Remark

0: Low level, 1: High level, Hi-Z: High impedance

Data Sheet U14388EJ2V0DS00

1.3 External Processing of Pins and Drive Capacity

µµµµ

PD31172

When using the V

4172, process the pins externally, as shown in the table below.

Signal Name External Processing Drive Capacity Tolerance SCLK AD (0:24) DATA (0:31)

−

LCDCS# Pull up RD# WR#

Pull up Pull up

Note 1

80 pF 3 V 80 pF 3 V 80 pF 3 V

−

3 V 80 pF 3 V 80 pF 3 V

LCDRDY Pull up 40 pF 3 V ROMCS (2:3)# Pull up 80 pF 3 V CKE Pull down 80 pF 3 V

Note 1

UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET

Pull up Pull up Pull up Pull up Pull up Pull up Pull up

Note 1

80 pF 3 V 80 pF 3 V 80 pF 3 V 80 pF 3 V 80 pF 3 V

−

−−

3 V

IOCS16# Pull up 40 pF 3 V IOCHRDY Pull up 40 pF 3 V HOLDRQ#

−

HOLDAK# Pull up SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# PS2INT BUSCLK ARBCLKSEL DP (1:2) DN (1:2)

Pull up Pull up

−−

−

−−

−

Note 1

40 pF 3 V

−

80 pF 3 V 80 pF 3 V

40 pF 3 V 40 pF 3 V 40 pF 3 V 40 pF 3 V 40 pF 3 V

Note 2 Note 2

3 V

5 V

(1/2)

Notes 1.

Remark

The same specification has been made for these pins in the V

4121. If these pins have been processed in the VR4121, there is no need to perform this processing in the VRC4172. In full-speed mode: 50 pF, In low-speed mode: 350 pF

There is no need to perform external processing if no particular external processing has been specified (−).

Data Sheet U14388EJ2V0DS00

Signal Name External Processing Drive Capacity Tolerance PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# CD (0:7) STROBE# Pull up 40 pF 3 V ACK# Pull up 40 pF 3 V BUSY Pul l down 40 pF 3 V PE Pull down 40 pF 3 V SELECT Pull down 40 pF 3 V AUTOFEED# Pull up 40 pF 3 V SELECTIN# Pull up 40 pF 3 V ERROR# Pul l up 40 pF 3 V INIT# Pull up 40 pF 3 V DIR1284 RXD CTS# DSR# TXD RTS# DTR# DCD# RI# PS2CLK P ul l up 40 pF 5 V PS2DATA Pull up 40 pF 5 V GPIO (0:23) Pull up/pull down 40 pF 3 V EXCS (0:5)# LCDBAK CLKOUT48M

−

−−

−

−−

−

−−

−

−−

−

40 pF 3 V

3 V

3 V 40 pF 3 V 40 pF 3 V

3 V 40 pF 3 V

40 pF 3 V

3 V

3 V 40 pF 3 V 40 pF 3 V 40 pF 3 V

3 V

40 pF 3 V 40 pF 3 V 40 pF 3 V

µµµµ

PD31172

(2/2)

Remark

There is no need to perform external processing if no particular external processing has been specified (−).

Data Sheet U14388EJ2V0DS00

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