DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD3747
7400 PIXELS CCD LINEAR IMAGE SENSOR
The µ PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The
PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the
µ
photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
• Valid photocell : 7400 pixels
m
• Photocell pitch : 4.7
• Photocell size : 4.7 × 4.7 µ m
• Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
• Data rate : 44 MHz MAX. (22 MHz/1 output)
• Output type : 2 outputs in phase
• High sensitivity : 19.0 V/lx•s TYP. (Light source: Daylight color fluorescent lamp)
• Low image lag : 1 % MAX.
• Power supply : +12 V
• Drive clock level : CMOS output under 5 V operation
• On-chip circuits : Reset feed-through level clamp cir cuit s
: Voltage amplifiers
ORDERING INFORMATION
Part Number Package
PD3747D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
µ
µ
2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14892EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP (K)
Printed in Japan
©
2000
2
BLOCK DIAGRAM
φ
GND
GND
φ
φ
φ
CP
2L
2
1
· · ·· · ·
D135
13141820
10954
φ
D140
2
12
φ
TG
1121
V
OUT
2 (Even)
Data Sheet S14892EJ1V0DS00
OUT
1 (Odd)
V
22
CCD analog shift register
Transfer gate
Photocell
S2
D33
1
2
φ
OD
V
φ
R
2L
S1
D134
Transfer gate
CCD analog shift register
S7399
S7400
φ
1
µµ
µ
µ
PD3747
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
• µ PD3747D
V
OUT
1
Output signal 1 (Odd)
1
22
µµµµ
PD3747
V
OUT
2
Output signal 2 (Even)
Output drain voltage
No connection
Reset gate clock
Last stage shift register clock 2
No connection
Shift register clock 1
Ground
V
NC
φ
φ
2L
NCNo connection
NCNo connection
NC
φ
φ
GND
OD
R
1
2
PHOTOCELL STRUCTURE DIAGRAM
10
11
2
3
4
5
6
7
8
9
21
20
19
18
17
16
15
14
13
12
GND
φ
CP
NC
φ
2L
NC
NC
NC
φ
2
φ
1
φ
TG
Ground
Reset feed-through level clamp clock
No connection
Last stage shift register clock 2
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1Shift register clock 2
Transfer gate clock
m
µ
4.7
m1.5
µ
3.2
µ
m
Aluminum
shield
Data Sheet S14892EJ1V0DS00
Channel stopper
3
µµµµ
PD3747
ABSOLUTE MAXIMUM RATINGS (TA = +25
C)
°°°°
Parameter Symbol Ratings Unit
Output drain voltage V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V
Operating ambient temperature T
Storage temperature T
OD
, V
, V
1
2
φ
R
φ
CP
φ
TG
φ
A
stg
2L
φ
φ
−0.3 to +14 V
−0.3 to +8 V
−0.3 to +8 V
−0.3 to +8 V
−0.3 to +8 V
−25 to +55 °C
−40 to +100 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level V
Reset feed-through level clamp clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Data rate 2f
OD
, V
1H
2H
φ
φ
, V
1L
2L
φ
φ
RH
φ
RL
φ
CPH
φ
CPL
φ
TGH
φ
TGL
φ
R
φ
, V
, V
C)
°°°°
11.4 12.0 12.6 V
2LH
φ
2LL
φ
4.5 5.0 5.5 V
−0.3 0 +0.5 V
4.5 5.0 5.5 V
−0.3 0 +0.5 V
4.5 5.0 5.5 V
−0.3 0 +0.5 V
4.5 5.0 5.5 V
−0.3 0 +0.5 V
1244MHz
4
Data Sheet S14892EJ1V0DS00
ELECTRICAL CHARACTERISTICS
µµµµ
PD3747
TA = +25°C, VOD = 12 V, f
= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V
φ
R
p-p
,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol Test Conditions MIN. T YP. MAX. Unit
Saturation voltage V
sat
Saturation exposure SE Daylight color fluorescent lamp − 0.10 − lx•s
Photo response non-uniformity PRNU V
= 500 mV − 510%
OUT
Average dark signal ADS Light shielding − 0.5 3.0 mV
Dark signal non-uniformity DSNU Light shielding − 8.0 14.0 mV
Power consumption P
Output impedance Z
Response R
Image lag IL V
Offset level
Output fall delay time
Note 1
Note 2
Register imbalance RI V
Total transfer efficie n c y TTE V
W
O
F
V
OS
t
d
Daylight color fluorescent lamp 13.3 19.0 24.7 V/lx•s
= 500 mV − 0.5 1.0 %
OUT
V
= 500 mV − 14 − ns
OUT
= 500 mV 0 1.0 4.0 %
OUT
= 1 V, data rate = 44 MHz 94 98 − %
OUT
Response peak − 550 − nm
Reset feed-through noise
Random noise
Shot noise
Note 1
DR1 V
DR2 V
RFTN Light shielding −300 +300 +900 mV
bit Light shielding, bit clamp mode − 2.0 − mV
σ
line Light shielding, line clamp mode − 8.0 − mV
σ
shot V
σ
/DSNU − 250 − timesDynamic range
sat
/σ bit − 1000 − times
sat
= 500 mV, bit clamp mode − 8.0 − mV
OUT
1.5 2.0 − V
− 350 600 mW
− 0.2 0.3 kΩ
3.7 4.7 5.7 V
Notes 1. Refer to TIMING CHART 2, 3.
2. When the fall time of
2L (t2’) is the TYP. value (refer to TIMING CHART 2, 3). Note that V
φ
the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
OUT
1 and V
OUT
2 are
Data Sheet S14892EJ1V0DS00
5
µµµµ
PD3747
INPUT PIN CAPACITANCE (TA = +25
C, VOD = 12 V)
°°°°
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
Shift register clock pin capacitance 2 C
Last stage shift register clock pin capacitance C
Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance C
Transfer gate clock pin capacitance C
1
φ
19− 250 300 pF
φ
13 − 250 300 pF
2
φ
210− 250 300 pF
φ
14 − 250 300 pF
L
φ
2L 5 − 10 20 pF
φ
18 − 10 20 pF
R
φ
CP
φ
TG
φ
R4− 10 20 pF
φ
CP 20 − 10 20 pF
φ
TG 12 − 100 150 pF
φ
6
Data Sheet S14892EJ1V0DS00
TIMING CHART 1
φ
TG
1
φ
2
φ
φ
2L
φ
Data Sheet S14892EJ1V0DS00
(Bit clamp mode)
(Line clamp mode)
R
φ
CP
φ
CP
NoteNote
1
3
V
OUT
1
V
OUT
2
Note Set the R and CP to low level during this period.
φφ
2
5
4
6
29
30
31
32
35
33
36
34
Optical black
(96 pixels)
125
127
126
128
Invalid photocell
129
131
130
132
(6 pixels)
133
135
134
136
Valid photocell
137
138
(7400 pixels)
7531
7533
7532
7534
Invalid photocell
7537
7535
7538
7536
(6 pixels)
7539
7540
7541
7542
µµ
µ
µ
PD3747
7
TIMING CHART 2 (Bit clamp mode)
µµµµ
PD3747
φ
OUT1, 2
V
t1
90%
φ
1
10%
90%
φ
2
10%
t1'
φ
CP
2L
90%
10%
t5
t4
t3
t6
90%
R
10%
t8t7t9
90%
10%
φ
t2
t2'
t11t10
+
t
d
RFTN
RFTN
10%
−
Symbol MIN. TYP. MAX. Unit
t1, t2 0 50 − ns
t1’, t2’ 05− ns
t3 10 125 − ns
t4, t5 0 5 − ns
t6 0 125 − ns
t7 5 125 − ns
t8, t9 0 5 − ns
t10 t3 125 − ns
t11 0 250 − ns
OS
V
8
Data Sheet S14892EJ1V0DS00
TIMING CHART 3 (Line clamp mode)
µµµµ
PD3747
φ
V
OUT1, 2
t1
90%
φ
1
10%
90%
φ
2
10%
t1'
90%
φ
2L
10%
t5
t4
φ
CP
t3
90%
R
10%
"L"
t12
t2'
t2
+
t
d
RFTN
RFTN
10%
−
Symbol MIN. TYP. MAX. Unit
t1, t2 0 50 − ns
t1’, t2’ 05− ns
t3 10 125 − ns
t4, t5 0 5 − ns
t12 5 250 − ns
OS
V
Data Sheet S14892EJ1V0DS00
9
TIMING CHART 4 (Bit clamp mode, Line clamp mode)
µµµµ
PD3747
Note Set the
t14
TG
φ
90%
1
φ
2L
φ2,φ
φ
R
φ
CP
R and φ CP to low level during this period.
φ
90%
10%
t16
t13
Note
t15
90%
10%
t5
t4
t3
t6t17
t9
t8
t7
90%
10%
t11t10
1,
2 cross points
φ
φ
φ
φ
φ φ
φ φ
φ
1
φ
2
Symbol MIN. TYP. MAX. Unit
t3 10 125 − ns
t4, t5 0 5 − ns
t6 0 125 − ns
t7 5 125 − ns
t8, t9 0 5 − ns
t10 t3 125 − ns
t11 0 250 − ns
t13 1000 1500 − ns
t14, t15 0 50 − ns
t16, t17 200 300 − ns
1,
2L cross points
φ
φ
φ
φ
φ φ
φ φ
φ
1
2 V or more 2 V or more
φ
2L
2 V or more
0.5 V or more
Remark Adjust cross points of (
10
1, φ 2) and (φ 1, φ 2L) with input resistance of each pin.
φ
Data Sheet S14892EJ1V0DS00
DEFINITIONS OF CHARACTERISTIC ITEMS
µµµµ
PD3747
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula.
PRNU (%) =
∆x
× 100
x
∆x: maximum of x
x =
x
j
− x
7400
x
j
Σ
j = 1
7400
j
: Output voltage of valid pixel number j
OUT
V
Register dark
DC level
∆x
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7400
d
j
Σ
ADS (mV) =
j = 1
7400
d
j
: Dark signal of valid pixel number j
Data Sheet S14892EJ1V0DS00
11
µµµµ
PD3747
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV): maximum of d
− ADS
j = 1 to 7400
j
dj: Dark signal of valid pixel number j
OUT
V
ADS
Register dark
DC level
DSNU
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Respo nse : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
TG
φ
IL (%) =
Light
V
OUT
V
VOUT
1
× 100
ON OFF
VOUT
V1
9. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
(V
12
RI (%) =
2j – 1 – V2j
∑
n
j = 1
1
∑
n
j = 1
)
n
V
j
× 100
n
: Number of valid pixels
j
V
: Output voltage of each pixel
Data Sheet S14892EJ1V0DS00
µµµµ
10. Random noise : σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines)
data sampling at dark (light shielding).
PD3747
100
Σ
σ
(mV) =
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
11. Shot noise :
Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data
sampling in the light. This includes the random noise.
The formula is the same with that of random noise.
i = 1
σσσσ
shot
2
(Vi – V)
100 100
, V =
Vi : A valid pixel output signal among all of the valid pixels
V
OUT
100
1
V
i
Σ
i = 1
V1
V2
…
V100
line 1
line 2
…
line 100
Data Sheet S14892EJ1V0DS00
13
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
4
2
1
0.5
Relative Output Voltage
0.25
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
2
1
Relative Output Voltage
0.2
A
= +25°C)
µµµµ
PD3747
0.1
01020304050
Operating Ambient Temperature TA (°C)
SPECTRAL RESPONSE CHARACTERISTIC (TA = +25°C)
100
80
60
40
Response Ratio (%)
20
0.1
5101
Storage Time (ms)
14
0
1200600400 1000800
Wavelength (nm)
Data Sheet S14892EJ1V0DS00
APPLICATION CIRCUIT EXAMPLE
µµµµ
PD3747
φ
R
φ
2L
φ
1
φ
2
µ
10 F/16 V
+
µ
0.1 F
+12 V+5 V
µ
0.1 F
122
B1 V
+
µ
F/25 V
47
47
Ω
47
Ω
2 Ω
2 Ω
10
11
V
2
3
NC
4
φ
5
φ
6
NC
7
NC
8
NC
9
φ
φ
GND
OUT
OD
R
2L
1
2
PD3747
µ
1
GNDV
φ
φ
OUT
φ
CP
NC
2L
NC
NC
NC
φ
φ
TG
+5 V
+
µ
0.1 F
21
20
19
18
17
16
15
14
13
12
B2
47 Ω
47 Ω
2 Ω
2 Ω
10 Ω
2
2
1
µ
10 F/16 V
φ
φ
φ
φ
φ
CP
2L
2
1
TG
Remarks 1. It is recommended that pins 5 and 18 (
14 (
2).
φ
2. The inverters shown in the above application circuit example are the 74AC04.
B1, B2 EQUIVALENT CIRCUIT
4.7 kΩ
CCD
V
OUT
47 Ω
Data Sheet S14892EJ1V0DS00
2L) are separately driven a driver other than that of pins 10,
φ
+12 V
+
110 Ω
2SA1005
2SC945
1 kΩ
µ
47 F/25V
15
µµµµ
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400))
(Unit : mm)
The 1st valid pixel
PD3747
3.2
0.3
±
1.02±0.15
0.46±0.06
1
42.2±0.25
48.6±0.5
25.4
2.54
(5.37)
4.68±0.5
9.65±0.3
1.60±0.25
4.33±0.5
0~10°
10.16
2.38
(1.95)
0.3
±
3
2
0.25±0.05
16
Name Refractive index
Glass cap
1 1st valid pixel Center of pin 1
2 Photosensitive surface of CCD chip Bottom of package
3 Photosensitive surface of CCD chip Top of glass cap
Data Sheet S14892EJ1V0DS00
Dimensions
47.5×9.25×0.7
1.5
22D-1CCD-PKG10
µµµµ
PD3747
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices .
For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (C10535E).
Type of Through-hole Device
µµµµ
PD3747D : CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
Process Conditions
Partial heating method Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin)
Data Sheet S14892EJ1V0DS00
17
[MEMO]
µµµµ
PD3747
18
Data Sheet S14892EJ1V0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
µµµµ
PD3747
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14892EJ1V0DS00
19
µµµµ
PD3747
•
The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
•
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
•
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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