DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3728
7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3728 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
µ
PD3728 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
The
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell : 7300 pixels × 3
• Photocell's pitch : 10 µm
• Line spacing : 40 µm (4 lines) Red line-Green line, Green line-Blue line
7
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10
• Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 40 MHz MAX. (20 MHz/1 output)
• Output type : 2 outputs in phase/color
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
lx•hour)
ORDERING INFORMATION
Part Number Package
µ
PD3728D CCD linear image sensor 36-pin ceramic DIP (600 mil)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S13878EJ1V0DS00(1st edition)
Date published April 1999 N CP(K)
Printed in Japan
©
1999
BLOCK DIAGRAM
20
φ
CLB 1L GND
30
φφφ
29
φ
28
16
23
24
µ
PD3728
21
GND
V
OUT
2
(Blue, even)
GND
V
OUT
1
(Blue, odd)
GND
OUT
3
V
(Green, odd)
V
OUT
4
(Green, even)
GND
OUT
6
V
(Red, even)
GND
V
OUT
5
(Red, odd)
31
32
CCD analog shift register
Transfer gate
33
. . . . . . . . . .
D27
D128
S1
Photocell
S2
(Blue)
Transfer gate
34
CCD analog shift register
35
36
CCD analog shift register
Transfer gate
. . . . . . . . . .
D27
D128
S1
Photocell
S2
(Green)
Transfer gate
1
CCD analog shift register
2
3
CCD analog shift register
Transfer gate
4
. . . . . . . . . .
D27
D128
S1
Photocell
S2
(Red)
Transfer gate
5
CCD analog shift register
S7300
S7299
S7300
S7299
S7300
S7299
D129
D129
D129
D134
D134
D134
TG1
φ
22
(Blue)
TG2
φ
21
(Green)
φ
TG3
15
(Red)
GND
2
6
8
7
OD
V
RB
9
φ
10
DATA SHEET S13878EJ1V0DS00
13 14
φφφ
12
PIN CONFIGURATION (Top View)
Blue photocell array
10 m
µ
Green photocell array
10 m
µ
Red photocell array
10 m
µ
4 lines
(40 m)
µ
4 lines
(40 m)
µ
CCD linear image sensor 36-pin ceramic DIP (600 mil)
•µPD3728D
V
1
OUT
Output signal 4 (Green, even)
4
36
V
Output signal 3 (Green, odd)
OUT
3
µ
PD3728
Ground
Output signal 6 (Red, even)
Ground
Output signal 5 (Red, odd)
Ground
Output drain voltage
Reset gate clock
Shift register clock 10
No connection
No connection
No connection
Shift register clock 1
Shift register clock 2
Transfer gate clock 3 (for Red)
GND
V
GND
V
GND
φ
φ
OUT
OUT
V
OD
RB
φ
10
NC
NC
NC
φ
φ
TG3
2
1
1
Red
1
Blue
Green
3
6
4
5
5
6
7
8
9
10
11
12
1
13
2
14
15
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
V
OUT
GND
V
OUT
GND
φ
CLB
φ
1L
φ
20
NC
NC
NC
2
φ
1
φ
φ
TG1
Output signal 1 (Blue, odd)
1
Ground
Output signal 2 (Blue, even)
2
Ground
Reset feed-through level
clamp clock
Last stage shift register clock 1
Shift register clock 20
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 1 (for Blue)
Ground
Ground
No connection
No connection
GND
NC
NC
16
17
18
7300
7300
7300
21
20
19
φ
Transfer gate clock 2 (for Green)
TG2
No connection
NC
No connection
NC
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
3
m
µ
Channel stopper
DATA SHEET S13878EJ1V0DS00
Aluminum
shield
7 m
µ
µ
10 m
3
µ
PD3728
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V
φ
1, Vφ1L, Vφ10, Vφ2, Vφ20 –0.3 to +15 V
φ
RB –0.3 to +15 V
φ
CLB –0.3 to +15 V
φ
TG1
to V
φ
TG3 –0.3 to +15 V
Operating ambient temperature TA –25 to +60 °C
Storage temperature Tstg –40 to +100 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level V
Reset feed-through level clamp clock low level V
Transfer gate clock high level
Note
Transfer gate clock low level V
Data rate 2f
φ
1H, Vφ1LH, Vφ10H, Vφ2H, Vφ20H 4.5 5.0 5.5 V
φ
1L, Vφ1LL, Vφ10L, Vφ2L, Vφ20L –0.3 0 +0.5 V
φ
RBH 4.5 5.0 5.5 V
φ
RBL –0.3 0 +0.5 V
φ
CLBH 4.5 5.0 5.5 V
φ
CLBL –0.3 0 +0.5 V
V
φ
TG1H
to V
φ
TG3H 4.5 Vφ1H Vφ1H V
φ
TG1L
to V
φ
TG3L –0.3 0 +0.5 V
φ
RB – 2 40 MHz
(V
φ
10H)(Vφ10H)
Note When Transfer gate clock high level (V
Image lag can increase.
φ
Remark Pin 9 (
10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal
waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
4
φ
TG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H (Vφ10H)),
DATA SHEET S13878EJ1V0DS00
ELECTRICAL CHARACTERISTICS
µ
PD3728
TA = +25 °C, VOD = 12 V, f
φ
RB = 1 MHz, data rate = 2 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 1.5 2.0 – V
Saturation exposure Red SER 0.35 lx•s
Green SEG 0.39 lx•s
Blue SEB 0.31 lx•s
Photo response non-uniformity PRNU VOUT = 1 V 6 18 %
Note 1
Note 1
Note 1
Note 1
Green RG 3.6 5.1 6.6 V/lx•s
Blue RB 4.5 6.4 8.3 V/lx•s
Note 3
Green 540 nm
Blue 460 nm
Note 2
ADS1 Light shielding 1.0 5.0 mV
ADS2 0.5 5.0 mV
DSNU1 Light shielding 2.0 5.0 mV
DSNU2 1.0 5.0 mV
IL1 VOUT = 1 V 2.0 5.0 %
IL2 1.0 5.0 %
VOS 4.0 5.0 6.0 V
td VOUT = 1 V 20 ns
data rate = 40 MHz
DR11 Vsat/DSNU1 1000 times
DR12 Vsat/DSNU2 2000 times
DR21 Vsat/σbit1 2000 times
DR22 Vsat/σbit2 4000 times
RFTN Light shielding –500 +200 +500 mV
σbit1 Light shielding, bit clamp – 1.0 – mV
σbit2 mode (t7 = 150 ns) – 0.5 – mV
σline1 Light shielding, line – 4.0 – mV
σline2 clamp mode (t19 = 3 µs) – 2.0 – mV
Average dark signal
Dark signal non-uniformity
Power consumption PW 600 800 mW
Output impedance ZO 0.3 0.5 kΩ
Response Red RR 3.9 5.6 7.3 V/lx•s
Image lag
Offset level
Output fall delay time
Register imbalance RI VOUT = 1 V 0 4.0 %
Total transfer efficiency TTE VOUT = 1 V, 95 98 %
Response peak Red 630 nm
Dynamic range
Reset feed-through noise
Random noise
Note 1
Note 2
Notes 1. ADS1, DSNU1, IL1, DR11, DR21, σbit1 and σline1 show the specification of VOUT1 and VOUT2.
ADS2, DSNU2, IL2, DR12, DR22, σbit2 and σline2 show the specification of VOUT3 to VOUT6.
2. Refer to TIMING CHART 2, 5.
φ
3. When the fall time of
1L (t2’) is the TYP. value (refer to TIMING CHART 2, 5).
DATA SHEET S13878EJ1V0DS00
5
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
Shift register clock pin capacitance 2 C
Last stage shift register clock pin capacitance C
Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance C
Transfer gate clock pin capacitance C
φ
1
φ
2
φ
L
φ
RB
φ
CLB
φ
TG
φ
1 13 350 500 pF
23 350 500 pF
φ
10 9 350 500 pF
φ
2 14 350 500 pF
24 350 500 pF
φ
20 28 350 500 pF
φ
1L 29 10 pF
φ
RB 8 10 pF
φ
CLB 30 10 pF
φ
TG1 22 100 pF
φ
TG2 21 100 pF
φ
TG3 15 100 pF
µ
PD3728
Remark Pins 13, 23 (φ1) and pin 9 (φ10) are connected each other inside of the device.
Pins 14, 24 (φ2) and pin 28 (φ20) are connected each other inside of the device.
6
DATA SHEET S13878EJ1V0DS00
TIMING CHART 1 (Bit clamp mode, for each color)
φ
TG1 to
φ
TG3
1 ( 10)
φ
φ
2 ( 20)
φ
φ
φ
1L
DATA SHEET S13878EJ1V0DS00
φ
RB
φ
CLB
OUT
1, 3, 5
V
Note Note
27
135
91113
7
1517192123
25
29
119
121
123
125
127
129
131132
7425
7427
7429
7431
7433
7435
7437
28
246
OUT
2, 4, 6
V
7
Note Input the
φ
RB and
φ
CLB pulses continuously during this period, too.
101214
8
1618202224
26
30
Optical black
(96 pixels)
120
122
124
126
Invalid photocell
(6 pixels)
128
130
Valid photocell
(7300 pixels)
7426
7428
7430
7432
Invalid photocell
(6 pixels)
7434
7436
7438
µ
PD3728
TIMING CHART 2 (Bit clamp mode, for each color)
t1 t2
µ
PD3728
1 ( 10)
φ
2 ( 20)
φ
φ
OUT
V
V
φ
φ
φ
φ
RB
CLB
1 to
OUT
1L
90 %
10 %
90 %
10 %
90 %
10 %
t1'
6
90 %
10 %
t5 t6
t3
t10
90 %
10 %
RFTN
t4
t2'
t11
t9t8
t7
t
d
V
OS
10 %
Symbol MIN. TYP. MAX. Unit
t1, t2 0 50 ns
t1’, t2’ 0 5 ns
t3 20 50 ns
t4 5 200 – ns
t5, t6 0 20 ns
t7 20 150 ns
t8, t9 0 20 ns
t10 –10
t11 –5
Note 1
Note 2
+50 – ns
+50 ns
8
DATA SHEET S13878EJ1V0DS00
Notes 1. MIN. of t10 shows that the φRB and φCLB overlap each other.
µ
PD3728
90 %
t10
φ
RB
φ
CLB
90 %
2. MIN. of t11 shows that the φ1L and φCLB overlap each other.
φ
φ
1L
CLB
t11
90 %
90 %
DATA SHEET S13878EJ1V0DS00
9
TIMING CHART 3 (Bit clamp mode, for each color)
µ
PD3728
t12 t14t13
TG1 to TG3
φ
φ
1 ( 10)
2 ( 20)
φ
φφ
φφφ
RB
φ
CLB
1L
90 %
10 %
t15
90 %
Note 1
Symbol MIN. TYP. MAX. Unit
t11 –5
t12 3000 10000 ns
t13, t14 0 50 ns
t15, t16 900 1000 ns
Note 2
+50 ns
t16
90 %
t11
90 %
Notes 1. Input the φRB and φCLB pulses continuously during this period, too.
2. MIN. of t11 shows that the φ1L and φCLB overlap each other.
90 %
t11
90 %
2 V or more 0.5 V or more
1L
φ
φ
1 (φ10), φ2 (φ20) cross points
φ
1 ( 10)
φ
2 V or more 2 V or more
φ
2 ( 20)
φ
φ
φ
1L
CLB
φ
1L, φ2 (φ20) cross points
φ
φ
2 ( 20)
Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin.
10
DATA SHEET S13878EJ1V0DS00
TIMING CHART 4 (Line clamp mode, for each color)
φ
TG1 to
φ
TG3
φφ
1 ( 10)
φφφ
2 ( 20)
1L
DATA SHEET S13878EJ1V0DS00
φ
RB
CLB
φ
Note Note
11
V
OUT
1, 3, 5
V
OUT
2, 4, 6
Note Set the
φ
RB to high level during this period.
Remark Inverse pulse of the
135
246
φ
TG1 to
91113
7
101214
8
φ
TG3 can be used as
1517192123
1618202224
25
26
φ
CLB.
27
29
28
30
Optical black
(96 pixels)
119
121
123
125
120
122
124
126
Invalid photocell
(6 pixels)
127
128
129
131132
130
Valid photocell
(7300 pixels)
7425
7427
7429
7431
7426
7428
7430
7432
Invalid photocell
(6 pixels)
7433
7434
7435
7436
7437
7438
µ
PD3728
TIMING CHART 5 (Line clamp mode, for each color)
t1 t2
µ
PD3728
φ
1( 10)
φ
φ
φφ
2( 20)
φ
φ
φ
φ
CLB
V
OUT
V
OUT
φ
1L
RB
1 to
90 %
10 %
90 %
10 %
90 %
10 %
t1'
“H”
6
90 %
10 %
t5 t6
t3
RFTN
t4
t2'
t
d
V
OS
10 %
Symbol MIN. TYP. MAX. Unit
t1, t2 0 50 ns
t1’, t2’ 0 5 ns
t3 20 50 ns
t4 5 200 – ns
t5, t6 0 20 ns
12
DATA SHEET S13878EJ1V0DS00
TIMING CHART 6 (Line clamp mode, for each color)
2 ( 20)
1 ( 10)
2 ( 20)
2 V or more 2 V or more
φφφ
φ
φ
φφ
1L
2 V or more 0.5 V or more
µ
PD3728
φ
φ
TG1 to TG3
1 ( 10)
φ
2 ( 20)
φ
φφφ
φ
φ
CLB
1L
RB
t12
90 %
10 %
t15
90 %
90 %
90 %
10 %
t20 t21
Symbol MIN. TYP. MAX. Unit
t12 3000 10000 ns
t13, t14 0 50 ns
t15, t16 900 1000 ns
t17, t18 100 1000 ns
t19 200 t12 ns
t20, t21 0 20 ns
Note
t19
t14t13
t16
t18t17
Note Set the φRB to high level during this period.
φ
Remark Inverse pulse of the
φ
1 (φ10), φ2 (φ20) cross points
TG1 to φTG3 can be used as φCLB.
φ
1L, φ2 (φ20) cross points
Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin.
DATA SHEET S13878EJ1V0DS00
13
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE
Product of intensity of illumination (I
3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
X) and storage time (s) when saturation of output voltage occurs.
µ
PD3728
PRNU (%) =
4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
ADS (mV) =
∆x
× 100
x
∆x : maximum of x
V
OUT
Register Dark
DC level
7300
d
j
Σ
j=1
7300
j
d
j
− x
7300
x
j
Σ
j=1
x =
7300
j
: Output voltage of valid pixel number j
x
∆x
: Dark signal of valid pixel number j
x
14
DATA SHEET S13878EJ1V0DS00
µ
PD3728
5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
− ADS
j = 1 to 7300
j
dj : Dark signal of valid pixel number j
V
OUT
ADS
Register Dark
DC level
DSNU
6. Output impedance: Z
O
Impedance of the output pins viewed from outside.
7. Response: R
Output voltage divided by exposure (Ix
•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
OUT
V
V
IL (%) = ×100
V
OUT
ON OFF
V
1
V
OUT
1
DATA SHEET S13878EJ1V0DS00
15
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
(V2j – 1 – V2j)
∑
n
RI (%) =
j = 1
1
∑
n
j = 1
n
V j
×100
n : Number of valid pixels
j : Output voltage of each pixel
V
10. Random noise: σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines)
data sampling at dark (light shielding).
µ
PD3728
100
(Vi – V)
σ (mV) = , V =
Σ
i=1
2
100
i: A valid pixel output signal among all of the valid pixels for each color
V
OUT
1
100
100
Σ
i=1
Vi
V
1
V
2
…
V
100
line 1V
line 2
…
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
16
DATA SHEET S13878EJ1V0DS00
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
4
2
1
0.5
Relative Output Voltage
0.25
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
2
1
Relative Output Voltage
0.2
µ
A
= +25 °C)
PD3728
0.1
100 20304050
Operating Ambient Temperature T
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
100
80
60
40
Response Ratio (%)
20
B
0.1
1510
A
(°C) Storage Time (ms)
(without infrared cut filter) (T
G
A
R
= +25 °C)
G
B
0
400 500 600 700 800
Wavelength (nm)
DATA SHEET S13878EJ1V0DS00
17
APPLICATION CIRCUIT EXAMPLE
µ
PD3728
+5 V
+
µµ
10 F/16 V 0.1 F
B4
B6
B5
47 Ω
φ
RB
2 Ω
10
11
12
2 Ω
2
φ φ
2 Ω
2 Ω
13
14
15
16
17
18
PD3728
µ
1
V
OUT
4
2
GND
3
OUT
6
4
5
OUT
5
6
GND
7
V
OD
8
φφ
RB
9
φφ
10 20
NC NC
NC
NC
1
φ
φ
2
TG3
φ φ φ
GND
NC
NC
36
V
OUT
3
35
GND
34
V
OUT
1V
33
GNDGND
32
V
OUT
2V
31
GND
30
φ
CLB
29
1L
28
27
26
NC
25
NC
24
φ
2
23
φ
1
22
TG1
21
TG2
φ
20
NC
19
NC
B3
B1
B2
47 Ω
47 Ω
2 Ω
2 Ω
2 Ω
2 Ω
2 Ω
+
47 F/25 V0.1 F
µ
µ
µµ
10 F/16 V0.1 F
10 Ω
+
φ
+12 V
+5 V
CLB
1
TG
Remarks 1. Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output
signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
2. The inverters shown in the above application circuit example are the 74AC04.
18
DATA SHEET S13878EJ1V0DS00
µ
PD3728
B1 to B6 EQUIVALENT CIRCUIT
4.7 kΩ
CCD
V
OUT
47 Ω
2SA1005
110 Ω
+12 V
2SC945
47 F/25 V
µ
+
µ
0.1 F
1 kΩ
DATA SHEET S13878EJ1V0DS00
19
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (600mil)
(Unit : mm)
94.00±0.50
1
9.5±0.9
The 1st valid pixel
(35.0)
14.99±0.3
2
(4.33)
15.24
µ
PD3728
3
1.27±0.05
0.46±0.05
88.9±0.6
1 The 1st valid pixel The center of the pin1
2 The 1st valid pixel The center of the package (Reference)
3 The surface of the chip The top of the glass cap (Reference)
4 The bottom of the package The surface of the chip
2.54
20.32
3.50±0.5
0.97±0.3
3.30±0.35
Name Dimensions Refractive index
Glass cap 93.0 × 13.6 × 1.0 1.5
(2.33)
2.0±0.3
0.25±0.05
4
20
36D-1CCD-PKG1-1
DATA SHEET S13878EJ1V0DS00
µ
PD3728
NOTES ON THE USE OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to
come off internally. Particular care should be taken when mounting the package on the circuit board.
When mounting the package, use a circuit board which will not subject the package to bending stress, or use a
socket.
Note
For this product, the reference value for the three-point bending strength
however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body
(ceramic).
Note Three-point bending strength test
Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min.
Load Load
is 30 kg. Avoid imposing a load,
70 mm 70 mm
DATA SHEET S13878EJ1V0DS00
21
[MEMO]
µ
PD3728
22
DATA SHEET S13878EJ1V0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
DD or GND with a resistor, if it is considered to have a possibility of
µ
PD3728
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
DATA SHEET S13878EJ1V0DS00
23
µ
PD3728
[MEMO]
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
Loading...