DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3739
5000 PIXELS CCD LINEAR IMAGE SENSOR
The µPD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical
signal.
The µPD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers
the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity
µ
version of the previous device, the
high-end business facsimiles.
FEATURES
• Valid photocell : 5000 pixels
• Photocell’s pitch : 7
• High sensitivity : 9.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp)
• Low image lag : 1 % MAX.
• Peak response wavelength : 550 nm (green)
• Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side)
• Data rate : 40 MHz MAX. (20 MHz/1 output)
• Output type : 2 outputs out of phase (2 outputs in phase also supported)
• Power supply : +12 V
• Drive clock level : CMOS output under 5 V operation
• On-chip circuit : Automatic
• Pin assign : Functional compatible with the µPD35H71A
PD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and
µ
m
φ
R level adjuster
ORDERING INFORMATION
Part Number Package
µ
PD3739D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
The information in this document is subject to change without notice.
Document No. S12744EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan
©
1997
COMPARISON CHART
µ
PD3739
Item
PIN CONFIGURATION Pin 1 GND DGND
Pin 2 NC TEST
Pin 4 NC VDD
Pin 11 NC VSUB
Pin 21 NC AGND
Pin 22 NC DGND
RECOMMENDED
OPERATING CONDITIONS pin external capacitor (pF)
ELECTRICAL
CHARACTERISTICS
TIMING CHART In phase outputs operating Out of phase outputs
DEFINITIONS OF
CHARACTERISTICS ITEMS
RECOMMENDED SOLDERING CONDITIONS Wave soldering is deleted —
Capacitance of reset gate clock
Data rate MIN. (MHz) 0.5 Unspecified
Saturation exposure TYP. (Ix⋅s)
Photo response TYP. 4 ±5
non-uniformity (%) MAX. 10 ±10
Average dark signal TYP. (mV)
Dark signal MIN. 0 –3
non-uniformity (mV) TYP. 4 –1, +3
MAX. 6 +6
Power consumption MAX. (mW)
Response (V/
Offset level TYP. (V) 3.5 3.0
Shift register clock pin
capacitance (pF)
Dynamic range TYP. DR1 375 500
(times) DR2 2143 Undefined
Reset feed-through MIN. 0 Unspecified
noise (mV) TYP. 400 250
Random noise TYP. (mV) 0.7 Undefined
Photo response non-uniformity
Dark signal non-uniformity Absolute value Minus and plus value
Random noise Standard deviation of signal Undefined
Ix⋅s)
Note
MIN. 7.2 4.15
TYP. 9.0 5.2
MAX. 10.8 6.25
MIN. 250 400
TYP. 350 500
MAX. 500 800
MAX. 600 500
timing is added operation only
Absolute value Minus and plus value
level distribution by scan
µ
PD3739
1000 ± 20 % Unspecified
0.17 0.29
0.3 1.0
400 Unspecified
µ
PD35H71A
Note Due to the changing of measurement conditions, and pin capacitance of each devices is almost the same.
(µPD3739: Power supply = 12 V, µPD35H71A: Power supply = 0 V)
2
BLOCK DIAGRAM
GND 1L2
1
V
OUT
2
20
Automatic R level adjuster
OUT
1
V
3
V
OD
19
φ
φφ φφ
R2
18 17
CCD analog shift register
Transfer gate
5
R1
φφ
6
2L1
D9
. . . . . .
S1
D32
CCD analog shift register
Photocell
S2
Transfer gate
22 12
14 13
S5000
D33
φφ
10
11
S4999
9
21
D34
φ
12 TG
µ
PD3739
3
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
µ
PD3739
Ground
No connection
Output signal 1
No connection
Reset gate clock 1
Last stage shift register clock 2
No connection
No connection
Shift register clock 2
Shift register clock 1
No connection
GND
122
221
NC
V
320
OUT
1
419
NC
φ
R1
518
617
φ
2L1
716
NC
815
NC
φ
21
914
φ
11
10 13
11 12
NC
NC
NC
V
OUT
2
V
OD
φ
R2
φ
1L2
NC
NC
φ
22
φ
12
φ
TG
No connection
No connection
Output signal 2
Output drain voltage
Reset gate clock 2
Last stage shift register clock 1
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock
PHOTOCELL STRUCTURE DIAGRAM
5 m
µ
Aluminum
shield
µ
7 m
2 m
µ
Channel stopper
4
µ
PD3739
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Transfer gate clock voltage V
φ
1, Vφ2 –0.3 to +15 V
φ
R1, VφR2 –0.3 to +15 V
φ
TG –0.3 to +15 V
Operating ambient temperature TA –25 to +55 ˚C
Storage temperature Tstg –40 to +100 ˚C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55 ˚C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level
Reset gate clock low level V
Capacitance of reset gate clock pin external capacitor
Transfer gate clock high level V
Transfer gate clock low level V
Data rate 2f
φ
1H, Vφ2H 4.5 5.0 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
V
φ
R1H, V
φ
R2H
Note 4.5 5.0 5.5 V
φ
R1L, VφR2L Note –0.3 0 +0.5 V
CEXT
φ
R Non-polar type 800 1000 1200 pF
φ
TGH 4.5 5.0 5.5 V
φ
TGL –0.3 0 +0.5 V
φ
R1, 2fφR2 0.5 2 40 MHz
Note Input the reset gate clocks 1 and 2 (φR1, φR2) to pins 5 and 18, respectively, via an input resistor and a capacitor.
Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies
φ
according to the IC, due to the on-chip automatic
R level adjuster. The recommended operating conditions
of reset gate clocks 1, 2 (φR1, φR2) in the table above are for signals applied to the external capacitor.
φ
Remark
1 in the above tables represents φ11, φ12 and φ1L2. φ2 represents φ21, φ22 and φ2L1.
5
µ
ELECTRICAL CHARACTERISTICS
TA = +25 ˚C, VOD = 12 V, f
light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 V
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 1.0 1.5 V
Saturation exposure SE Daylight color fluorescent lamp 0.17 lx•s
Photo response non-uniformity PRNU VOUT = 500 mV 4 10 %
Average dark signal ADS Light shielding 0.3 3.0 mV
Dark signal non-uniformity DSNU Light shielding 0 4.0 6.0 mV
Power consumption PW 200 400 mW
Output impedance ZO 0.2 0.5 kΩ
Response RF Daylight color fluorescent lamp 7.2 9.0 10.8 V/Ix·s
Response peak wavelength 550 nm
Image lag IL VOUT = 1 V 0.3 1.0 %
Offset level
Output fall delay time
Register imbalance RI VOUT = 500 mV 0 4.0 %
Total transfer efficiency TTE VOUT = 500 mV, data rate = 40 MHz 92 98 %
Dynamic range DR1 Vsat/DSNU 375 times
Reset feed-through noise
Random noise σ Light shielding — 0.7 — mV
Note 1
Note 2
φ
1 = 1 MHz, data rate = 2 MHz, storage time = 10 ms
VOS 2.0 3.5 5.0 V
td VOUT = 1 V 20 ns
DR2 Vsat/σ 2143 times
Note 1
RFTN Light shielding 0 400 600 mV
p-p
PD3739
Notes 1. Refer to TIMING CHART 2, 5.
2. Typical value when the respective fall times of φ1L2 and φ2L1 are t11’, t41’ and t2’, t32’ (refer to TIMING
CHART 2, 5). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in
APPLICATION CIRCUIT EXAMPLE.
6
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
Shift register clock pin capacitance 2 C
Last stage shift register clock pin capacitance C
Reset gate clock pin capacitance C
Transfer gate clock pin capacitance C
φ
1
φ
11 10 250 350 500 pF
φ
12 13 250 350 500 pF
φ
2
φ
21 9 250 350 500 pF
φ
22 14 250 350 500 pF
φ
L
φ
1L2 17 40 50 100 pF
φ
2L1 6 40 50 100 pF
φ
R
φ
R1 5 8 10 15 pF
φ
R2 18 8 10 15 pF
φ
TG
φ
TG 12 100 150 200 pF
µ
PD3739
7
8
TIMING CHART 1 (Out of phase operation)
φ
TG
11
φ
21
φ
2L1
φ
R1
φ
1
3
5
7
9
OUT
1
V
12
φ
22
φ
1L2
φ
11
27
29
31
33
35
5029
5031
5033
5035
5037
φ
R2
OUT
2
V
Note Input the
Note
2
4
6
8
10
12
Optical black
(22 pixels)
φ
R1 and φR2 pulses continuously during this period, too.
28
30
Invalid photocell
(2 pixels)
32
34
36
Valid photocell
(5000 pixels)
5030
5032
Invalid photocell
(2 pixels)
5034
5036
5038
µ
PD3739
TIMING CHART 2 (Out of phase operation)
V
V
φ
φ
φ
2L1
φ
OUT
11
21
R1
t7
50 %
50 %
90 %
10 %
90 %
10 %
t1’ t2’
t6
t5
t4
d
t
90 %
10 %
10 %
50 %
50 %
1
t1 t2
90 %
t3
RFTN
t7’
OS
V
10 %
t16
t17
t14
90 %
10 %
t11’ t12’
d
t
µ
PD3739
90 %
10 %
90 %
50 %
φ
12
φ
22
φ
1L2
t12
10 %
t17’
t11
50 %
50 %
t15
φ
OUT
R2
50 %
2
t13
RFTN
OS
V
90 %
10 %
10 %
9
TIMING CHART 3 (Out of phase operation)
µ
PD3739
TG
φ
11, 12, 1L2
21, 22, 2L1
φ
11, φ21 cross points
φ
11
φφφ
φφφ
50 %
t21
90 %
50 %
10 %
t24 t23 t25
φ
12, φ22 cross points
φ
12
t22
φ
21
φ
11, φ2L1 cross points
φ
11
φ
2L1
2 V or more 2 V or more
2 V or more
0.5 V or more
φ
22
φ
1L2, φ22 cross points
22
φ
φ
1L2
2 V or more 2 V or more
2 V or more
0.5 V or more
Remark Adjust cross points of (φ11, φ21), (φ12, φ22), (φ11, φ2L1) and (φ1L2, φ22) with input resistance of each pin.
Symbol MIN. TYP. MAX. Unit
t1, t2, t11, t12 0 50 ns
t1’, t2’, t11’, t12’ 0 5 ns
t3, t13 15 50 ns
t4, t14 5 20 ns
t5, t6, t15, t16 0 20 ns
t7, t7’, t17, t17’ 25 — ns
t21, t22 0 50 ns
t23 1000 2000 5000 ns
t24, t25 10 100 ns
10
TIMING CHART 4 (In phase operation)
TG
φ
11
φ
φ
21
2L1
φ
R1
φ
1
3
OUT
1
V
12
φ
22
φ
1L2
φ
5
7
9
11
27
29
31
33
35
5029
5031
5033
5035
5037
11
R2
φ
V
OUT
2
Note Input the
φ
R1 and
Note
2
4
6
8
10
12
Optical black
φ
R2 pulses continuously during this period, too.
(22 pixels)
28
30
Invalid photocell
(2 pixels)
32
34
36
Valid photocell
(5000 pixels)
5030
5032
Invalid photocell
(2 pixels)
5034
5036
5038
µ
PD3739
12
TIMING CHART 5 (In phase operation)
t37 t31 t32
11
φ
21
φ
2L1
φ
φ
R1
OUT
1
V
12
φ
φ
22
φ
1L2
R2
φ
OUT
2
V
50 %
50 %
90 %
10 %
50 %
50 %
90 %
10 %
t36
t35 t34
t47 t42
t45
t46
t44
t32’
90 %
10 %
90 %
10 %
10 %
10 %
t41’
t
d
t
d
90 %
10 %
90 %
10 %
50 %
50 %
90 %
10 %
90 %
10 %
50 %
50 %
t33
RFTN
t43
RFTN
t37’
t47’
t31’
OS
V
t41
t42’
OS
V
µ
PD3739
TIMING CHART 6 (In phase operation)
µ
PD3739
φ
TG
φ
11
φ
φ
21, 2L1
φ
12, 1L2
φ
φ
22
φ
11, φ21 cross points
φ
11
50 %
t51
90 %
50 %
10 %
t54 t53 t55
t52
φ
12, φ22 cross points
12
φ
50 %
φ
21
φ
11, φ2L1 cross points
11
φ
φ
2L1
2 V or more 2 V or more
2 V or more
0.5 V or more
22
φ
φ
1L2, φ22 cross points
φ
22
φ
1L2
2 V or more 2 V or more
2 V or more
0.5 V or more
Remark Adjust cross points of (φ11, φ21), (φ12, φ22), (φ11, φ2L1) and (φ1L2, φ22) with input resistance of each pin.
Symbol MIN. TYP. MAX. Unit
t31, t32, t41, t42 0 50 ns
t31’, t32’, t41’, t42’ 0 5 ns
t33, t43 15 50 ns
t34, t44 5 20 ns
t35, t36, t45, t46 0 20 ns
t37, t37’, t47, t47’ 25 — ns
t51, t52 0 50 ns
t53 1000 2000 5000 ns
t54, t55 10 100 ns
13
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE
Product of intensity of illumination (I
3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
X) and storage time(s) when saturation of output voltage occurs.
µ
PD3739
PRNU (%) =
4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
∆x
× 100
x
OUT
V
Register Dark
DC level
j
∆x : maximum of x
5000
2700
x
j
xj
∑
Σ
j = 1
j=1
x =
x =
5000
2700
j
: Output voltage of valid pixel number j
x
− x
∆x
x
14
ADS (mV) =
ADS (mV) =
5000
2700
∑
j = 1
Σ
j=1
5000
2700
d
j
dj
j : Dark signal of valid pixel number j
d
µ
PD3739
5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV): maximum of | d
j – ADS | j = 1 to 5000
dj: Dark signal of valid pixel number j
OUT
V
Register Dark
DC level
6. Output impedance: ZO
Impedance of the output pins viewed from outside.
7. Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
ADS
DSNU
TG
φ
Light
V
OUT
IL (%) = ×100
V
V1
OUT
ON
OFF
V1
VOUT
15
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
(V2j – 1 – V2j)
∑
n
RI (%) =
j = 1
1
∑
n
j = 1
n
×100
V j
n : Number of valid pixels
j : Output voltage of each pixel
V
10. Random noise: σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines)
data sampling at dark (light shielding).
µ
PD3739
σ (mV) =
100
∑
i=1
(Vi – V)
100
2
V
,
i : A valid pixel output signal among all of the valid pixels
V
V
OUT
100
1
=
100
∑
i=1
Vi
V
1
V
2
V
100
line 1
line 2
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
16
STANDARD CHARACTERISTIC CURVES (TA = +25 ˚C)
g
)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
4
2
1
0.5
Relative Output Voltage
0.25
2
1
Relative Output Voltage
0.2
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC
µ
PD3739
0.1
01020304050
Operating Ambient Temperature T
100
80
60
40
Response Ratio (%)
20
A
0.1
(˚C)
SPECTRAL RESPONSE CHARACTERISTIC
5101
Storage Time (ms)
0
Wavelen
th (nm
1200600400 1000800
17
APPLICATION CIRCUIT EXAMPLE (Out of phase operation)
µ
PD3739
+5 V
1
GND
NC
22
+
µµ
0.1 F 47 F/25 V
µ
PD3739
10 Ω
+12 V
+5 V
+
µ
φ
R1
φ
2
2
NC
µ
0.1 F10 F/16 V
200 Ω 200 Ω
B1
1000 pF 1000 pF
47 Ω
2 Ω
2 Ω
3
V
OUT
1
4
NC
5
φφ φ
R1
6
2L1
φφ
7
NC
8
NC
9
φ
21
10
11
φ
11
NC
TG
21
NC
20
V
OUT
2
19
V
OD
18
R2
17
1L2
16
NC
15
NC
14
φ
22
13
12
φ
12
φ
+
µµ
B2
47 Ω
2 Ω
2 Ω
2 Ω
0.1 F 10 F/16 V
R2
φ
1
φ
TG
Remarks 1. The µPD3739 can be operated leaving pin 2 (NC) unconnected, and connecting pin 4 (NC) and pin 11
µ
(NC) to a +12 V power supply (when replaces the
PD35H71A).
2. It is recommended that pins 6 (φ2L1) and 17 (φ1L2) each is separately driven a driver other than that
of pins 10, 13 (φ11, φ12) and pins 9, 14 (φ21, φ22).
3. The inverters shown in the above application circuit example are the 74AC04.
B1, B2 EQUIVALENT CIRCUIT
4.7 kΩ
CCD
V
OUT
47 Ω
2SA1005
110 Ω
+12 V
2SC945
47 F/25V
1 kΩ
µ
+
18
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22PIN CERAMIC DIP(CERDIP)(400mil)
Name Refractive index
±0.3
42.2±0.25
4.0±0.3
1bit
9.65
±
0.3
10.16
2.54
0.46±0.06
1.02±0.15
4.33±0.5
4.68±0.5
(5.27)
Glass cap
1.5
(1.95)
0 to 10°
22D-1CCD-PKG8
48.6±
0.5
47.5×9.25×0.7
1.60±0.25
25.4
0.25±0.05
2.38
(Unit : mm)
Dimensions
µ
PD3739
19
µ
PD3739
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering
processes are used, or if the soldering is performed under different conditions, please make sure to consult with our
sales offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Type of Through-hole Device
µ
PD3739D: CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
Process Conditions
Partial heating method Pin temperature: 260 ˚C or below, Heat time: 10 seconds or less (per pin).
20
[MEMO]
µ
PD3739
21
[MEMO]
µ
PD3739
22
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
µ
PD3739
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
23
µ
PD3739
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2
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