NEC UPD3777CY Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

µ

PD3777

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5400 PIXELS

The

PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical

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signal and has the function of color separati on.

The

PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And

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it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is
suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.

FEATURES

Valid photocell : 5400 pixels × 3

•

Photocell’s pitch : 5.25

•

Photocell size : 5.25 × 5.25

•

Line spacing : 42

•

Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

•

Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side)

•

m

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m (8 lines) Red line - Green line, Green line - Blue line

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3 COLOR CCD LINEAR IMAGE SENSOR

××××

2

m

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: 600 dpi US letter (8.5” × 11”) size (shorter side)

Drive clock level : CMOS output under 5 V operation

•

Data rate : 4 MHz MAX.

•

Power supply : +12 V

•

On-chip circuits : Reset feed-through level clamp circuits

•

: Clamp pulse generation circuit
: Voltage amplifiers

ORDERING INFORMATION

Part Number Package

PD3777CY CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))

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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. S14583EJ1V0DS00 (1st edition)
Date Published December 1999 NS CP (K)
Printed in Japan

©

1999

2

BLOCK DIAGRAM

φ

V

OD

19

OUT

1

V
(Blue)

Data Sheet S14583EJ1V0DS00

OUT

V
(Green)

OUT

V
(Red)

21

2

22

3

1

Clamp pulse

generator

2L

GND GND

2

1117

........

D14

........

D14

........

D14

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

CCD analog shift register

CCD analog shift register

D64

CCD analog shift register

CCD analog shift register

D64

CCD analog shift register

(Blue)

Transfer gate

Transfer gate

Photocell

S1

S2

(Green)

Transfer gate

Transfer gate

Photocell

S1

S2

(Red)

Transfer gate

S5399

S5400

S5399

S5400

S5399

S5400

D65

D65

D65

D66

D66

D66

D67

D67

D67

φ

14

1

φ

TG1

13

(Blue)

φ

TG2

12

(Green)

φ

TG3

10

(Red)

µ µ

µ

µ

PD3777

3

φ

RB

4

φ

1L

9

φ

2

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))

PD3777CY

•

µ

µ

µ

PD3777

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Output signal 3 (Red)

Ground

Reset gate clock

Last stage shift register clock 1

No connection

No connection

Shift register clock 2

Transfer gate clock 3
(for Red)

Ground

V

GND

φ

φ

GND

OUT

RB

φ

1L

NC

NCNo connection

NCNo connection

NC

φ

TG3

1

3

2

1

1

1

3

4

5

6

7

8

2

9

10

11

Red

5400

Green

5400

Blue

5400

V

22

V

21

NC No connection

20

V

19

NC

18

φ

17

NC

16

NC

15

φ

14

φ

13

φ

12

Output signal 2 (Green)

OUT

2

Output signal 1 (Blue)

OUT

1

Output drain voltage

OD

No connection

Last stage shift register clock 2

2L

No connection

No connection

Shift register clock 1

1

Transfer gate clock 1

TG1

(for Blue)
Transfer gate clock 2

TG2

(for Green)

PHOTOCELL STRUCTURE DIAGRAM

2.5

µ

2.75 m

µ

Aluminum
shield

µ

5.25 m

m

Channel stopper

PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)

5.25 m

µ

5.25 m

µ

5.25 m

µ

Data Sheet S14583EJ1V0DS00

Blue photocell array

Green photocell array

Red photocell array

8 lines

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(42 m)

8 lines

(42 m)

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3

µ

µ

PD3777

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ABSOLUTE MAXIMUM RATINGS (TA = +25

C)

°°°°

Parameter Symbol Ratings Unit
Output drain voltage V
Shift register clock voltage V
Reset gate clock voltage V
Transfer gate clock voltage V
Operating ambient temperature T
Storage temperature T

OD

φ

φ

φ

, V

φ

1L

2L

, V

φ

TG3

1

2

, V

φ

RB

φ

TG1

to V

A

stg

−

0.3 to +15 V

−

0.3 to +8 V

−

0.3 to +8 V

−

0.3 to +8 V

−

25 to +60

−

40 to +70

°

C

°

C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25

Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Data rate f

OD

φ

φ

φ

φ

φ

TG3H

TG3L

1LL

1LH

, V

, V

φ

2LH

φ

2LL

1H

2H

, V

, V

φ

φ

1L

2L

, V

, V

φ

RBH

φ

RBL

φ

TG1H

to V

φ

φ

RB

TG1L

to V

φ

C)

°°°°

11.4 12.0 12.6 V

4.5 5.0 5.5 V

−

0.3 0 +0.5 V

4.5 5.0 5.5 V

−

0.3 0 +0.5 V

4.5 V

−

0.3 0 +0.5 V

−

Note

φ

1H

Note

φ

1H

V

1.0 4.0 MHz

V

When Transfer gate clock high level (V

Note

lag can increase.

φ

TG1H

to V

TG3H

) is higher than Shift register clock high level (V

φ

1H

), Image

φ

4

Data Sheet S14583EJ1V0DS00

ELECTRICAL CHARACTERISTICS

µ

µ

PD3777

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TA = +25 °C, VOD = 12 V, data rate (f

RB

) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 V

φ

p-p

,

light source : 3200 K halogen lamp + C−500S (infrared cut filter, t = 1 mm) + HA−50 (heat absorbing filter, t = 3 mm)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage V
Saturation exposure

Red SER 0.420 lx•s

sat

2.0 2.5

Green SEG 0.429 lx•s
Blue SEB 0. 739 lx•s

Photo response non-uniformity PRNU V

OUT

= 1.0 V 6 20 %
Average dark signal ADS Light shielding 0.2 2.0 mV
Dark signal non-uniformity DSNU Light shielding 1.5 5.0 mV
Power consumption P
Output impedance Z
Response

Red R
Green R

Blue R
Image lag IL V
Offset level
Output fall delay time

Note 1

Note 2

Total transfer efficiency TTE V
Register imbalance RI V
Response peak

Red 630 nm

W

O

R

G

B

OUT

= 1.0 V 2.0 7.0 %

OS

V

d

t

OUT

V

= 1.0 V 50 ns

OUT

= 1.0 V, data rate = 4 MHz 92 98 %

OUT

= 1.0 V 0 1.0 4.0 %

4.15 5.94 7.72 V/lx•s

4.07 5.82 7.57 V/lx•s

2.36 3.38 4.39 V/lx•s

4.0 5.5 7.0 V

360 540 mW

0.5 1 k

Green 540 nm

Blue 460 nm

sat

/DSNU 1666 timesDynamic range

sat

σ

/

Light shielding

−

1000

2500 times

−

300 +500 mV

−

1.0

Reset feed-through noise
Random noise

Note 1

DR1 V
DR2 V
RFTN Light shielding

σ

−

−

V

mV

Ω

Notes 1.

Refer to
When each fall time of

2.

TIMING CHART 2

1L and

φ

.

2L (t2’, t1’) is the TYP. value (refer to

φ

Data Sheet S14583EJ1V0DS00

TIMING CHART 2

).

5

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PD3777

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INPUT PIN CAPACITANCE (TA = +25

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
Shift register clock pin capacitance 2 C

Reset gate clock pin capacitance C
Transfer gate clock pin capacitance C

C, VOD = 12 V)

°°°°

φ

1

φ

2

φ

L

φ

RB

φ

TG

φ

1 14 650 pF

φ

2 9 650 pF

φ

1L 4 10 pFLast stage shift register clock pin capacitance C

φ

2L 17 10 pF

φ

RB 3 10 pF

φ

TG1 13 60 pF

φ

TG2 12 60 pF

φ

TG3 10 60 pF

6

Data Sheet S14583EJ1V0DS00