NEC UPD3737D Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3737

5150-BIT CCD LINEAR IMAGE SENSOR

The µPD3737 is a 5150-bit high sensitivity CCD (Charge Coupled Device) linear image sensor which

changes optical images to electrical signal.

The µPD3737 has high speed CCD register, so it is suitable for high resolution scanners and facsimiles

which scan high definition document at high speed.

FEATURES

• Valid photocell 5150-bit

• Photocell's pitch 7

• High response sensitivity Providing a response 4.3 times better than the existing equivalent NEC

• Peak response wavelength 550 nm (green)

• Resolution 16 dot/mm across the shorter side of an A3-size (297 × 420 mm) sheet,

• Power supply +12 V

• Drive clock level CMOS output under 5V operation

• High speed scan 252 µs/line

• Data rate 20 MHz

µ

m

µ

product (

24 dot/mm across the shorter side of an A4-size (210 × 297 mm) sheet

PD3571) to the light from a daylight fluorescent lamp

ORDERING INFORMATION

Part Number Package Quality Grade

µ

PD3737D CCD LINEAR IMAGE SENSOR 22 PIN CERAMIC DIP (CERDIP) (400 mil) Standard

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

Document No. IC-3352
(O. D. No. IC-8925)
Date Published July 1994 P
Printed in Japan

The mark shows revised points.

©

1994

BLOCK DIAGRAM

µ

PD3737

V

OD

4

22

R

φ

18

OUT

V

2

AGND

5

AGND

1L

φ

12

14

φ

1

Optical black (OB) 18 bits, invalid photocell 2 bits,
valid photocell 5150 bits, invalid photocell 2 bits

9

2L

φ

13

10

φ

TG

φ

2

2

PIN CONFIGURATION (Top View)

CCD LINEAR IMAGE SENSOR 22 PIN CERAMIC DIP (CERDIP) (400 mil)

µ

PD3737

No connection

Analog ground

No connection

Output unit drain voltage

Analog ground

No connection

No connection

No connection

Last-stage shift register clock 2

Shift register clock 2

No connection

122

NC

221

AGND

320

NC

OD

419

V

518

AGND

617

NC

716

NC

815

NC

2L

914

φ

2

φ

10 13

11 12

NC

R

φ

NC

NC

V

OUT

NC

1

φ

TG

φ

1L

φ

Reset gate clock

No connectionNC

No connection

No connection

Output

No connectionNC

No connection

No connectionNC

Shift register clock 1

Transfer gate clock

Last-stage shift register clock 1

PHOTOELEMENT STRUCTURE DIAGRAM

5 m

µ

Aluminum
electrode

µ

7 m

2 m

µ

Channel stopper

3

ABSOLUTE MAXIMUM RATINGS (Ta = +25 °C)

Parameter Symbol Ratings Unit

Output unit drain voltage VOD –0.3 to +15 V

Shift register clock voltage V

Last-stage shift register clock voltage V

Reset signal voltage V

Transfer gate signal voltage V

φ

1, φ2 –0.3 to +15 V

φ

1L, Vφ2L –0.3 to +15 V

φ

R –0.3 to +15 V

φ

TG –0.3 to +15 V

Operating ambient temperature Topt –25 to +55 °C
Storage temperature Tstg –40 to +100 °C

RECOMMENDED OPERATING CONDITIONS (Ta = –25 to + 55 °C)

Parameter Symbol MIN. TYP. MAX. Unit

Output unit drain voltage VOD 11.4 12.0 12.6 V

µ

PD3737

Shift register clock signal high level V

Shift register clock signal low level V

Reset signal φR high level V

Reset signal φR low level V

Transfer gate signal high level V

Transfer gate signal low level V

Data rate f

φ

1H, Vφ2H, 4.5 5.0 5.5 V

V

φ

1LH, Vφ2LH

φ

1L, Vφ2L, –0.3 0 +0.5 V

V

φ

1LL, Vφ2LL

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

TGH 4.5 Vφ1H Vφ1H V

φ

TGL –0.3 0 +0.5 V

φ

R 0.5 1 20 MHz

Remark 1. Input reset signal φR to pin 22 via capacitor. Concerning the connection method refer to APPLICATION

EXAMPLE.

2. Operating conditions of reset signal φR is not the condition at device pins but the conditions of the

signal which applied to capacitor.

φ

3. When V

TGH > Vφ1H, image lag increases.

4

µ

PD3737

ELECTRICAL CHARACTERISTICS

Ta = +25 °C, VDD = 12 V, f

light source: 3200 K halogen lamp + C500 (infrared cut filter), input clock = 5 V

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Saturation voltage Vsat 1.0 1.5 V

Saturation exposure SE Daylight color fluorescent lamp 0.2 lx·s
Photo response non-uniformity PRNU VOUT = 500 mV ±5 ±10 %

Average dark signal ADS Light shielding 1.0 3.0 mV

Dark signal non-uniformity DSNU Light shielding

Power consumption PW 100 mW
Output impedance ZO 0.2 0.5 kΩ

Response RF Daylight color fluorescent lamp 6 7.5 9 V/lx·s

Response peak wavelength 550 nm

Image lag IL VOUT = 1 V 0.3 1 %

Offset level VOS 2.0 3.0 5.0 V

Input capacity of shift register clock C
pin C

Input capacity of last-stage shift C
register clock pin C

Input capacity of reset pin C

Input capacity of transfer gate clock C
pin

Output fall delay time td

Register imbalance RI VOUT = 500 mV 0 4 %

Transfer efficiency TTE VOUT = 500 mV, f

Dynamic range DR Vsat/DSNU 500 times

Reset feed-through noise RFSN Light shielding 250 500 mV

φ

1 = 0.5 MHz, data rate = 1 MHz, storage time = 10 ms

φ

1 800 pF

φ

2

φ

1L 50 pF

φ

2L

φ

R 10 pF

φ

TG 150 pF

Note

Time from 90 % to 10 % of φ2L fall 25 ns
is 5ns.

φ

R1 = 20 MHz 92 98 %

–3

P-P

+3
–1

+6

mV

Note td is defined as a time from 10 % of φ2L to 10 % of VOUT, output after passing through two steps of emitter

follower in the application example.

5