NEC UPD3734ACY Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3734A
2660 PIXELS CCD LINEAR IMAGE SENSOR
The µPD3734A is a high sensitivity CCD (Charge Coupled Device) linear image sensor which changes optical
images to electrical signal.
The µPD3734A has 2660 pixels and an output amplifier which has high gain and wide output range, but low noise.
Built-in sample and hold circuit converts and outputs independent signal from CCD register in every pixel to
continuous video signal. So it is easy to interface to A/D converter or Bi-level converter.
FEATURES
• Valid photocell : 2660 pixels
• Photocell’s pitch : 11 µm
• High sensitivity : 70 V/lx·s TYP.
• Peak response wavelength : 550 nm (green)
• Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side)
300 dpi US letter (8.5” × 11”) size (shorter side)
• Power supply : +12 V
• Drive clock level : CMOS output under 5 V operation
• High speed scan : 0.54 ms/line (S/H in used)
• Built-in circuit : Sample and hold circuit
Reset feed-through level clamp circuit
Clamp pulse generation circuit
Voltage amplifier
µ
• Low noise : A quarter of the
• Low image lag : 1 % MAX.
• Pin assign : Compatible with the
PD3734
µ
PD3734
ORDERING INFORMATION
Part Number Package
µ
PD3734ACY CCD linear image sensor 22-pin plastic DIP (400 mil)
The information in this document is subject to change without notice.
Document No. S11454EJ1V0DS00 (1st edition)
Date Published May 1996 P
Printed in Japan
©
1996
COMPARISON CHART
µ
PD3734A
Item
PIN CONFIGURATION Pin 13 No connection Digital GND
RECOMMENDED
OPERATING CONDITIONS
ELECTRICAL
CHARACTERISTICS
TIMING CHART t4 MIN. (ns) 90 150
DEFINITIONS OF Dark signal non-uniformity Absolute value Minus and plus value
CHARACTERISTICS ITEMS
Data rate MAX. (MHz)
Average dark signal MAX. (mV)
Dark signal MIN. –8
non-uniformity (mV) TYP. 4 ±4
MAX. 6 +8
Power consumption TYP. 190 170
(mW) MAX. 250 220
Image lag (%) TYP. 0.3 7
MAX. 1.0 14
Total transfer efficiency Data rate = 4 MHz Data rate = 3 MHz
(test conditions)
Reset feed-through MIN. –900 0
noise (mV) TYP. –200 1000
MAX. +500 1800
Bit noise TYP. (mVp-p) 4.5 16
Random noise (mV) 0.9 (S/H in used) No definition
t5 MIN. (ns) 70 150
t8 MIN. (ns) 20 80
Random noise Refer to DEFINITIONS OF No definition
µ
PD3734ACY
5 (S/H in used) 3 (No conditions)
4 (S/H not in used)
3.0 8.0
0.9 (S/H not in used)
CHARACTERISTICS ITEMS
11. Random noise
µ
PD3734CY-1
2
BLOCK DIAGRAM
AGND
φ
RB
10
21
V
OD
3
φ
2
14
φ
V
OUT
SHB
17
Voltage Amplifier
•
•
S/H circuit
•
Reset feed-through
level clamp circuit
Optical black (OB) 18 pixels, invalid 2 pixels,
valid photocell 2660 pixels, invalid 2 pixels
TG
φ
9
2
1
φ
15
4
AGND
µ
PD3734A
3
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (400 mil)
µ
PD3734A
No connection
Sample and hold clock
Output drain voltage
Analog GND
No connection
No connection
No connection
No connection
Transfer gate clock
Analog GND
No connection
NC
122
221
φ
SHB
V
320
OD
419
AGND
518
NC
617
NC
716
NC
815
NC
φ
TG
914
10 13
AGND
11 12
NC
NC
φ
RB
NC
NC
NC
V
OUT
NC
φ
1
φ
2
NC
NC
No connection
Reset gate clock
No connection
No connection
No connection
Output
No connection
Shift register clock 1
Shift register clock 2
No connection
No connection
PHOTOCELL STRUCTURE DIAGRAM
9 m
µ
Aluminum
electrode
µ
11 m
2 m
µ
Channel stopper
4
µ
PD3734A
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Transfer gate clock voltage V
Sample and hold clock voltage V
φ
1, Vφ2 –0.3 to +15 V
φ
RB –0.3 to +15 V
φ
TG –0.3 to +15 V
φ
SHB –0.3 to +15 V
Operating ambient temperature TA –25 to +60 ˚ C
Storage temperature Tstg –40 to +70 ˚ C
Caution Exposure to ABSOLUTE MAXIMUM RATING for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = –25 to +60 ˚C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Sample and hold clock high level V
Sample and hold clock low level V
Data rate f
φ
1H, Vφ2H 4.5 5.0 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
φ
RBH 4.5 5.0 5.5 V
φ
RBL –0.3 0 +0.5 V
φ
TGH 4.5 5.0 5.5 V
φ
TGL –0.3 0 +0.5 V
φ
SHBH 4.5 5.0 5.5 V
φ
SHBL –0.3 0 +0.5 V
φ
RB S/H in used 0.2 1 5 MHz
S/H not in used 0.2 1 4 MHz
5
µ
PD3734A
ELECTRICAL CHARACTERISTICS
TA = +25 ˚C, VOD = 12 V, f
light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 V
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 1.5 2.0 V
Saturation exposure SE Daylight color fluorescent lamp 0.029 lx•s
Photo response non-uniformity PRNU VOUT = 500 mV ±2 ±8%
Average dark signal ADS Light shielding 1.0 3.0 mV
Dark signal non-uniformity DSNU Light shielding 4 6 mV
Power consumption PW 190 250 mW
Output impedance ZO 0.5 1 kΩ
Response RF Daylight color fluorescent lamp 49 70 91 V/Ix·s
Response peak wavelength 550 nm
Image lag IL VOUT = 1 V 0.3 1.0 %
Offset level VOS 3.5 4.5 5.5 V
Input capacitance of shift register C
clock pin C
Input capacitance of reset gate clock C
pin
Input capacitance of sample and hold C
clock pin
Input capacitance of transfer gate C
clock pin
Output fall delay time td 80 ns
Register imbalance RI VOUT = 500 mV 3 %
Total transfer efficiency TTE VOUT = 1 V, data rate = 4 MHz 92 %
Dynamic range DR Vsat/DSNU 500 times
Reset feed-through noise RFSN Light shielding –900 –200 +500 mV
Sample and hold noise SHSN Light shielding, –50 0 +50 mV
Bit noise BN 4.5 mVp-p
Random noise σ S/H in used 0.9 mV
Resolution MTF Modulation transfer function at 65 %
φ
1 = 0.5 MHz, data rate = 1 MHz, storage time = 10 ms
φ
1,
φ
2
φ
RB 5pF
φ
SHB 5pF
φ
TG 100 pF
φ
SHB series resistor 47 Ω
S/H not in used 0.9 mV
nyquist frequency
p-p
400 pF
6
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