NEC UPD3725AD Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3725A
5000-BIT × 3 CCD COLOR LINEAR IMAGE SENSOR
The µPD3725A is a high sensitivity 5000-bit × 3 CCD (Charge Coupled Device) color linear image sensor which
changes optical images to electrical signal and has the function of color separation.
µ
PD3725A has 3 rows of 5000-bit photocell array and 6 rows of 2500-bit charge transferred register, so it is
The
suitable for high resolution color image scanners and digital color copiers.
FEATURES
• Valid photocell : 5000-bit × 3
µ
• Photocell's pitch : 14
• Line distance : 112 µm (8 lines) R(red) bit-G(green) bit, Gbit-B(blue)bit
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107lx•Hour)
• Resolution : 16 dot/mm across the shorter side of a B4-size (257 × 364 mm) sheet
• Drive clock level : CMOS output under 5 V operation
• Data rate : 16 MHz MAX.
• High speed scan : 320
• Power supply : +12 V
m
µ
s/line
µ
CHANGED POINTS from the
• Pins 18 and 15, 17 and 14, 11 and 8, 12 and 9 are each connected inside of the device (refer to BLOCK
DIAGRAM).
• The specification of the total transfer efficiency (TTE) is improved from 92 % to 93.5 % (MIN.) (refer to
ELECTRICAL CHARACTERISTICS).
ORDERING INFORMATION
Part Number Package
µ
PD3725AD CCD linear image sensor 24-pin ceramic DIP (600 mil)
PD3725D-01
Document No. S11324EJ1V0DS00 (1st edition)
Date Published March 1996 P
Printed in Japan
The information in this document is subject to change without notice.
©
1996
BLOCK DIAGRAM
22V
OUT
2
φ
R1B
φ
R2B
φ
1A1
φ
2A1 V
20 5 18 17 4
CCD analog shift register 2
Transfer gate
µ
PD3725A
OD
GND7
GND21
φ
TG116
OUT
OUT
OUT
OUT
OUT
1
4
(G)
3
6
(R)
5
(B)
...........
D26
S1
D127
Photocell
S2
S4999
S5000
...........
D128
D133
Transfer gate
23V
24V
D26
CCD analog shift register 1
CCD analog shift register 4
Transfer gate
...........
S1
D127
Photocell
S2
S4999
S5000
...........
D128
D133
φ
1A215
φ
2A214
φ
TG213
Transfer gate
1V
2V
D26
CCD analog shift register 3
CCD analog shift register 6
Transfer gate
...........
S1
D127
Photocell
S2
S4999
S5000
...........
D128
D133
φ
2A312
φ
1A311
φ
TG310
Transfer gate
3V
CCD analog shift register 5
6
φ
2L
19
φ
1L
φ
8
1A4
φ
9
2A4
2
PIN CONFIGURATIONS (Top View)
Signal output 3 (GREEN)
Signal output 6 (RED)
Signal output 5 (RED)
Output drain voltage
Reset clock 2
Last-stage shift register clock 2
Ground
Shift register clock 1
Shift register clock 2
Transfer gate clock 3
Shift register clock 1
Shift register clock 2
V
OUT
3
V
OUT
6
V
OUT
5
V
OD
R2B
2L
GND
1A4
2A4
TG3
1A3
2A3
φ
φ
φ
φ
φ
φ
φ
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
OUT
4
V
OUT
1
V
OUT
2
GND
R1B
1L
1A1
2A1
TG1
1A2
2A2
TG2
φ
φ
φ
φ
φ
φ
φ
φ
Signal output 4 (GREEN)
Signal output 1 (BLUE)
Signal output 2 (BLUE)
Ground
Reset clock 1
Last-stage shift register clock 1
Shift register clock 1
Shift register clock 2
Transfer gate clock 1
Shift register clock 1
Shift register clock 2
Transter gate clock 2
5000
5000
5000
R
G
B
1
1
1
12 m
µ
2 m
µ
14 m
µ
Channel stopper
Aluminium
electrode
CCD linear image sensor 24-pin ceramic DIP (600 mil)
µ
PD3725A
PHOTOCELL STRUCTURE DIAGRAM
3
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
µ
PD3725A
Shift register clock voltage V
Reset signal voltage V
Transfer gate signal voltage V
φ
1, Vφ2 –0.3 to +15 V
φ
R1B, VφR2B –0.3 to +15 V
φ
TG –0.3 to +15 V
Operating ambient temperature TA –25 to +60 °C
Storage temperature Tstg –40 to +100 °C
Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding
the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock signal high level V
Shift register clock signal low level V
Reset signal high level V
Reset signal low level V
Transfer gate signal high level V
φ
1H, Vφ2H 4.5 5 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
φ
R1BH, VφR2BH 4.5 5 5.5 V
φ
R1BL, VφR2BL –0.3 0 +0.5 V
φ
TGH 4.5 5 5.5 V
Transfer gate signal low level V
Data rate 2 × f
Remark
φ1:φ
1A1 to φ1A4, φ1L
φ2:φ
2A1 to φ2A4, φ2L
φ
TGL –0.3 0 +0.5 V
φ
R1B, 2 × fφR2B – 2 16 MHz
4
ELECTRICAL CHARACTERISTICS
µ
PD3725A
TA = +25 °C, VOD = 12 V, føR1B, f
φ
R2B = 1 MHz, data rate = 2 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 1.0 1.3 – V
SER 0.3 lx•s
Saturation exposure SEG 0.3 lx•s
SEB 0.6 lx•s
Photo response non-uniformity PRNU VOUT = 500 mV ±6 ±15 %
Average dark signal ADS Light shielding 0.1 5 mV
Dark signal non-uniformity DSNU Light shielding –5 0.5 +5 mV
Power consumption PW 300 500 mW
Output impedance Z O 0.5 1 kΩ
RR 2.71 3.87 5.03 V/lx•s
Response RG 2.66 3.80 4.91 V/lx•s
RB 1.45 2.07 2.70 V/lx•s
Image lag IL VOUT = 500 mV 2 5 %
Offset level
Output fall delay time
Note 1
Note 2
VOS 468V
td 33 40 47 ns
Total transfer efficiency TTE f
Register imbalance RI VOUT = 500 mV 0.0 4.0 %
Red response peak 630 nm
Green response peak 540 nm
Blue response peak 460 nm
Dynamic range DR Vsat/DSNU 2600 times
Reset feed through noise RFSN Light shielding 300 500 mV
φ
R1B, fφR2B = 8 MHz, data rate = 16 MHz 93.5 98 %
Notes 1. Refer to TIMING CHART 3, 5.
2. Each fall delay time of φ1L and φ2L (t11, t27 and t1, t37) is the TYP. value (refer to TIMING CHART 3, 5).
5
INPUT PIN CAPACITANCE
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
φ
TG1 16
µ
PD3725A
Transfer gate pin capacitance C
Reset clock pin capacitance C
Last stage shift register clock pin capacitance C
Shift register clock pin capacitance A C
Shift register clock pin capacitance B C
φ
TG
φ
R 50 80 pF
φ
L 100 150 pF
φ
A 250 380 pF
φ
B 500 750 pF
φ
TG2 13 300 450 pF
φ
TG3 10
φ
R1B 20
φ
R2B 5
φ
1L 19
φ
2L 6
φ
1A1 18
φ
1A4 8
φ
2A1 17
φ
2A4 9
φ
1A2 15
φ
1A3 11
φ
2A2 14
φ
2A3 12
6
TIMING CHART 1
φ
φ
TG1, TG3
φ
φ
φ
φ
1A1 to 1A4, 1L
φ
2A1 to 2A4, 2L
φ
R1B
φ
R2B
V
OUT
1, 3, 5
OUT
2, 4, 6
V
TG2
φ
φ
R, B
G
0 1 2 3 13 60 61 62 63 64 65 66
D0 D2 D4 D8 D26 D122 D126 S1 S3 S5
D1 D3 D5 D25 D27 D123 D127 S2 S4 S6
Vacant transfer (26 bits) Optical black (96 bits) Invalid photocell (6 bits)
Valid photocell (5000 bits)
Caution Pins 18 (
And also pins 17 (
φ
1A1) and 15 (
φ
φ
1A2), 11 (
2A1) and 14 (
φ
1A3) and 8 (φ1A4) are each connected inside of the device, so do not input different timings to them.
φ
2A2), 12 (
φ
2A3) and 9 (
φ
2A4) are each connected inside of the device, so do not input different timings to them
µ
PD3725A
(refer to BLOCK DIAGRAM).
7
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