NEC UPD3720ACY Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3720A

2700 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

The µPD3720A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to

electrical signal and has the function of color separation.

µ

PD3720A has 3 rows of 2700 pixels and 3 pairs of 2 rows of 1350-bit charge transferred registers, reset feed-

The through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. It is suitable for color image scanners, color facsimiles and so on.

FEATURES

• Valid photocell : 2700 pixels × 3

µ

• Photocell's pitch : 10.5

• Line spacing : 42 µm (4 lines) Red line-Green line, Green line-Blue line

• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

• Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate : 3 MHz MAX.

• Power supply : +12 V

• On-chip circuits : Reset feed-through level clamp circuits

• Pin assign : Compatible with the

m

300 dpi US letter (8.5” × 11”) size (shorter side)

Clamp pulse generation circuit Voltage amplifiers

µ

PD3720

ORDERING INFORMATION

Part Number Package

µ

PD3720ACY CCD linear image sensor 22-pin plastic DIP (400 mil)

Document No. S12035EJ1V0DS00(1st edition) Date published November 1996 N Printed in Japan

The information in this document is subject to change without notice.

©

1996

COMPARISON CHART

µ

PD3720A

PIN CONFIGURATION Pin 11 Analog ground Digital ground ELECTRICAL Output fall delay time 70 80

CHARACTERISTICS TYP. (ns) TIMING CHART Output signal waveform Spike noise reduced –

BLOCK DIAGRAM

V

19 2 11 17

OUT

1

V (B)

21

Item

OD

AGND AGND 2L

φ

........

D14

µ

PD3720A

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

S2699

S2700

D65

D66

µ

PD3720

D67

14

φ

1

13

φ

TG1

V (G)

V (R)

OUT

CCD analog shift register

Transfer gate

2

22

Clamp pulse generator

3

1

3

φ

RB

4

φ

1L

........

D14

........

D14

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

S2699

S2700

S2699

S2700

D65

D66

D67

12

φ

TG2

10

φ

TG3

9

φ

2

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin plastic DIP(400 mil)

µ

PD3720A

Output signal 3 (RED)

Analog ground

Reset gate clock

Last stage shift register clock 1

No connection

Shift register clock 2

V

OUT

AGND

φ

RB

φ

1L

NC

φ

V

NC

V

NC

φ

NC

φ

OUT

OD

2L

1

3

1

2

1

3

4

5

6

R

G

B

7

8

9

2

22

21

20

19

18

17

16

15

14

Output signal 2 (GREEN)

2

1

Output signal 1 (BLUE)

No connection

Output drain voltage

No connection

Last stage shift register clock 2

No connection

Shift register clock 1

φ

Transfer gate clock 3

Analog ground

TG3

AGND

10

11

PHOTOCELL STRUCTURE DIAGRAM

2700

7.5 m

µ

Aluminum shield

2700

µ

10.5 m

13

12

µ

3

m

φ

TG1

φ

TG2

Channel stopper

Transfer gate clock 1

Transfer gate clock 2

3

ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)

Parameter Symbol Ratings Unit

Output drain voltage VOD –0.3 to +15 V

µ

PD3720A

Shift register clock voltage V Reset gate clock voltage V Transfer gate clock voltage V

φ

1, Vφ2, Vφ1L, Vφ2L –0.3 to +15 V

φ

RB –0.3 to +15 V

φ

TG1

– V

φ

TG3 –0.3 to +15 V

Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock signal high level V Shift register clock signal low level V Reset gate clock high level V Reset gate clock low level V Transfer gate clock high level V Transfer gate clock low level V Data rate f

φ

1H, Vφ2H, Vφ1LH, Vφ2LH 4.5 5.0 5.5 V

φ

1L, Vφ2L, Vφ1LL, Vφ2LL –0.3 0 +0.5 V

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

TG1H

– V

φ

TG3H 4.5 5.0 5.5 V

φ

TG1L

– V

φ

TG3L –0.3 0 +0.5 V

φ

RB – 1 3 MHz

4

ELECTRICAL CHARACTERISTICS

µ

PD3720A

TA = +25 °C, VOD = 12 V, f

φ

RB = 1 MHz, data rate = 1 MHz, storage time = 5 ms,

light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage Vsat 2.0 3.0 – V Saturation exposure Red SER 0.15 lx•s

Green SEG 0.16 lx•s

Blue SEB 0.27 lx•s Photo response non-uniformity PRNU VOUT = 1 V 6 20 % Average dark signal ADS Light shielding 0.5 2.5 mV Dark signal non-uniformity DSNU Light shielding 1.5 8.0 mV Power consumption PW 400 600 mW Output impedance ZO 0.5 1 kΩ Response Red RR 14.14 20.20 26.26 V/lx•s

Green RG 12.95 18.50 24.05 V/lx•s

Blue RB 7.77 11.10 14.43 V/lx•s Image lag IL VOUT = 1 V 2 10 % Offset level Output fall delay time

Note1

Note2

VOS 3 4.5 6.6 V td VOUT = 1 V 70 ns

Total transfer efficiency TTE VOUT = 1 V, 92 98 %

data rate = 3 MHz

Register imbalance RI VOUT = 1 V 0 1.0 4.0 % Response peak Red 630 nm

Green 540 nm

Blue 460 nm Dynamic range DR1 Vsat /DSNU 2000 times

DR2 Vsat /σ 3000 times Reset feed-through noise Random noise σ Light shielding – 1.0 – mV

Note1

RFTN Light shielding –1000 –300 +300 mV

Notes 1. Refer to TIMING CHART2.

2. When each fall delay time of

φ

1L and φ2L (t2´, t1´) is the TYP. value (refer to TIMING CHART 2).

5

INPUT PIN CAPACITANCE

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

µ

PD3720A

Transfer gate clock pin capacitance C

Reset gate clock pin capacitance C Last stage shift register clock pin capacitance C

Shift register clock pin capacitance 1 C Shift register clock pin capacitance 2 C

φ

TG

φ

RB

φ

L

φ

1

φ

2

φ

TG1 13 200 pF

φ

TG2 12 200 pF

φ

TG3 10 200 pF

φ

RB 3 50 pF

φ

1L 4 30 pF

φ

2L 17 30 pF

φ

1 14 700 pF

φ

2 9 700 pF

6