NEC UPD3719D Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3719
10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3719 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
µ
PD3719 has 3 rows of 10600 pixels, and each row has a single-sided readout type of charge transfer register.
The
It has reset feed-through level clamp circuits and voltage amplifiers. Moreover, a large dynamic range is realized
by using a large saturation voltage and a low-noise amplifier. Therefore, it is suitable for 1200 dpi/A4 professional
color image scanners and so on.
FEATURES
• Valid photocell : 10600 pixels × 3
• Photocell's pitch : 7 µm
µ
• Line spacing : 70
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 2 MHz MAX.
• Power supply : +15 V
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number Package
µ
PD3719D CCD linear image sensor 36-pin ceramic DIP (600 mil)
m (10 lines) Red line-Green line, Green line-Blue line
1200 dpi US letter (8.5” × 11”) size (shorter side)
Voltage amplifiers
Document No. S13492EJ1V0DS00(1st edition)
Date published September 1998 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
©
1998
BLOCK DIAGRAM
φ
CLB
31
V
OUT
1
33
(Blue)
V
OUT
2
V
OUT
(Red)
35
3
2
(Green)
µ
PD3719
φ
φ
2
34
GND
32
GND
15
D14
D14
D14
······
······
······
S1
D64
Transfer gate
CCD analog shift register
S1
D64
Transfer gate
CCD analog shift register
S1
D64
Transfer gate
CCD analog shift register
Photocell
S2
(Blue)
Photocell
S2
(Green)
Photocell
S2
(Red)
S10599
S10600
S10599
S10600
S10599
S10600
D65
D65
D65
D66
D66
D66
D67
D67
D67
GNDGND
3
25 24
1
22
GND
φ
TG
23
GND
21
GND
14
4
5 6
φ
V
RB
OD
V
RD
1312
φ
φ
2
1
2
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (600 mil)
µ
PD3719
No connection
Output signal 3 (Red)
Ground
Output drain voltage
Reset gate clock
Reset drain voltage
No connection
No connection
No connection
V
OUT
GND
V
φ
V
NC
RB
NC
NC
NC
36
35
34
33
32
31
30
29
28
NC
V
OUT
GND
V
OUT
GND
φ
CLB
NC
NC
NC
1
3
2
1
1
Green
1
Blue
3
4
OD
5
6
RD
7
8
9
Red
No connection
Output signal 2 (Green)
2
Ground
1
Output signal 1 (Blue)
Ground
Reset feed-through level
clamp clock
No connection
No connection
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Ground
Ground
No connection
No connection
No connection
NC
NC
φ
φ
GND
GND
NC
NC
NC
27
26
25
24
23
22
21
20
19
NC
NC
φ
φ
φ
GND
GND
NC
NC
10
11
12
2
1
13
14
15
16
10600
10600
10600
17
18
2
1
TG
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock
Ground
Ground
No connection
No connection
3
µ
PD3719
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
7 m
µ
Blue photocell array
4 m
µ
Aluminum
shield
µ
7 m
3
m
µ
Channel stopper
7 m
µ
7 m
µ
Green photocell array
Red photocell array
10 lines
(70 m)
µ
10 lines
(70 m)
µ
4
µ
PD3719
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +16 V
Reset drain voltage VRD –0.3 to +16 V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V
φ
1, Vφ2 –0.3 to +8 V
φ
RB –0.3 to +8 V
φ
CLB –0.3 to +8 V
φ
TG –0.3 to +8 V
Operating ambient temperature TA –25 to +60 °C
Storage temperature Tstg –40 to +100 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 14.0 15.0 16.0 V
Reset drain voltage VRD 14.0 VOD VOD V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level V
Transfer gate clock low level V
Data rate f
Note When Transfer gate clock high level (V
φ
1H, Vφ2H 4.5 5.0 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
φ
RBH 4.5 5.0 5.5 V
φ
RBL –0.3 0 +0.5 V
V
φ
CLBH 4.5 5.0 5.5 V
V
φ
CLBL –0.3 0 +0.5 V
φ
TGH 4.5 V
φ
TGL –0.3 0 +0.3 V
φ
RB – 1 2 MHz
φ
TGH) is higher than Shift register clock high level (Vφ1H), Image lag
Note
φ
1H
Note
V
φ
1H
can increase.
V
5
ELECTRICAL CHARACTERISTICS
µ
PD3719
TA = +25 °C, VOD = 15 V, VRD = 15 V, data rate (f
φ
RB) = 2 MHz, storage time = 5.5 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 4.0 5.0 – V
Saturation exposure Red SER 0.52 lx•s
Green SEG 0.57 lx•s
Blue SEB 0.94 lx•s
Photo response non-uniformity PRNU VOUT = 2.5 V 6 20 %
Average dark signal ADS Light shielding 0.8 3.0 mV
Dark signal non-uniformity DSNU Light shielding 1.5 5.0 mV
Power consumption PW 400 600 mW
Output impedance ZO 0.5 1 kΩ
Response Red RR 6.8 9.7 12.6 V/lx•s
Green RG 6.2 8.8 11.4 V/lx•s
Blue RB 3.8 5.3 6.8 V/lx•s
Image lag IL VOUT = 2.5 V 2.0 5.0 %
Offset level
Output fall delay time
Total transfer efficiency TTE VOUT = 2.5 V 92 98 %
Response peak Red 630 nm
Dynamic range DR1 Vsat /DSNU 3333 times
Reset feed-through noise
Random noise σ Light shielding – 0.5 – mV
Note1
VOS 8.8 10.8 12.8 V
Note2
Green 540 nm
Blue 460 nm
Note1
td VOUT = 2.5 V 70 ns
DR2 Vsat /σ 10000 times
RFTN Light shielding 0 1500 2500 mV
Notes 1. Refer to TIMING CHART 2.
2. When the fall time of
6
φ
1 (t1) is the TYP. value (refer to TIMING CHART 2).
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