NEC UPA1500BH Datasheet

DATA SHEET

31.5 MAX.

4.2 MAX.

123456789101112

2.54 TYP. 0.7±0.1 1.4±0.1 0.5±0.1 1.4 TYP.

2.5 TYP.

10.5 MAX.10.0 MIN.

ELECTRODE CONNECTION

1, 5, 8, 12
2, 4, 9, 11
6, 7
3, 10

GATE
DRAIN, ANODE
SOURCE
CATHODE

COMPOUND FIELD EFFECT POWER TRANSISTOR

µ

PA1500B

N-CHANNEL POWER MOS FET ARRAY

SWITCHING USE

DESCRIPTION

The µPA1500B is N-channel Power MOS FET Array
that built in 4 circuits and surge absorber designed for
solenoid, motor and lamp driver.

FEATURES

• 4 V driving is possible

• Large Current and Low On-state Resistance

I

D(DC) = ±3 A

R

DS(on)1 ≤ 0.18 Ω MAX. (VGS = 10 V, ID = 2 A)

R

DS(on)2 ≤ 0.24 Ω MAX. (VGS = 4 V, ID = 2 A)

• Low Input Capacitance Ciss = 200 pF TYP.

• Surge Absorber, built in

ORDERING INFORMATION

Type Number Package

µ

PA1500BH 12 Pin SIP

ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)

Drain to Source Voltage VDSS
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse) I
Repetitive peak Reverse Voltage
Diode Forward Current I
Total Power Dissipation P
Total Power Dissipation P
Channel Temperature T
Storage Temperature T
Single Avalanche Current I
Single Avalanche Energy E

Notes 1. V

GS = 0

2. V

DS = 0

3. PW ≤ 10

Note 1
Note 2

GSS

D(DC) ±3.0 A/unit

Note 3

D(pulse)

Note 4

VRRM

Note 4

F(av)

Note 5

T1

Note 6

T2
CH 150 ˚C
stg –55 to 150 ˚C

Note 7

AS

Note 7

AS

µ

s, Duty Cycle ≤ 1 %

60 V

±20 V

±12 A/unit

65 V

3.0 A/unit
28 W

4.0 W

3.0 A

0.9 mJ

4. Rating of Surge Absorber

5.

4 Circuits, TC = 25 ˚C

6. 4 Circuits, TA = 25 ˚C

7.

Starting TCH = 25 ˚C, VDD = 30 V, VGS = 20 V → 0,
RG = 25 Ω, L = 100 µH

PACKAGE DIMENSIONS

(in millimeters)

CONNECTION DIAGRAM

234

D

5

D

1

R

R

G

1

6

R

G

8

D1 to D

4

D5 to D

8

Z

D

R

G

Z

D

91011

D

D

Z

D

: Body Diode
: Surge Absorber
: Gate to Source Protection Diode
: Gate Input Resistance 330 Ω TYP.

5

7

3

R

12

G

G

6

D

Z

D

8

D

Z

D

D

2

D

4

7

The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.

Document No. G10597EJ2V0DS00 (2nd edition)
Date Published December 1995 P
Printed in Japan

©

1995

µ

PA1500B

ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)

CHARACTERISTIC SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain Leakage Current IDSS VDS = 60 V, VGS = 0 10
Gate Leakage Current IGSS VGS = ± 20 V, VDS = 0 ±10
Gate Cutoff Voltage VGS(off) VDS = 10 V, ID = 1.0 mA 1.0 2.0 V
Forward Transfer Admittance | Yfs |VGS = 10 V, ID = 2.0 A 2.0 S
Drain to Source On-State RDS(on)1 VGS = 10 V, ID = 2.0 A 0.10 0.18 Ω

Resistance

RDS(on)2 VGS = 4.0 V, ID = 2.0 A 0.14 0.24 Ω
Input Capacitance Ciss VDS = 10 V, VGS = 0, f = 1.0 MHz 200 pF
Output Capacitance Coss 150 pF
Reverse Transfer Capacitance Crss 55 pF
Turn-on Delay Time td(on) ID = 2.0 A, VGS = 10 V, VDD = 30 V, 20 ns
Rise Time tr

RL = 15 Ω

·

·

100 ns
Turn-off Delay Time td(off) 735 ns
Fall Time tf 350 ns
Total Gate Charge QG VGS = 10 V, ID = 3.0 A, VDD = 48 V 13 nC
Gate to Source Charge QGS 2nC
Gate to Drain Charge QGD 4.7 nC
Body Diode Forward Voltage VF(S-D) IF = 3 A, VGS = 0 1.0 V

µ

A

µ

A

SURGE ABSORBER (Diode, builtin) 1 Unit

Repetitive peak Reverse Current
Diode Forward Voltage VF IF = 3.0 A 1.5 V

Test Circuit 1 Avalanche Capability

DUT

in

= 25 Ω

R

PG

VGS = 20 V→ 0

50 Ω

I

AS

I

D

V

DD

IRRM VR = 65 V 10

Test Circuit 2 Switching Time

BV

DSS

Starting T

L

V

DD

V

DS

CH

PG.

V

GS

0

t

t = 1 s

µ

Duty Cycle ≤ 1 %

R

in

R

in

= 10 Ω

DUT

R

L

V

GS

Wave Form

V

DD

I

D

Wave Form

V

GS

10 %

0

I

D

10 %

0

t

d

(on)

t

on

90 %

V

GS (on)

I

D

t

d

(off)

t

r

Test Circuit 3 Gate Charge

DUT

I

G

= 2 mA

R

L

t

off

µ

90 %

A

90 %

10 %

t

f

PG.

50 Ω

V

DD

2

TYPICAL CHARACTERISTICS (TA = 25 ˚C)

µ

PA1500B

TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE

6

NEC

µ

PA1500BH

5

4

Laed

Print
Circuit
Boad

4 Circuits operation
3 Circuits operation

2 Circuits operation

3

1 Circuit operation

2

- Total Power Dissipation - W

1

T

P

0

50 100 150

TA - Ambient Temperature - ˚C

FORWARD BIAS SAFE OPERATING AREA

100

I

I

D(DC)

D(Pulse)

DC

10

Limited (V

DS(on)

R

1

- Drain Current - A

D

I

= 10 V)

GS

TC = 25 ˚C
Single Pulse

0.1

0.1

1 10 100

V

DS -

Drain to Source Voltage - V

Under same
dissipation in
each circuit

PW = 1 ms

10 ms

50 ms

100 ms

TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE

30

4 Circuits operation

20

3 Circuits operation
2 Circuits operation

1 Circuit operation

10

- Total Power Dissipation - W

T

P

TC is grease
Temperature on back surface

0

50 100 150

T

C

- Case Temperature - ˚C

DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA

100

80

60

40

20

dT - Percentage of Rated Power - %

0

20 40 60 80 100 120 140 160

C

- Case Temperature - ˚C

T

Under same
dissipation in
each circuit

FORWARD TRANSFER CHARACTERISTICS

100

10

1.0

- Drain Current - A

D

I

TA = 125˚C

75 ˚C
25 ˚C

-25 ˚C

0.1

25

1346

0

GS

- Gate to Source Voltage - V

V

Pulsed

DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE

12

V

GS

= 20 V

10

10 V

8

6

4

- Drain Current - A

D

I

2

0

DS

V

V

GS

= 4 V

1

2

3

- Drain to Source Voltage - V

Pulsed

4

3