NEC PD75P308 User Manual
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P308
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P308 is a model of the µPD75308 equipped with a one-time PROM or EPROM instead of an
internal mask ROM.
µ
Two types are available as the
quantity of many different types of application systems as data can only be written once to the one-time
PROM of this type. Programs can be written and rewritten to the built-in EPROM type making it ideal
for system evaluation.
Detailed functions are described in the followig user's manual. Be sure to read it for designing.
PD75P308. The one-time PROM type is ideal for production of a small
µ
PD75308 User's Manual: IEM-5016
FEATURES
•
µ
PD75308 compatible
• Memory capacity
• Program memory (PROM): 8064 x 8 bits
• Data memory (RAM): 512 x 4 bits
• Can be connected to a pull-up resistor through software: Ports 0-3, 6, 7
• Open-drain input/output: Ports 4 and 5
• Single power source: 5V ± 5%
ORDERING INFORMATION
Part Number Package Internal ROM
µ
PD75P308GF-3B9 80-pin plastic QFP (14 x 20 mm) One-time PROM
µ
PD75P308K 80-pin ceramic WQFN (LCC w/window) EPROM
QUALITY GRADE
Part Number Package Quality Grade
µ
PD75P308GF-001-3B9 80-pin plastic QFP (14 x 20 mm) Standard
µ
PD75P308K 80-pin Ceramic WQFN (LCC w/window) Standard
★
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The function common to the one-time PROM and EPROM types of product is referred to as PROM throughout this document.
Document No. IC-2472B
(O. D. No. IC-7208C)
Date Published November 1993 P
Printed in Japan
The information in this document is subject to change without notice.
The mark ★ shows major revised points.
NEC Corporation 1989
PIN CONFIGURATION
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
COM0
COM1
COM2
COM3
S11
S10S9S8S7S6S5S4S3S2S1S0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35
µ
µ
PD75P308GF-3B9
PD75P308K
RESET
36 37 38 39 40
P73/KR7
P72/KR6
P71/KR5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X2
X1
PP
V
XT2
XT1
DD
V
P33 (MD3)
P32 (MD2)
P31/SYNC (MD1)
P30/LCDCL (MD0)
P23/BUS
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SBI
µ
PD75P308
BIAS
LC1
LCO
VVV
LC2
P40
P41
P42
P43
SS
V
P50
P51
P52
P53
P01/SCK
P00/INT4
P02/SO/SB0
2
BLOCK DIAGRAM
3
TI0/P13
PTO0/P20
BUZ/P23
SI/SBI/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60KR3/P63,
KR4/P70KR7/P73
BASIC
INTERVAL
TIMER
TIMER/EVENT
COUNTER
INTW
SERIAL
INTERFACE
INTERRUPT
CONTROL
8
BUFFER(16)
INTBT
#0
INTT0
WATCH
TIMER
INTCSI
BIT SEQ.
4
4
4
4
4
P00-P03
P10-P13
P20-P23
P30-P33
/MD0-MD3
P40-P43
PROGRAM
COUNTER(13)
ALU
CY
SP(8)
BANK
PORT0
PORT1
PORT2
PORT3
PORT4
PROGRAM
f
LCD
MEMORY
(PROM)
GENERAL REG.
DECODE
AND
CONTROL
8064 x 8 BITS
DATA
MEMORY
(RAM)
PORT5
PORT6
PORT7
512 x 4 BITS
LCD
CONTROLLER
/DRIVER
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
N
f /2
X
SYSTEM CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
CPU
CLOCK
f
LCD
4
4
4
24
8
4
3
P50-P53
P60-P63
P70-P73
S0-S23
S24/BP0
-S31/BP7
COM0-COM3
V -V
LCO LC2
BIAS
µ
PD75P308
LCDCL/P30
SYNC/P30
PCL/P22
XT1
V
V
DD
X2
X1XT2
PP
RESET
V
SS
µ
PD75P308
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................. 5
1.1 PORT PINS ................................................................................................................................................. 5
1.2 NON PORT PINS ....................................................................................................................................... 6
1.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................ 7
★
1.4 NOTES ON USING P00/INT4 AND RESET PINS ..................................................................................... 9
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308.................................................................. 10
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ........................................................... 11
3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY ............................................ 11
3.2 PROGRAM MEMORY WRITE PROCEDURE .......................................................................................... 12
3.3 PROGRAM MEMORY READ PROCEDURE ............................................................................................ 13
µ
3.4 ERASURE (
PD75P308K ONLY) ............................................................................................................. 14
4. ELECTRICAL SPECIFICATIONS........................................................................................................ 15
5. PACKAGE DRAWINGS ...................................................................................................................... 28
6. RECOMMENDED SOLDERING CONDITIONS................................................................................. 30
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 31
★
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 32
4
1. PIN FUNCTIONS
1.1 PORT PINS
µ
PD75P308
Pin Name
Input/Output Function 8-Bit I/O When Reset
Also Served
As
P00 Input INT4
P01 Input/Output SCK
P02 Input/Output SO/SB0
P03 Input/Output SI/SBI
P10 INT0
P11 INT1
P12 INT2
Input
P13 TI0
P20 PTO0
P21 —
Input/Output
P22 PCL
P23 BUZ
2
P30*
P31*
P32*
P33*
2
Input/Output
2
2
SYNC
MD2
MD3
P40-43*2Input/Output —
P50-P53*2Input/Output —
P60 KR0
P61 KR1
P62 KR2
Input/Output
P63 KR3
P70 KR4
P71 KR5
P72 KR6
Input/Output
P73 KR7
BP0 S24
BP1 S25
BP2 S26
Output
BP3 S27
BP4 S28
BP5 S29
BP6 S30
Output
BP7 S31
4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.
With noise elimination function
4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.
4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.
Programmable 4-bit input/output port
MD0LCDCL
(PORT3)
MD1
This port can be specified for input/output
in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
N-ch open-drain 4-bit input/output port
(PORT4)
Data input/output pin for writing and
verifying of program memory (PROM)
(lower 4 bits)
N-ch open-drain 4-bit input/output port
(PORT5)
Data input/output pin for writing and
verifying of program memory (PROM)
(upper 4 bits)
Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/output
in bit units.
Internal pull-up resistors can be specified
in 4-bit units by software.
4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.
1-bit output port (BIT PORT)
Shared with a segment output pin.
X
X
X
High impedance
●●
High impedance
●●
X
Input
InputX
Input
Input
Input
Input
*3
Input/
Output
Circuit
TYPE
B
F -A
F -B
M -C
B -C
E-B
E-B
M-A
M-A
F -A
F -A
G-C
*1
★
*1: Circles indicate schmitt trigger inputs.
2: Can directly drive LED.
3: For BP0-7, V
LC1 indicated below are selected as the input source.
However, the output level is changed depending on BP0-7 and the VLC1 external circuits.
5
1.2 NON PORT PINS
µ
PD75P308
Pin Name
Input/Output Function When Reset
TI0 Input P13
PTO0 Output P20
PCL Input/Output P22
BUZ Input/Output P23 Input E-B
SCK Input/Output P01
SO/SB0 Input/Output P02 Input
SI/SB1 Input/Output P03 Input M -C
Also Served
As
Timer/event counter external event pulse input
Timer/event counter output
Clock output
Fixed frequency output (for buzzer or for trimming
the system clock)
Serial clock input/output
Serial data output
Serial bus input/output
Serial data input
Serial bus input/output
—
Input
Input
Input
Edge detection vector interrupt input (either rising
INT4 Input P00 —
INT0 P10
Input
INT1 P11
INT2 Input P12
KR0-KR3 Input/Output P60-P63
KR4-KR7 Input/Output P70-P73
S0-S23 Output —
★
S24-S31 Output BP0-7
COM0-
COM3
V
LC0-VLC2 ——
Output —
BIAS — —
LCDCL*2Input/Output P30
SYNC*2Input/Output P31
or falling edge detection is effective)
Edge detection vector interrupt input (detection
edge can be selected)
Edge detection testable input (rising edge detection)
Testable input/output(parallel falling edge detection)
Testable input/output(parallel falling edge detection)
Segment signal output
Segment signal output
Common signal output
LCD drive power
External dividing resistor disconnect output
Externally expanded driver clock output
Externally expanded driver sync clock output
—
—
Input
Input
*3
*3
*3
—
High-impedance
Input
Input
To connect the crystal/ceramic oscillator to the main
X1, X2 Input — —
system clock generator.
When inputting the external clock, input the external
clock to pin X1, and the reverse phase of the
external clock to pin X2.
XT1 Input —
XT2 — —
To connect the crystal oscillator to the subsystem
clock generator.
When the external clock is used, in XT1 inputs the
external clock. In this case, pin XT2 must be left
open.
—
Pin XT1 can be used as a 1-bit input (test) pin.
RESET Input —
MD0-MD3 Input/Output P30-P33
System reset input (low level active)
To select mode when writing/verifying of program
memory (PROM)
—
Input
Program voltage application when writing and
VPP ——
verifying of program memory (PROM)
Connect to V
DD during the normal operation
—
Apply +12.5V when writing/verifying EPROM
DD ——
V
VSS ——
Positive power supply
GND
—
—
Input/
Output
Circuit
*1
TYPE
B -C
E-B
E-B
F -A
F -B
B
B -C
B -C
F -A
F -A
G-A
G-C
G-B
—
—
E-B
E-B
—
—
B
E-B
—
—
—
*1: Circles indicate schmitt trigger inputs.
2: These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31.
3: For these display output, V
LCX indicated below are selected as the input source.
S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output level varies depending on the particular display output and VLCX external circuit.
6
1.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the
µ
PD75P308
µ
PD75P308.
TYPE A (for TYPE E–B)
DD
V
P–ch
IN
N–ch
Input buffer of CMOS standard
TYPE B
IN
TYPE D (for TYPE E–B, F-A)
data
output
disable
P–ch
OUT
N–ch
Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)
TYPE E–B
P.U.R.
enable
data
Type D
output
disable
V
DD
P.U.R.
P–ch
IN/OUT
Schmitt trigger input with hysteresis characteristics
TYPE B–C
V
DD
P.U.R.
P–ch
IN
P.U.R. : Pull
P.U.R.
enable
–Up Resistor
Schmitt trigger input with hysteresis characteristics
TYPE E–E
data
output
disable
Type A
P.U.R. : Pull–Up Resistor
P.U.R.
enable
Type D
Type A
Type B
P.U.R. : Pull–Up Resistor
V
DD
P.U.R.
P–ch
IN/OUT
7
µ
PD75P308
TYPE F–A
data
output
disable
TYPE F–B
output
disable
(P)
data
output
disable
P.U.R.
enable
Type D
Type B
P.U.R. : Pull–Up Resistor
P.U.R.
enable
output
disable
(N)
P.U.R. : Pull–Up Resistor
VDD
V
DD
P-ch
N-ch
P–ch
IN/OUT
V
DD
P.U.R.
P–ch
IN/OUT
TYPE G–B
VLC0
P-ch
VLC1
COM
data
VLC2
N-ch
TYPE G–C
VDD
VLC0
VLC1
SEG
data/Bit Port data
VLC2
P-ch N-ch
OUT
N-ch P-ch
P-ch
P-ch
OUT
N-ch
N-ch
TYPE G–A
VLC0
LC1
V
SEG
data
VLC2
P-ch
P-ch
OUT
N-ch
N-ch
TYPE M–A
data
output
disable
IN/OUT
N-ch
Middle voltage input buffer
8
TYPE M-C
V
DD
P.U.R.
µ
PD75P308
data
output
disable
P.U.R.
enable
N-ch
P–ch
IN/OUT
P.U.R. : Pull–Up Resistor
1.4 NOTES ON USING P00/INT4 AND RESET PINS
In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function
µ
to set a test mode (for IC testing) in which the internal operations of the
When a voltage higher than V
during ordinary operation, the
DD is applied to either of these pins, the test mode is set. This means that, even
µ
PD75P308 may be set in the test mode if a noise exceeding VDD is applied.
PD75P308 are tested.
For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring
line of the pin may cause the above problem.
Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise
preventive measures as shown below by using external components.
• Connect diode with low V
and P00/INT4, RESET pin
Diode with
low V
F
P00/INT4, RESET
F between VDD
• Connect capacitor between V
and P00/INT4, RESET pin
V DD V DD
P00/INT4, RESET
DD
V DDV DD
9
µ
PD75P308
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308
The µPD75P308 is a model of the µPD75308 and is equipped with a PROM instead of a mask ROM.
µ
Programs can be rewritten to the PROM of the
µ
PD75P308 and µPD75308. You should fully consider these differences when you debug or produce your
PD75P308. Table 2-1 shows the differences between the
application system on an experimental basis by using the PROM model, and then proceed to mass-produce
the system by using the mask ROM model.
µ
For the details of the CPU and the internal hardware, refer to
PD75308 User's Manual (IEM-5016).
Table 2-1 Differences between µPD75P308 and µPD75308
Program Memory
Pull-up Resistor Ports 4, 5
Dividing Resistor for LCD
Driving Power Supply
Pin Connection
Electrical Specifications
★
Operating Voltage Range 5V±5% 2.7-6.0V
Package
Others
★
★
Note:
The noise immunity and noise radiation differ between the PROM and mask ROM models. To replace
the PROM model with the mask ROM model in the course of experimental production to mass
production, evaluate your system by using the CS mode (not ES model) of the mask ROM model.
Item
Pins 50-53 P30/MD0-P33/MD3 P30-P33
Pin 57 VPP NC
µ
PD75P308K
• EPROM • PROM (one-time model) • Mask ROM
• 0000H-1F7FH • 0000H-1F7FH • 0000H-1F7FH
• 8064 x 8 bits • 8064 x 8 bits • 8064 x 8 bits
Not provided Mask option
Not provided Mask option
Current dissipations and operating temperature ranges differ between µPD75P308 and
µ
PD75308. For detail, refer to the specification documents of each mode.
80-pin ceramic WQFN
(LCC w/window)
Noise immunity and noise radiation differ because circuit scale and mask layout are
different.
µ
PD75P308GF
80-pin plastic QFP (14 x 20 mm)
µ
PD75308GF
10
µ
PD75P308
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY)
The program memory of the µPD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents
of this PROM, the pins listed in the table below are used. Note that no address input pins are provided
because the address is updated by the clock input through the X1 pin.
Pin Name Function
VPP Applies voltage when program memory is written/verified (normally, at VDD potential)
X1, X2
MD0-MD3 These pins select operation mode when program memory is written/verified.
P40-P43 (Lower 4)
P50-P53 (Upper 4)
VDD
Note 1:
Always cover the erasure window of the µPD75P308K with a light-opaque film except when the
These pins input clock that updates address when program memory is written/verified. To X2 pin,
input signal 180º out of phase in respect to signal to X1 pin.
These pins input/output 8-bit data when program memory is written/verified.
Power supply voltage application pin.
Apply 5V ± 5% to this pin during normal operation and 6V when program memory is written/verified.
contents of the program memory are erased.
2:
The one-time PROM model µPD75P308GF is not equipped with a window and therefore, the
contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays.
3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY
When +6V is applied to the V
DD pin of the
µ
PD75P308 with +12.5V applied to the VPP pin, the µPD75P308
is set in the program memory write/verify mode. In this mode, the following operation modes can be set
by using the MD0-MD3 pins. At this time, pull down the levels of all the other pins to VSS.
VPP
+12.5 V
Operating Mode Specification
VDD
MD0 MD1 MD2 MD3
HLHL
+6 V
LHHH
LLHH
HxHH
Operating Mode
Program memory address 0 clear mode
Write mode
Verify mode
Program inhibit mode
x: L or H
11
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