NEC PD75P0016, PD750004, PD750006, PD750008 User Manual
USER'S MANUAL
µPD750008
4 BIT SINGLE-CHIP MICROCOMPUTER
µPD750004
µPD750006
µPD750008
µPD75P0016
Document No. U10740EJ2V0UM00 (2nd edition)
(Previous No. IEU-1421)
Date Published April 1996 P
©
1995
Printed in Japan
GENERAL
1
PIN FUNCTIONS
FEATURES OF THE ARCHITECTURE AND MEMORY MAP
INTERNAL CPU FUNCTIONS
PERIPHERAL HARDWARE FUNCTIONS
INTERRUPT AND TEST FUNCTIONS
STANDBY FUNCTION
RESET FUNCTION
WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)
MASK OPTION
INSTRUCTION SET
FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016
DEVELOPMENT TOOLS
MASK ROM ORDERING PROCEDURE
2
3
4
5
6
7
8
9
10
11
A
B
C
INSTRUCTION INDEX
HARDWARE INDEX
RIVISION HISTORY
D
E
F
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M7 94.11
Major Changes
Page Description
All The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4
to µPD750008GB-xxx-3BS-MTX.
The µPD75P0016 under development has been changed to the already-developed
µPD75P0016.
The input withstand voltage at ports 4 and 5 during open drain has been changed from
12 V to 13 V.
Preface English-version document numbers have been added to "Related documents."
p.4 The format of the table in Section 1.3 has been changed.
p.45 The caution in using Mk II mode has been added in Section 4.1.1 .
p.85 The description for the mask option when using the feedback resistor has been added in
(6) in Section 5.2.2.
p.187 The description for the interrupt enable flag has been added in Section 6.3.
p.198 Table 6-4 has been added in Section 6.6.
p.233 Section 9.4 has been added.
p.235 Chapter 10 has been added.
p.237–298 The operand @rpa has been changed to @rpa1 in Section 11.
p.241 @rpa1 has been added in the table in (1) in Section 11.2.
p.264 The title of Section 11.4 has been modified to conform to that of Section 11.2.
p.301 Appendix B
Supported OS versions have been upgraded.
p.321 Appendix F has been added.
The mark * shows major revised points.
PREFACE
Readers This manual is intended for engineers who want to learn the capabilities of the
µPD750004, µPD750006, µPD750008, and µPD75P0016 to develop application systems
based on them.
Purpose The purpose of this manual is to help users understand the hardware capabilities (shown
below) of the µPD750004, µPD750006, µPD750008, and µPD75P0016.
Configuration This manual is roughly divided as follows:
• General
• Pin functions
• Architecture feature and memory map
• Internal CPU functions
• Peripheral hardware functions
• Interrupt and test functions
• Standby function
• Reset function
• Writing to and verifying program memory (PROM)
• Mask option
• Instruction set
Guidance Readers of this manual should have general knowledge of the electronics, logical circuit,
and microcomputer fields.
• For users who have used the µPD75008:
–> See Appendix A to check for any difference in the functions and read the
explanation of those differences.
• To check the functions of an instruction in detail when the reader knows its
mnemonics:
–> See the instruction index in Appendix D.
• To check the functions of specific internal circuits, etc.:
–> See Appendix E.
• To understand the overall functions of the µPD750004, µPD750006, µPD750008,
and µPD75P0016:
–> Read through all chapters sequentially.
Notation Data bit significance : Higher-order bits on the left side
Lower-order bits on the right side
Active low : xxx (Pin and signal names are overscored.)
Memory map address : Low-order address on the upper side
High-order address on the lower side
Note : Explanation of an indicated part of text
Caution : Information requesting the user's special attention
Remark : Supplementary information
Important and emphasized matter : Described in bold face
Numeric value : Binary .................. xxxx or xxxxB
Decimal ............... xx xx
Hexadecimal ....... xxxxH
Related documents Some documents are preliminary editions, but they are not so specified in the tables
below.
Documents related to devices
*
Document Name
µPD750004, 750006, 750008 Data Sheet U10738J IC-3647
µPD75P0016 Data Sheet U10328J To be prepared
µPD750008 User’s Manual U10740J (This manual) IEU-1421
µPD750008 Instruction List IEM-5593 —
75XL Series Selection Guide U10453J U10453E
Document Number
Japanese English
Documents related to development tools
Document Name
Hardware IE-75000-R/IE-75001-R User’s Manual EEU-846 EEU-1416
IE-75300-R-EM User’s Manual EEU-951 EEU-1493
EP-75008CU-R User’s Manual EEU-699 EEU-1317
EP-75008GB-R User's Manual EEU-698 EEU-1305
PG-1500 User’s Manual EEU-651 EEU-1335
Software RA75X Assembler Package User’s Operation EEU-731 EEU-1346
Manual
PG-1500 Controller PC-9800 Series (MS-DOSTM) Base EEU-704 EEU-1291
User’s Manual
IBM PC Series (PC DOS
Language EEU-730 EEU-1363
TM
) Base EEU-5008 U10540E
Document Number
Japanese English
Other documents
Document Name
Package Manual IEI-635 IEI-1213
Semiconductor Device Mounting Technology Manual IEI-616 IEI-1207
Quality Grade on NEC Semiconductor Devices IEI-620 IEI-1209
Reliability and Quality Control of NEC Semiconductor Devices IEI-5068 —
Electrostatic Discharge (ESD) Test MEM-539 —
Semiconductor Device Quality Guarantee Guide MEI-603 MEI-1202
Microcontroller-Related Products Guide - by third parties MEI-604 —
Document Number
Japanese English
Caution The above related documents are subject to change without notice. Be sure to use the
latest edition when you design your system.
[MEMO]
CONTENTS
CHAPTER 1 GENERAL ......................................................................................................................... 1
1.1 FUNCTION OVERVIEW ......................................................................................... 2
1.2 ORDERING INFORMATION................................................................................... 3
1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS ............................................. 4
1.4 BLOCK DIAGRAM .................................................................................................. 5
1.5 PIN CONFIGURATION (TOP VIEW) ..................................................................... 6
CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 9
2.1 PIN FUNCTIONS OF THE µPD750008 ................................................................. 9
2.2 PIN FUNCTIONS .................................................................................................... 12
2.2.1 P00-P03 (PORT0)...................................................................................... 12
P10-P13 (PORT1)...................................................................................... 12
2.2.2 P20-P23 (PORT2)...................................................................................... 13
P30-P33 (PORT3)...................................................................................... 13
P40-P43 (PORT4), P50-P53 (PORT5) ..................................................... 13
P60-P63 (PORT6), P70-P73 (PORT7) ..................................................... 13
2.2.3 P80, P81 (PORT8)..................................................................................... 13
2.2.4 TI0 .............................................................................................................. 13
2.2.5 PTO0, PTO1 .............................................................................................. 13
2.2.6 PCL............................................................................................................. 14
2.2.7 BUZ ............................................................................................................ 14
2.2.8 SCK, SO/SB0, SI/SB1 ............................................................................... 1 4
2.2.9 INT4............................................................................................................ 14
2.2.10 INT0, INT1 ................................................................................................ 14
2.2.11 INT2 .......................................................................................................... 1 5
2.2.12 KR0-KR3................................................................................................... 15
KR4-KR7................................................................................................... 15
2.2.13 X1, X2 ....................................................................................................... 15
2.2.14 XT1, XT2................................................................................................... 16
2.2.15 RESET ...................................................................................................... 16
2.2.16 V
2.2.17 V
......................................................................................................................................... 16
DD
......................................................................................................................................... 16
SS
2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only).................. 17
2.2.19 VPP (for the µPD75P0016 only)............................................................... 1 7
2.2.20 MD0-MD3 (for the µPD75P0016 only)..................................................... 17
2.3 PIN INPUT/OUTPUT CIRCUITS ............................................................................ 18
2.4 CONNECTION OF UNUSED PINS........................................................................ 20
- i -
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 21
3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21
3.1.1 Data Memory Bank Structure .................................................................... 21
3.1.2 Data Memory Addressing Modes .............................................................. 23
3.2 GENERAL REGISTER BANK CONFIGURATION ................................................. 3 4
3.3 MEMORY -M APP ED I /O .......................................................................................... 39
CHAPTER 4 INTERNAL CPU FUNCTIONS ......................................................................................... 45
4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS................................................... 45
4.1.1 Differences between Mk I Mode and Mk II Mode..................................... 45
4.1.2 Setting of the Stack Bank Selection Register (SBS)................................ 46
4.2 PROGRAM COUNTER (PC) ................................................................................. 47
4.3 PROGRAM MEMORY (ROM) ................................................................................ 48
4.4 DATA MEMORY (RAM) .......................................................................................... 5 3
4.4.1 Data Memory Configuration....................................................................... 5 3
4.4.2 Specification of a Data Memory Bank....................................................... 54
4.5 GENERAL REGISTER............................................................................................ 56
4.6 ACCUMULATOR..................................................................................................... 5 7
4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)............ 58
4.8 PROGRAM STATUS WORD (PSW) ...................................................................... 62
4.9 BANK SELECT REGISTER (BS) ........................................................................... 65
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ...................................................................... 6 7
5.1 DIGITAL I/O PORTS............................................................................................. 67
5.1.1 Types, Features, and Configurations of Digital I/O Ports ........................ 68
5.1.2 I/O Mode Setting........................................................................................ 74
5.1.3 Digital I/O Port Manipulation Instructions ................................................. 76
5.1.4 Digital I/O Port Operation .......................................................................... 7 9
5.1.5 Specification of Bilt-in Pull-Up Resistors .................................................. 81
5.1.6 I/O Timing of Digital I/O Ports ................................................................... 82
5.2 CLOCK GENERA TOR ............................................................................................ 8 4
5.2.1 Clock Generator Configuration.................................................................. 84
5.2.2 Functions and Operations of the Clock Generator ................................... 85
5.2.3 System Clock and CPU Clock Setting ...................................................... 94
5.2.4 Clock Output Circuit................................................................................... 96
5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER ................................................... 99
5.3.1 Configuration of the Basic Interval Timer/Watchdog Timer ..................... 99
5.3.2 Basic Interval Timer Mode Register (BTM) .............................................. 99
5.3.3 Watchdog Timer Enable Flag (WDTM)..................................................... 101
5.3.4 Operation of the Basic Interval Timer ....................................................... 10 1
- ii -
5.3.5 Operation of the Watchdog Timer ............................................................. 102
5.3.6 Other Functions ......................................................................................... 103
5.4 CLOCK TIMER ........................................................................................................ 105
5.4.1 Configuration of the Clock Timer .............................................................. 106
5.4.2 Clock Mode Register ................................................................................. 106
5.5 TIMER/EVENT COUNTER ..................................................................................... 108
5.5.1 Configuration of Timer/Event Counter ...................................................... 108
5.5.2 8-Bit Timer/Event Counter Mode Operation ............................................. 114
5.5.3 Notes on Timer/Event Counter Applications............................................. 120
5.6 SERIAL INTERFACE.............................................................................................. 1 23
5.6.1 Serial Interface Functions.......................................................................... 123
5.6.2 Configuration of Serial Interface ............................................................... 124
5.6.3 Register Functions ..................................................................................... 127
5.6.4 Operation Halt Mode.................................................................................. 13 5
5.6.5 Three-Wire Serial I/O Mode Operations ................................................... 137
5.6.6 Two-Wire Serial I/O Mode ......................................................................... 144
5.6.7 SBI Mode Operation .................................................................................. 150
5.6.8 Manipulation of SCK Pin Output ............................................................... 179
5.7 BIT SEQUENTIAL BUFFER ................................................................................... 181
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS .............................................................................. 183
6.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT........................... 183
6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES ............................. 185
6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS.......................... 1 87
6.4 INTERRUPT SEQUENCE ...................................................................................... 195
6.5 MULTIPLE INTERRUPT PROCESSING CONTROL............................................. 1 96
6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS ................. 198
6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING .................... 200
6.8 EFFECTIVE USE OF INTERRUPTS ..................................................................... 202
6.9 INTERRUPT APPLICATIONS ................................................................................ 202
6.10 TEST FUNCTION ................................................................................................. 210
6.10.1 Test Sources.......................................................................................... 21 0
6.10.2 Hardware to Control Test Functions ..................................................... 210
CHAPTER 7 STANDBY FUNCTION ..................................................................................................... 215
7.1 SETTING OF STANDBY MODES AND OPERATION STATUS ........................... 216
7.2 RELEASE OF THE STANDBY MODES................................................................. 2 17
7.3 OPERATION AFTER A STANDBY MODE IS RELEASED ................................... 219
7.4 SELECTION OF A MASK OPTION ........................................................................ 220
7.5 APPLICATIONS OF THE STANDBY MODES....................................................... 22 0
- iii -
CHAPTER 8 RESET FUNCTION ........................................................................................................... 225
CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 229
9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING
THE PROGRAM MEMORY .................................................................................... 230
9.2 WRITING TO THE PROGRAM MEMORY ............................................................. 230
9.3 READING THE PROGRAM MEMORY .................................................................. 232
*
9.4 SCREENING OF ONE-TIME PROM ...................................................................... 233
CHAPTER 10 MASK OPTION ............................................................................................................... 235
*
10.1 PIN......................................................................................................................... 235
10.2 MASK OPTION OF STANDBY FUNCTION......................................................... 2 35
10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK ........ 236
CHAPTER 11 INSTRUCTION SET .......................................................................................................... 2 37
11.1 UNIQUE INSTRUCTIONS .................................................................................... 23 7
11.1.1 GETI Instruction ..................................................................................... 237
11.1.2 Bit Manipulation Instructions .................................................................. 238
11.1.3 String-Effect Instructions........................................................................ 2 38
11.1.4 Number System Conversion Instructions .............................................. 23 9
11.1.5 Skip Instructions and the Number of Machine Cycles Required
for a Skip ............................................................................................... 240
11.2 INSTRUCTION SET AND OPERATION .............................................................. 241
11.3 INSTRUCTION CODES OF EACH INSTRUCTION ............................................ 258
11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS.......................... 26 4
11.4.1 Transfer Instructions .............................................................................. 264
11.4.2 Table Reference Instructions................................................................. 2 7 0
11.4.3 Bit Transfer Instructions ......................................................................... 273
11.4.4 Arithmetic/Logical Instructions ............................................................... 273
11.4.5 Accumulator Manipulation Instructions.................................................. 279
11.4.6 Increment/Decrement Instructions......................................................... 2 79
11.4.7 Compare Instructions ............................................................................. 280
11.4.8 Carry Flag Manipulation Instructions..................................................... 2 8 1
11.4.9 Memory Bit Manipulation Instructions ................................................... 282
11.4.10 Branch Instructions .............................................................................. 28 4
11.4.11 Subroutine Stack Control Instructions ................................................. 289
11.4.12 Interrupt Control Instructions ............................................................... 293
11.4.13 I/O Instructions ..................................................................................... 29 4
11.4.14 CPU Control Instructions ..................................................................... 295
11.4.15 Special Instructions .............................................................................. 295
- iv -
APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ............................ 2 99
APPENDIX B DEVELOPMENT TOOLS................................................................................................ 30 1
APPENDIX C MASKED ROM ORDERING PROCEDURE ................................................................... 3 09
APPENDIX D INSTRUCTION INDEX.................................................................................................... 31 1
D.1 INSTRUCTION INDEX (BY FUNCTION) .............................................................. 311
D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER) ............................................. 314
APPENDIX E HARDWARE INDEX.......................................................................................................... 317
E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE.......
HARDWARE NAME).............................................................................................. 317
E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE
HARDWARE SYMBOL) ......................................................................................... 319
APPENDIX F REVISION HISTORY ......................................................................................................... 321
*
- v -
LIST OF FIGURES (1/4)
Figure No. Title Page
2-1 Pin Input/Output Circuits .................................................................................................. 18
3-1 Use of MBE = 0 Mode and MBE = 1 Mode..................................................................... 22
3-2 Data Memory Organization and Addressing Range of Each Addressing Mode ............ 24
3-3 Updating Static RAM Addresses ...................................................................................... 2 8
3-4 Example of Register Bank Selection ............................................................................... 35
3-5 General Register Configuration (4-bit Processing) ......................................................... 37
3-6 General Register Configuration (8-bit Processing) ......................................................... 38
3-7 µPD750008 I/O Map......................................................................................................... 40
4-1 Stack Bank Selection Register Format............................................................................ 46
4-2 Program Counter Organization ........................................................................................ 47
4-3 Program Memory Map (in µPD750004)........................................................................... 49
4-4 Program Memory Map (in µPD750006)........................................................................... 50
4-5 Program Memory Map (in µPD750008)........................................................................... 51
4-6 Program Memory Map (in µPD75P0016)......................................................................... 52
4-7 Data Memory Map ............................................................................................................ 5 4
4-8 General Register Format.................................................................................................. 56
4-9 Register Pair Format ........................................................................................................ 5 7
4-10 Accumulator ...................................................................................................................... 57
4-11 Format of Stack Pointer and Stack Bank Select Register .............................................. 59
4-12 Data Saved to the Stack Memory (Mk I Mode) ............................................................... 59
4-13 Data Restored from the Stack Memory (Mk I Mode) ...................................................... 60
4-14 Data Saved to the Stack Memory (Mk II Mode) .............................................................. 60
4-15 Data Restored from the Stack Memory (Mk II Mode) ..................................................... 61
4-16 Program Status Word Format .......................................................................................... 62
4-17 Bank Select Register Format ........................................................................................... 65
5-1 Data Memory Addresses of Digital Ports......................................................................... 6 7
5-2 Configurations of Ports 0 and 1 ....................................................................................... 69
5-3 Configurations of Ports 2 and 7 ....................................................................................... 70
5-4 Configurations of Ports 3n and 6n (n = 0 to 3) ................................................................ 71
5-5 Configurations of Ports 4 and 5 ....................................................................................... 72
5-6 Configuration of Port 8 ..................................................................................................... 73
5-7 Formats of Port Mode Registers...................................................................................... 75
5-8 Pull-Up Resistor Specification Register Format.............................................................. 82
- vi -
LIST OF FIGURES (2/4)
Figure No. Title Page
5-9 I/O Timing Chart of Digital I/O Ports................................................................................ 82
5-10 ON Timing Chart of Built-in Pull-Up Resistor Connected by Software.......................... 8 3
5-11 Block Diagram of the Clock Generator ............................................................................ 84
5-12 Format of the Processor Clock Control Register............................................................. 8 7
5-13 Format of the System Clock Control Register ................................................................. 88
5-14 External Circuit for the Main System Clock Oscillator .................................................... 89
5-15 External Circuit for the Subsystem Clock Oscillator........................................................ 8 9
5-16 Examples of Oscillator Connections Which Should Be Avoided .................................... 90
5-17 Subsystem Clock Oscillator .............................................................................................. 9 2
5-18 Sub-Oscillator Control Register (SOS) Format ............................................................... 93
5-19 Changing the System Clock and CPU Clock ................................................................... 95
5-20 Configuration of the Clock Output Circuit ........................................................................ 96
5-21 Format of the Clock Output Mode Register..................................................................... 9 7
5-22 Application to Remote Control Output ............................................................................. 98
5-23 Block Diagram of the Basic Interval Timer/Watchdog Timer .......................................... 99
5-24 Format of the Basic Interval Timer Mode Register ......................................................... 100
5-25 Format of the Watchdog Timer Enable Flag (WDTM) ..................................................... 1 0 1
5-26 Block Diagram of the Clock Timer ................................................................................... 10 6
5-27 Clock Mode Register Format ........................................................................................... 107
5-28 Block Diagram of the Timer/Event Counter (Channel 0) ................................................ 109
5-29 Block Diagram of the Timer Counter (Channel 1)........................................................... 1 10
5-30 Timer/Event Counter Mode Register (Channel 0) Format .............................................. 112
5-31 Timer Counter Mode Register (Channel 1) Format......................................................... 11 3
5-32 Timer/Event Counter Output Enable Flag Format........................................................... 114
5-33 Timer/Event Counter Mode Register Setup..................................................................... 1 15
5-34 Timer/Event Counter Output Enable Flag Setup............................................................. 116
5-35 Configuration of Timer/Event Counter ............................................................................. 11 8
5-36 Count Operation Timing ................................................................................................... 11 9
5-37 Error at the Start of the Timer.......................................................................................... 12 0
5-38 Example of the SBI System Configuration ...................................................................... 1 24
5-39 Block Diagram of the Serial Interface .............................................................................. 125
5-40 Format of Serial Operation Mode Register (CSIM) ......................................................... 127
5-41 Format of Serial Bus Interface Control Register (SBIC) ................................................. 131
5-42 Peripheral Hardware of Shift Register ............................................................................. 134
5-43 Example of Three-Wire Serial I/O System Configuration ................................................ 1 37
5-44 Timing of Three-Wire Serial I/O Mode............................................................................. 1 40
- vii -
LIST OF FIGURES (3/4)
Figure No. Title Page
5-45 Operations of RELT and CMDT....................................................................................... 14 1
5-46 Transfer Bit Switching Circuit........................................................................................... 141
5-47 Example of Two-Wire Serial I/O System Configuration .................................................. 14 4
5-48 Timing of Two-Wire Serial I/O Mode ................................................................................ 1 4 7
5-49 Operations of RELT and CMDT....................................................................................... 14 8
5-50 Example of SBI System Configuration ............................................................................. 150
5-51 Timing of SBI Transfer ..................................................................................................... 152
5-52 Bus Release Signal .......................................................................................................... 153
5-53 Command Signal .............................................................................................................. 153
5-54 Address ............................................................................................................................. 153
5-55 Slave Selection Using an Address................................................................................... 154
5-56 Command .......................................................................................................................... 154
5-57 Data................................................................................................................................... 154
5-58 Acknowledge Signal ......................................................................................................... 155
5-59 Busy and Ready Signals .................................................................................................. 15 6
5-60 Operations of RELT, CMDT, RELD, and CMDD (Master) .............................................. 161
5-61 Operations of RELT, CMDT, RELD, and CMDD (Slave) ................................................ 161
5-62 Operation of ACKT ........................................................................................................... 162
5-63 Operation of ACKE ........................................................................................................... 162
5-64 Operation of ACKD........................................................................................................... 16 3
5-65 Operation of BSYE ........................................................................................................... 16 4
5-66 Pin Configuration .............................................................................................................. 167
5-67 Address Transfer Operation from Master Device to Slave Device (WUP = 1) .............. 169
5-68 Command Transfer Operation from Master Device to Slave Device .............................. 17 0
5-69 Data Transfer Operation from Master Device to Slave Device....................................... 17 1
5-70 Data Transfer Operation from Slave Device to Master Device....................................... 17 2
5-71 Example of Serial Bus Configuration ............................................................................... 174
5-72 Transfer Format of the READ Command ........................................................................ 175
5-73 Transfer Format of the WRITE and END Commands..................................................... 176
5-74 Transfer Format of the STOP Command......................................................................... 1 76
5-75 Transfer Format of the STATUS Command .................................................................... 177
5-76 Status Format of the STATUS Command ....................................................................... 177
5-77 Transfer Format of the RESET Command ...................................................................... 1 78
5-78 Transfer Format of the CHGMST Command................................................................... 178
5-79 Master and Slave Operation in Case of Error ................................................................. 17 9
5-80 SCK/P01 Pin Circuit Configuration .................................................................................. 1 80
- viii -
LIST OF FIGURES (4/4)
Figure No. Title Page
5-81 Format of the Bit Sequential Buffer ................................................................................. 181
6-1 Block Diagram of Interrupt Control Circuit....................................................................... 184
6-2 Interrupt Vector Table ....................................................................................................... 18 5
6-3 Interrupt Priority Specification Register ........................................................................... 189
6-4 Configurations of the INT0, INT1, and INT4 Circuits ...................................................... 191
6-5 I/O Timing of a Noise Eliminator...................................................................................... 19 2
6-6 Format of Edge Detection Mode Registers ..................................................................... 193
6-7 Interrupt Sequence ........................................................................................................... 195
6-8 Multiple Interrupt Processing by a High-Order Interrupt ................................................. 196
6-9 Multiple Interrupt Processing by Changing the Interrupt Status Flags........................... 197
6-10 Block Diagram of the INT2 and KR0 to KR7 Circuits ...................................................... 2 1 2
6-11 Format of INT2 Edge Detection Mode Register (IM2) .................................................... 213
7-1 Standby Mode Release Operation................................................................................... 218
7-2 Wait Time When the STOP Mode Is Released............................................................... 219
8-1 Configuration of Reset Functions..................................................................................... 22 5
8-2 Reset Operation by Generation of RESET Signal .......................................................... 225
B-1 Drawings of the EV-9200G-44 (Reference)..................................................................... 3 06
B-2 Recommended Pattern on Boards for the EV-9200G-44 (Reference) ........................... 307
- ix -
LIST OF TABLES (1/2)
Table No. Title Page
1-1 Features of the Products.................................................................................................. 1
2-1 Digital I/O Port Pins.......................................................................................................... 9
2-2 Non-Port Pin Functions .................................................................................................... 11
2-3 Connection of Unused Pins .............................................................................................. 20
3-1 Addressing Modes............................................................................................................ 25
3-2 Register Bank to Be Selected with the RBE and RBS.................................................... 34
3-3 Recommended Use of Register Banks with Normal Routines and
Interrupt Routines ............................................................................................................. 34
3-4 Addressing Modes Applicable to Peripheral Hardware Operation.................................. 39
4-1 Differences between Mk I Mode and Mk II Mode............................................................ 4 5
4-2 Stack Area to Be Selected by the SBS ........................................................................... 58
4-3 PSW Flags Saved/Restored in Stack Operation............................................................. 62
4-4 Carry Flag Manipulation Instructions ............................................................................... 6 3
4-5 Information Indicated by the Interrupt Status Flag.......................................................... 64
4-6 Register Bank to Be Selected with the RBE and RBS.................................................... 66
5-1 Types and Features of Digital Ports ................................................................................ 68
5-2 I/O Pin Manipulation Instructions ..................................................................................... 7 8
5-3 Operations by I/O Port Manipulation Instructions ............................................................ 80
5-4 Specification of Built-in Pull-Up Resistors ....................................................................... 81
5-5 Maximum Time Required to Change the System Clock and CPU Clock....................... 94
5-6 Resolution and Longest Setup Time ................................................................................ 117
5-7 Serial Clock Selection and Application (In the Three-Wire Serial I/O Mode) ................. 1 40
5-8 Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode) ................... 148
5-9 Serial Clock Selection and Application (In the SBI Mode) .............................................. 1 60
5-10 Various Signals Used in the SBI Mode............................................................................ 16 5
6-1 Interrupt Sources.............................................................................................................. 185
6-2 Set Signals for Interrupt Request Flags........................................................................... 18 8
6-3 Interrupt Processing Statuses of IST0 and IST1............................................................. 19 4
6-4 Identifying Interrupt Sharing Vector Table Address ........................................................ 198
6-5 Test Source ....................................................................................................................... 2 10
6-6 Signals Setting Test Request Flags ................................................................................. 2 10
- x -
LIST OF TABLES (2/2)
Table No. Title Page
7-1 Operation Statuses in the Standby Mode........................................................................ 21 6
7-2 Selection of a Wait Time with BTM .................................................................................. 21 9
8-1 Status of the Hardware after a Reset .............................................................................. 226
10-1 Selecting Mask Option of Pin........................................................................................... 235
- xi -
[MEMO]
- xii -
CHAPTER 1 GENERAL
CHAPTER 1 GENERAL
The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcomputers. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004,
µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries.
The 75XL series takes over the CPUs of the 75X series, realizing a wide range of operating voltages and
high-speed operation. In addition to having upward compatibility with existing products, the 75XL series is
best suited for battery-driven applications.
The µPD750004, µPD750006, µPD750008, and µPD75P0016 have the following features:
• Operable on low voltage: VDD = 2.2 to 5.5 V
• Switchable instruction execution times (useful for high-speed operation and power saving)
0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (at 4.19 MHz)
0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (at 6.0 MHz)
122 µs (at 32.768 kHz)
• Enhanced timers: 4 channels
• Easy replacement (The functions and instructions of the µPD75008 are taken over.)
The 75XL series comes in four models, according to the size and type of program memory (see
Table 1-1).
Table 1-1. Features of the Products
1
Model Program memory (ROM) Remarks
µPD750004 4096 x 8 bits Masked ROM
µPD750006 6144 x 8 bits
µPD750008 8192 x 8 bits
µPD75P0016 16384 x 8 bits One-time PROM
The µPD75P0016, having the electrically programmable one-time PROM, is pin-compatible with the
µPD750004, µPD750006, and µPD750008. It is suitable for small-scale production or prototype production
in system development.
Applications
• Consumer electronics
VCR, audio equipment (such as CD players), remote controller, etc.
• Others
Telephone, camera, etc.
Remark This manual will explain only the µPD750008 when the µPD750008, µPD750004,
µPD750006, and µPD75P0016 are functionally the same. Users of the µPD750004, µPD750006,
or µPD75P0016 should read µPD750008 as referring to µPD750004, µPD750006, or µPD75P0016.
1
µPD750008 USER'S MANUAL
1.1 FUNCTION OVERVIEW
Item Function
Instruction execution •0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz)
time •0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz)
Internal memory ROM 4096 x 8 bits (µPD750004)
RAM 512 x 4 bits
General register •When operating in 4 bits: 8 x 4 banks
I/O port 34 8 CMOS input pins Can incorporate 25 pull-up resistors
*
•122 µs (when the subsystem clock operates at 32.768 kHz)
6144 x 8 bits (µPD750006)
8192 x 8 bits (µPD750008)
16384 x 8 bits (µPD75P0016)
•When operating in 8 bits: 4 x 4 banks
18 CMOS I/O pins
Four pins can directly drive
the LED.
8 N-ch open-drain I/O pins Can withstand 13 V.
Eight pins can directly drive Can incorporate pull-up resistors that
the LED. are specified with the mask option.
that are specified with the software.
Note
Timer 4 •Timer/event counter: 1 channel
•Timer counter: 1 channel
•Basic interval timer/watchdog timer: 1 channel
•Clock timer: 1 channel
Serial interface •Three-wire serial I/O mode (switchable between the start LSB and the start MSB)
•Two-wire serial I/O mode
•SBI mode
Bit sequential buffer 16 bits
Clock output •F, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz)
•F, 750 kHz, 375 kHz, 93.7 kHz (when the main system clock operates at 6.0 MHz)
Vectored interrupt External: 3,Internal: 4
Test input External: 1,Internal: 1
System clock oscillator •Ceramic or crystal oscillator for the main system clock
•Crystal oscillator for the subsystem clock
Standby function STOP/HALT mode
Operating ambient T
temperature
Supply voltage V
Package 42-pin plastic shrink DIP (600 mil)
–40°C to +85°C
A =
2.2 to 5.5 V
DD =
44-pin plastic QFP (10 x 10 mm)
*
NoteThe N-ch open-drain I/O port pins of the µPD75P0016 are not connected to pull-up resistors by mask
option, and are always open.
2
CHAPTER 1 GENERAL
1.2 ORDERING INFORMATION
Part number Package On-chip ROM
µPD750004CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM
Note
Note
Note
Note
44-pin plastic QFP (10 x 10 mm) Masked ROM
44-pin plastic QFP (10 x 10 mm) Masked ROM
44-pin plastic QFP (10 x 10 mm) Masked ROM
44-pin plastic QFP (10 x 10 mm) One-time PROM
µPD750004GB-xxx-3BS-MTX
µPD750006CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM
µPD750006GB-xxx-3BS-MTX
µPD750008CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM
µPD750008GB-xxx-3BS-MTX
µPD75P0016CU 42-pin plastic shrink DIP (600 mil) One-time PROM
µPD75P0016GB-3BS-MTX
Note Code orders on and after April 1, 1996 can be accepted.
Remark xxx is a ROM code number.
*
*
*
*
3
µPD750008 USER'S MANUAL
1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS
Item µPD750004 µPD750006 µPD750008 µPD75P0016
Program counter 12 bits 13 bits 14 bits
Program memory (byte) Masked ROM Masked ROM Masked ROM One-time PROM
4096 6144 8192 16384
Data memory (x 4 bits) 512
Mask Pull-up resistors at Incorporated None
option ports 4 and 5 (Whether to incorporate pull-up resistors can (Cannot be
be specified.) incorporated.)
*
*
Wait time during Available Not available
RESET (Can be selected from 217/fX or 215/fX.)
Selection to use Yes No
feedback resistors (Whether to enable feedback resistors can (Use of feedback
for subsystem clock be specified.) resistors is factory-set)
Pin 6-9 (CU) P33-30 P33/MD3-P30/MD0
connection
Others Noise immunity and noise radiation vary with the circuit scale and mask
23-26 (GB)
20 (CU) IC V
38 (GB)
layout.
Note
(Fixed to 215/fX.)
PP
Note 217/fX (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz)
215/fX (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz)
Caution The noise immunity and noise radiation of the PROM model differ from those of the mask
ROM model. If you replace the PROM model with the ROM model of the course of
experimental production to mass production, perform thorough evaluation by using the
CS model (not ES model) of the mask ROM model.
4
1.4 BLOCK DIAGRAM
CHAPTER 1 GENERAL
TI0
PTO0
PTO1
BUZ
SI/SB1
SO/SB0
SCK
INT0
INT1
INT2
INT4
KR0 - KR7
Basic interval timer/
watchdog timer
TOUT0
TOUT0
INTBT
Timer/event
counter
INTT0
Timer counter
INTT1
Wach timer
INTW
Clocked serial
interface
INTCSI
Interrupt
control
RESET
Program
counter
ROM
program
memory
Clock output
control
PCL/P22
Note 1
Note 2
Clock divider
N
X
/2
f
Sub Main
XT1XT2 X1 X2
ALU
Decode and
control
Clock generator
CY
General register
RAM
data memory
512 x 4 bits
CPU clock
Standby
control
DD
IC
Note 3
PP
)
(V
SP
SBS
BANK
V
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Bit sequential
buffer (16)
SS
RESETV
4
P00 - P03
P10 - P13
4
4
P20 - P23
P30 - P33
4
P30/MD0 -
( )
P33/MD3
P40 - P43
4
P50 - P53
4
4
P60 - P63
P70 - P73
4
2
P80, P81
Note 3
Notes 1. The program counter for the µPD750004 consists of 12 bits, 13 bits for the µPD750006 and
µPD750008, and 14 bits for the µPD75P0016.
2. The ROM capacity depends on the product.
3. ( ) : µPD75P0016
5
µPD750008 USER'S MANUAL
1.5 PIN CONFIGURATION (TOP VIEW)
(1) 42-pin plastic shrink DIP (600 mil)
µPD750004CU-XXX
µPD750006CU-XXX
µPD750008CU-XXX
µPD75P0016CU
XT1
XT2
RESET
X1
X2
P33 (/MD3)
P32 (/MD2)
P31 (/MD1)
P30 (/MD0)
P81
P80
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT4/P00
TI0/P13
INT2/P12
INT1/P11
INT0/P10
Note
PP
)
IC (V
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DD
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
P40
P41
P42
P43
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
Note Connect IC (VPP) to VDD, keeping the wiring as short as possible.
Remark ( ) : µPD75P0016.
6
(2) 44-pin plastic QFP (10 x 10 mm)
µPD750004GB-XXX-3BS-MTX
µPD750006GB-XXX-3BS-MTX
µPD750008GB-XXX-3BS-MTX
µPD75P0016GB-3BS-MTX
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
P53
P52
P51
P50
1
2
3
4
5
6
7
8
9
10
11
Note
)
PP
DD
P10/INT0
P11/INT1
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
V
IC (V
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
P12/INT2
NC
33
32
31
30
29
28
27
26
25
24
23
CHAPTER 1 GENERAL
P13/TI0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P80
P81
P30 (/MD0)
P31 (/MD1)
P32 (/MD2)
P33 (/MD3)
NC
P43
P42
P41
P40
SS
V
XT1
XT2
X1
RESET
X2
Note Connect IC (VPP) to VDD, keeping the wiring as short as possible.
Remark ( ) : µPD75P0016.
7
µPD750008 USER'S MANUAL
Pin name
P00-P03 : Port 0 RESET : Reset input
P10-P13 : Port 1 TI0 : Timer input 0
P20-P23 : Port 2 PTO0, 1 : Programmable timer output 0, 1
P30-P33 : Port 3 BUZ : Buzzer clock
P40-P43 : Port 4 PCL : Programmable clock
P50-P53 : Port 5 INT0, 1, 4 : External vectored interrupt 0, 1, 4
P60-P63 : Port 6 INT2 : External test input 2
P70-P73 : Port 7 X1, 2 : Main system clock oscillation 1, 2
P80-P81 : Port 8 XT1, 2 : Subsystem clock oscillation 1, 2
KR0-KR7: Key return NC : No connection
SCK : Serial clock IC : Internally connected
SI : Serial input V
SO : Serial output V
SB0, 1 : Serial bus 0, 1 V
DD
SS
PP
: Positive power supply
: Ground
: Programming power supply
MD0-MD3 : Mode selection 0 - 3
8
CHAPTER 2 PIN FUNCTIONS
2.1 PIN FUNCTIONS OF THE µPD750008
CHAPTER 2 PIN FUNCTIONS
Table 2-1. Digital I/O Port Pins (1/2)
Pin used Function circuit
Input/
output
Also
as
8 bit Upon
I/O reset
P00 Input INT4 4-bit input port (PORT0). x Input B
P01 I/O SCK For P01 to P03, built-in pull-up resistors F -A
P02 I/O SO/SB0 can be connected by software in units of F -B
P03 I/O SI/SB1 3 bits. M -C
P10 Input INT0 4-bit input port (PORT1). x Input B -C
P11 INT1 Built-in pull-up resistors can be connected
P12 INT2 by software in units of 4 bits. Only the
P13 TI0 P10/INT0 pin is provided with noise
elimination function.
P20 I/O PTO0 4-bit I/O port (PORT2). x Input E-B
P21 PTO1 Built-in pull-up resistors can be connected
P22 PCL by software in units of 4 bits.
P23 BUZ
P30
P31
P32
P33
Note 2
Note 2
Note 2
Note 2
I/O (MD0)
(MD1)
(MD2)
(MD3)
Note 3
Note 3
Note 3
Note 3
Programmable 4-bit I/O port (PORT3). x Input E-B
I/O can be specified bit by bit.
Built-in pull-up resistors can be connected
by software in units of 4 bits.
I/O
type
2
Note 1
Notes 1. I/O circuits enclosed in circles have a Schmitt-triggered input.
2. An LED can be driven directly.
3. ( ): µPD75P0016
9
µPD750008 USER'S MANUAL
Table 2-1. Digital I/O Port Pins (2/2)
*
*
*
*
Pin
P40- I/O — N-ch open-drain 4-bit I/O port (PORT4). O High level (when M-D
Note 2, 4
P43
P50- I/O — N-ch open-drain 4-bit I/O port (PORT5). O High level (when M-D
Note 2, 4
P53
P60 I/O KR0 Programmable 4-bit I/O port (PORT6). O Input F -A
P61 KR1 I/O can be specified bit by bit.
P62 KR2 Built-in pull-up resistors can be
P63 KR3 connected by software in units of 4 bits.
P70 I/O KR4 4-bit I/O port (PORT7). Input F -A
P71 KR5 Built-in pull-up resistors can be
P72 KR6 connected by software in units of
P73 KR7 4 bits.
P80 I/O — 2-bit input port (PORT8). x Input E-B
P81 — Built-in pull-up resistors can be
Input
output
Also
used Function circuit
as
Withstand voltage is 13 V in open-drain a pull-up resistor (M-E)
mode. is provided) or
A pull-up resistor can be provided bit high impedance
Note 5
Note 5
.
.
by bit (mask option)
Data input/output pins for writing/
verifying (lower 4 bits of program
memory (PROM).
Withstand voltage is 13 V in open-drain a pull-up resistor (M-E)
mode. is provided) or
A pull-up resistor can be provided bit high impedance
by bit (mask option)
Data input/output pins for writing/
verifying (higher 4 bits of program
memory (PROM).
connected by software in units of 2 bits.
8 bit Upon
I/O reset
I/O
type
Note 1
Note 3
Note 3
*
*
Notes 1. I/O circuits enclosed in circles have a Schmitt-triggered input.
2. An LED can be driven directly.
3. ( ): µPD75P0016
4. When pull-up resistors that can be specified with the mask option are not
incorporated (when pins are used as N-ch open-drain input ports), the input leak low
current increases when an input instruction or bit operation instruction is executed.
5. These pins of the µPD75P0016 are not provided with pull-up resistors by mask option, and are
always open.
10
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