NEC PD7564A, PD7564AA Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD7564A, 7564A(A)

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The μPD7564A is a 4-bit single-chip microcomputer with a small number of ports in a small package, which is of low-order models, μPD7554 and 7564 sub-series in the μPD7500 series. With an on-chip serial interface, it performs efficient dispersion processing of a system as a sub-CPU for the 75X series or 78k series.

The μPD7564A has outputs to directly drive a triac and LEDs and allows selection among many types of input/ output circuits using their respective mask options, sharply reducing the number of external circuits required.

Details of functions are described in the User’s Manual shown below. Be sure to read in design.

μPD7554, 7564 User’s Manual: IEM-1111D

FEATURES

∙47 types of instructions (Subset of μPD7500H SET B)

∙Instruction cycle

Ceramic oscillation : 2.86 μs

(in operation at 700 kHz, 5 V)

∙Program memory (ROM) capacity: 1024 × 8 bits

∙Data memory (RAM) capacity: 64 × 4 bits

∙Test source: One external source and two internal sources

∙8-bit timer/event counter

∙15 I/O lines (Total output current of all pins: 100 mA)

•Can directly drive a triac and a LED: P80 to P82

•Can directly drive LEDs: P100 to P103 and P110 to P113

•Mask option function provided for every port

APPLICATIONS

μPD7564A : PPCs, printers, VCRs, audio equipments, etc.

μPD7564A(A) : Automotive and transportation equipments, etc.

∙8-bit serial interface

∙Standby (STOP/HALT) function

∙Low supply voltage data retaining function for data memory

∙Built-in ceramic oscillator for system clock

∙Low power dissipation

∙Single power supply (2.7 to 6.0 V)

PIN CONFIGURATION (TOP VIEW)

P00/INT0	1		20	VSS
P01/SCK	2		19	P113
P02/SO	3		18	P112
P03/SI	4	μ	17	P111
P80	5	PD7564A	16	P110
P81	6		15	P103
P82	7		14	P102
CL2	8		13	P101
CL1	9		12	P100
VDD	10		11	RESET

The quality grade and absolute maximum ratings of the μPD7564A and the μPD7564A(A) differ. Except where specifically noted, explanations here concern the μPD7564A as a representative product. If you are using the μPD7564A(A), use the information presented here after the checking the functional differences.

The information in this document is subject to change without notice.

Document No.	IC-2401C	The mark shows major revised points.
(O. D. No.	IC-7834C)
Date Published December 1994 P		©		1994
Printed in Japan

μPD7564A, 7564A(A)

ORDERING INFORMATION

	Ordering Code	Package	Quality Grade
	μPD7564ACS-×××	20-pin plastic shrink DIP (300 mil)	Standard
	μPD7564AG-×××	20-pin plastic SOP (300 mil)	Standard
	μPD7564ACS(A)-×××	20-pin plastic shrink DIP (300 mil)	Special
	μPD7564AG(A)-×××	20-pin plastic SOP (300 mil)	Special

Caution Be sure to specify a mask option when ordering this device.

Remarks "×××" is a ROM code number.

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

					P01/SCK	P03/SI
				INT0	P02/SO
P00/INT0	CLOCK	CP	TIMER/EVENT	TEST	SERIAL
	CONTROL		COUNTER	CONTROL	INTERFACE
	CL

PROGRAM COUNTER (10)

C

A (4)

ALU

GENERAL REGISTERS

PROGRAM MEMORY

H (2)

L (4)

1024 × 8 BITS

INSTRUCTION

STACK POINTER (6)

DECODER

CL

φ

DATA MEMORY

SYSTEM

STANDBY

64 × 4 BITS

CLOCK

CONTROL

GENERATOR

CL1

CL2

VDD

VSS

RESET

3

PD7564Aμ OF DIAGRAM BLOCK

PORT0

BUFFER 4 P00–P03

PORT8

LATCH 3 P80–P82

BUFFER

PORT10

LATCH 4 P100–P103

BUFFER

PORT11

LATCH 4 P110–P113

BUFFER

7564A(A) PD7564A,μ

μPD7564A, 7564A(A)

	CONTENTS
1. PIN FUNCTIONS .........................................................................................................................................		6
1.1	PORT FUNCTIONS ...............................................................................................................................................	6
1.2	OTHER THAN PORTS ..........................................................................................................................................	6
1.3	PIN MASK OPTION ..............................................................................................................................................	7
1.4	CAUTION ON USE OF P00/INT0 PIN AND RESET PIN ...................................................................................	7
1.5	PIN INPUT/OUTPUT CIRCUITS ..........................................................................................................................	8
1.6	RECOMMENDED CONNECTION OF UNUSED μPD7564A PINS ..................................................................	11
1.7	OPERATION OF INPUT/OUTPUT PORTS .......................................................................................................	11

2. INTERNAL BLOCK FUNCTIONS ............................................................................................................		13
2.1	PROGRAM COUNTER (PC): 10 BITS ................................................................................................................	13
2.2	STACK POINTER (SP): 6 BITS ..........................................................................................................................	14
2.3	PROGRAM MEMORY (ROM): 1024 WORDS × 8 BITS ...................................................................................	15
2.4	GENERAL REGISTER .........................................................................................................................................	15
2.5	DATA MEMORY (RAM): 64 × 4 BITS ...............................................................................................................	16
2.6	ACCUMULATOR (A): 4 BITS .............................................................................................................................	17
2.7	ARITHMETIC LOGIC UNIT (ALU): 4 BITS ........................................................................................................	17
2.8	PROGRAM STATUS WORD (PSW): 4 BITS ....................................................................................................	17
2.9	SYSTEM CLOCK GENERATOR .........................................................................................................................	18
2.10	CLOCK CONTROL CIRCUIT ...............................................................................................................................	19
2.11	TIMER/EVENT COUNTER .................................................................................................................................	20
2.12	SERIAL INTERFACE ...........................................................................................................................................	21
2.13	TEST CONTROL CIRCUIT ..................................................................................................................................	23

3. STANDBY FUNCTIONS ...........................................................................................................................		25
3.1	STOP MODE ........................................................................................................................................................	25
3.2	CANCELLING THE HALT MODE .......................................................................................................................	25
3.3	CANCELLING STOP MODE BY RESET INPUT ................................................................................................	26
3.4	CANCELLING HALT MODE BY TEST REQUEST FLAG .................................................................................	26
3.5	CANCELLING HALT MODE BY RESET INPUT ................................................................................................	26

4.	RESET FUNCTIONS .................................................................................................................................	27
	4.1 DETAILS OF INITIALIZATION ...........................................................................................................................	27
5.	μPD7564A INSTRUCTION SET...............................................................................................................	28
6.	ELECTRICAL SPECIFICATIONS ..............................................................................................................	33
7.	CHARACTERISTICS CURVES ..................................................................................................................	40
8.	μPD7564A APPLIED CIRCUITS ...............................................................................................................	43
9.	PACKAGE INFORMATION .......................................................................................................................	45

4

μPD7564A, 7564A(A)

10.	RECOMMENDED PACKAGING PATTERN OF SOP (REFERENCE) .....................................................	49
11.	RECOMMENDED SOLDERING CONDITIONS.......................................................................................	50
APPENDIX A. COMPARISON BETWEEN SUB-SERIES PRODUCT FUNCTIONS.....................................		51
APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................		52
APPENDIX C. RELATED DOCUMENTS..........................................................................................................		54

5

μPD7564A, 7564A(A)

1. PIN FUNCTIONS

1.1PORT FUNCTIONS

Pin Name	Input/Output	Dual-Function			Function	After RESET	Input/Output
			Pin				Circuit
P00	Input		INT0				S
					4-bit input port (Port 0)
P01	Input/output		SCK			Input	X
					P00 serves also as a count clock (event pulse)
P02			SO				W
					input.
P03	Input		SI				S
					3-bit output port (Port 8)	High
P80 to P82	Output		––		High current (15 mA), middle-high voltage (9 V)		O
						impedance
					output
					4-bit I/O port (Port 10)	High
P100 to P103	Input/output		––		Middle-high current (10 mA), middle-high voltage
						impedance
					(9 V) input/output
						or	P
					4-bit I/O port (Port 11)
						high-level
P110 to P113	Input/output		––		Middle-high current (10 mA), middle-high voltage
						output
					(9 V) input/output

1.2OTHER THAN PORTS

Pin Name			Input/Output	Dual-Function	Function	After RESET	Input/Output
				Pin			Circuit
	INT0		Input	P00	Edge detection testable input pin (Rising edge)		S
	SCK		Input/output	P01	Serial clock Input/output pin	Input	X
	SO		Output	P02	Serial data output pin	Input	W
	SI		Input	P03	Serial data input pin	Input	S
	CL1				Connection pin for ceramic oscillation ceramic		––
	CL2				resonator
					System reset input pin (high-level active)
RESET					A pull-down resistor can be incorporated using		R
					the mask option.
	VDD				Positive power supply pin
	VSS				GND potential pin

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μPD7564A, 7564A(A)

1.3PIN MASK OPTION

Each pin is provided with the following mask options which can be selected for each bit according to the purpose:

Pin Name		Mask Options
P00	No internally provided resistor	Pull-down resistor internally provided Pull-up resistor internally provided
P01	No internally provided resistor	Pull-down resistor internally provided Pull-up resistor internally provided
P02	No internally provided resistor	Pull-down resistor internally provided Pull-up resistor internally provided
P03	No internally provided resistor	Pull-down resistor internally provided Pull-up resistor internally provided
P80	N-ch open-drain output	CMOS (push-pull) output
P81	N-ch open-drain output	CMOS (push-pull) output
P82	N-ch open-drain output	CMOS (push-pull) output
P100	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P101	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P102	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P103	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P110	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P111	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P112	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
P113	N-ch open-drain input/output	Push-pull input/output
	N-ch open-drain + pull-up resistor built-in input/output
RESET	Incorporating no pull-down resistor Incorporating a pull-down resistor

There is no mask option for PROM products. For more information, see the μPD75P64 Data Sheet (IC-2838).

1.4CAUTION ON USE OF P00/INT0 PIN AND RESET PIN

In addition to the functions shown in 1.1, 1.2 and 1.3, the P00/INT0 pin and RESET pin have a function for setting the test mode in which the internal operation of the μPD7564A is tested (IC test only).

When a potential greater than VSS is applied to either of these pins, the test mode is set. As a result, if noise exceeding VSS is applied during normal operation, the test mode will be entered and normal operation may be impeded.

If, for example, the routing of the wiring between the P00/INT0 pin and RESET pin is long, the above problem may occur as the result of inter-wiring noise between these pins.

Therefore, wiring should be carried out so as to suppress inter-wiring noise as far as possible. If it is not possible to suppress noise, anti-noise measures should be taken using external parts as shown in the figures below.

• Connection of diode with small VF between P00/

• Connection of capacitor between P00/INT0/

INT4/RESET pin and VSS

RESET pin and VSS

VDD

VDD

VDD

VDD

P00/INT0, RESET

P00/INT0, RESET

Diode

with

Small VF

VSS

VSS

7

μPD7564A, 7564A(A)

1.5PIN INPUT/OUTPUT CIRCUITS

This section presents the input/output circuit for each pin of the μPD7564A in a partly simplified format:

(1) Type A (for Type W)

VDD

P–ch

IN

N–ch

Forming an input buffer conformable to the CMOS specification

(2) Type D (for Types W and X)

VDD

data

P–ch

OUT

output	N–ch
disable

Forming a push-pull output which becomes high impedance (with both P-ch and N-ch off) in response to RESET input

8

μPD7564A, 7564A(A)

(3) Type O

	VDD
data	P–ch
	Mask Option
	OUT
output	N–ch (Middle-High Voltage,
disable	High-Current)

(4) Type P

VDD

data

P–ch

	Mask Option
	IN/OUT
output	N–ch (Middle-High Voltage,
disable	High-Current)

Middle-High Input Buffer

(5) Type R

Mask Option

9

μPD7564A, 7564A(A)

(6) Type S

VDD

Mask Option

IN

(7) Type W

data
Type D	IN/OUT
output	VDD
disable
	Mask Option
Type A

(8) Type X

data
Type D	IN/OUT
output	VDD
disable
	Mask Option

10

μPD7564A, 7564A(A)

1.6RECOMMENDED CONNECTION OF UNUSED μPD7564A PINS

Pin	Recommended Connection
P00/INT0	Connect to VSS.
P01 to P03	Connect to VSS or VDD.
P80 to P82	Leave open.
P100 to P103	Input state : Connect to VSS or VDD.
P110 to P113	Output state: Leave open.

1.7OPERATION OF INPUT/OUTPUT PORTS

(1) P00 to P03 (Port 0)

The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input, P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output.

To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See 2.10 “CLOCK CONTROL CIRCUIT” for details.)

To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1.

The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2 and SM1) of the shift mode register. See 2.12 “SERIAL INTERFACE” for details.

Even though this port operates using any function other than the port function, execution of the port input instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time.

(2) P80 to P83 (Port 8)

The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin.

The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs it to pins P80 to P83.

The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P80 to P82.

For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch opendrain output.

The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a different supply voltage because the output buffer has a dielectric strength of 9 V.

11

μPD7564A, 7564A(A)

(3) P100 to P103 (Port 10) and P110 to P113 (Port 11): Quasi-bidirectional input/output

P100 to P103 are 4-bit I/O pins which form the port 10 (4-bit I/O port with an output latch). P110 to P113 are 4- bit I/O pins which form the port 11 (4-bit I/O port with an output latch).

The port output instruction (OPL) latches the content of the accumulator to the output latch and outputs it to the 4-bit pins.

The data written once in the output latch and the output buffer state are retained until the output instruction to operate the port 10 or 11 is executed or the RESET signal is input. Even though an input instruction is executed for the port 10 or 11, the states of both the output latch and output buffer do not change.

The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P100 to P103 and P110 to P113. The input/output format of each of the ports 10 and 11 can be selected from among the N-ch open-drain input/ output, N-ch open-drain + pull-up resistor built-in input/output, and CMOS (push-pull) input/output by their

respective mask options.

When the CMOS (push-pull) input/output is selected, the port cannot return to the input mode once the output instruction is executed. However, the states of the pins of the port can be checked by reading via the port input instruction (IPL).

When one of the other two formats is selected, the port can enter the input mode to load the data on the 4-bit line to the accumulator (as a quasi-bidirectional port) when the port receives high level output. Select each type of the input/output format to meet the use of the port:

CMOS input/output

i)Uses all 4 bits of the port as input ports.

ii)Uses pins of the port as output pins not requiring middle withstand voltage output.

N-ch open-drain input/output

i)Uses pins of the port as I/O pins requiring a middle withstand voltage dielectric strength.

ii)Uses input pins of the port which also has output pins.

iii)Uses each pin of the port for both input and output by switching them over.

N-ch open-drain + pull-up resistor built-in input/output

i)Uses input pins of the port which also has output pins, that require a pull-up resistor.

ii)Uses each pin of the port for both input and output by switching them over. This requires a pull-up resistor.

Caution	Before using input pins in the case of or , write 1 in the output latch to turn the N-ch transistor
	off.

12

μPD7564A, 7564A(A)

2. INTERNAL BLOCK FUNCTIONS

2.1PROGRAM COUNTER (PC): 10 BITS

The program counter is a 10-bit binaryc ounter to retain program memory (ROM) address information.

Fig. 2-1 Program Counter Configuration

PC9	PC8	PC7	PC6	PC5	PC4	PC3	PC2	PC1	PC0	PC

When one instruction is executed, usually the program counter is incremented by the number of bytes of the instruction.

When the call instruction is executed, the PC is loaded with a nkew call address after the stack memory saves the current contents (return address) of the PC. When the return instruction is executed, the content (return address) of the stack memory is loaded onto the PC. When the jump instruction is executed, the immediate data identifying the destination of the jump is loaded to all or some of bits of the PC.

When a skip occurs, the PC is incremented by 2 or 3 during the machine cycle depending on the number of bytes in the next instruction.

When the RESET signal is input, all the bits of the PC are cleared to zero.

13

μPD7564A, 7564A(A)

2.2STACK POINTER (SP): 6 BITS

The stack pointer is a 6-bit register which retains head address information of the stack memory (LIFO type) which is a part of the data memory.

Fig. 2-2 Stack Pointer Configuration

SP5	SP4	SP3	SP2	SP1	SP0	SP

The stack pointer is decremented when the call instruction is executed. It is incremented when the return instruction is executed.

To determine the stack area, initialize the SP using the TAMSP instruction. Note that bit SP0 is loaded with 0 unconditionally when the TAMSP instruction is executed. Set the SP to the value of “the highest address of the stack area + 1” because the stack operation starts with decrementation of the SP.

When the highest address of the stack area is 3FH which is the highest address of the data memory, the initial value of SP5-0 must be 00H. For emulation using the μPD7500H (EVAKIT-7500B), set the data to be used for AM when executing the TAMSP instruction.

Fig. 2-3 In Execution of TAMSP Instruction

A3

A2

A1

A0

(HL)3

(HL)2

(HL)1

(HL)0

0

SP5

SP4

SP3

SP2

SP1

SP0

Note that the contents of the SP cannot be read.

Caution Be sure to set the SP at the initial stage of the program execution because the SP becomes undefined

when the RESET signal is input.

Example LHLI	00H
LAI	0
ST
LAI	4
TAMSP	;SP = 40H

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μPD7564A, 7564A(A)

2.3PROGRAM MEMORY (ROM): 1024 WORDS × 8 BITS

The program memory is a mask programmable ROM of 1024 word × 8 bits configuration. It is addressed by the program counter.

The program memory stores programs.

Address 000H is the reset start address.

Fig. 2-4 Program Memory Map

(0) 000H

Reset Start

(1023) 3FFH

2.4GENERAL REGISTER

General registers H (with two bits) and L (with four bits) operate individually. They also form a pair register HL (H: high order and L: low order) to serve as a data pointer for addressing the data memory.

Fig. 2-5 General Register Configuration

1	0	3		0
	H			L

The L register is also used to specify I/O ports and the mode register when an input/output instruction (IPL or OPL) is executed. It also used to specify the bits of a port when the SPBL or RPBL instruction is executed.

15

μPD7564A, 7564A(A)

2.5DATA MEMORY (RAM): 64 × 4 BITS

The data memory is a static RAM of 64 word × 4 bits configuration. It is used as the area to store or stack processed data. The data memory may be processed in 8-bit units when paired with the accumulator.

Fig. 2-6 Data Memory Map

( 0 ) 00H

64 Words × 4 Bits

(63) 3FH

The data memory is addressed in the following three ways:

•Direct: Direct addressing based on immediate data of an instruction

•Register indirect: Indirect addressing according to the contents of the pair register HL (including automatic incrementation and decrementation)

•Stack: Indirect addressing according to the contents of the stack pointer (SP)

An arbitrary space of the data memory is available as stack memory. The boundary of the stack area is specified when the TAMSP instruction initializes the SP. After that, the stack area is accessed automatically by the call or return instruction.

After the call instruction is executed, the content of the PC and PSW is stored in the order shown in the following diagram:

		Stack Area
	3				0
SP – 4
	0	0		PC9	PC8
SP – 3
			PSW*
SP – 2
		PC3 – PC0
SP – 1
		PC7 – PC4				* Bit 1 is fixed at 0.

When the return instruction is executed, the content of the PSW is not restored while those of the PC are restored. Data in the data memory is retained at a low supply voltage in the STOP mode.

16

μPD7564A, 7564A(A)

2.6ACCUMULATOR (A): 4 BITS

The accumulator is a 4-bit register which plays a major role in many types of arithmetic operations. The accumulator may be processed in 8-bit units when paired with the data memory addressed by the pair register HL.

Fig. 2-7 Accumulator Configuration

A3	A2	A1	A0	A

2.7ARITHMETIC LOGIC UNIT (ALU): 4 BITS

The arithmetic logic unit is a 4-bit arithmetic circuit to perform arithmetic and bit processing such as binary addition, logical operation, incrementation, decrementation, and comparison.

2.8PROGRAM STATUS WORD (PSW): 4 BITS

The program status word consists of skip flags (SK1 and SK0) and a carry flag (C). Bit 1 of the PSW is fixed at 0.

Fig. 2-8 Program Status Word Configuration

3	2	1	0
SK1	SK0	0	C	PSW

(1) Skip flags (SK1 and SK0)

Skip flags store the following skip status:

•Stacking by the LAI instruction

•Stacking by the LHLI instruction

•Skip condition establishment by any instruction other than stack instructions

The skip flags are set and reset automatically when respective instructions are executed.

(2) Carry flag (C)

The carry flag is set to 1 when a carry from bit 3 of the ALU occurs when the add instruction (ACSC) is executed. The flag is reset to 0 when the carry does not occur. The SC and RC instructions respectively set and reset the carry flag. The SKC instruction tests the contents of the flag.

The content of the PSW are automatically stored in the stack area when the call instruction is executed. It cannot be restored by the return inhstruction.

When the RESET signal is input, SK1 and SK0 are both cleared to zero and C becomes undefined.

17