NEC PD7564A, PD7564AA Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD7564A, 7564A(A)

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The µPD7564A is a 4-bit single-chip microcomputer with a small number of ports in a small package, which is

of low-order models,

forms efficient dispersion processing of a system as a sub-CPU for the 75X series or 78k series.

The µPD7564A has outputs to directly drive a triac and LEDs and allows selection among many types of input/

output circuits using their respective mask options, sharply reducing the number of external circuits required.

Details of functions are described in the User’s Manual shown below. Be sure to read in design.

PD7554 and 7564 sub-series in the µPD7500 series. With an on-chip serial interface, it per-

PD7554, 7564 User’s Manual: IEM-1111D

FEATURES

• 47 types of instructions

(Subset of

• Instruction cycle

Ceramic oscillation : 2.86 µs

• Program memory (ROM) capacity: 1024 × 8 bits

• Data memory (RAM) capacity: 64 × 4 bits

• Test source: One external source and two internal

sources

• 8-bit timer/event counter

• 15 I/O lines (Total output current of all pins: 100 mA)

• Can directly drive a triac and a LED: P80 to P82

• Can directly drive LEDs: P100 to P103 and P110 to

P113

• Mask option function provided for every port

PD7500H SET B)

(in operation at 700 kHz, 5 V)

APPLICATIONS

PD7564A : PPCs, printers, VCRs, audio equipments,

etc.

PD7564A(A) : Automotive and transportation equip-

ments, etc.

• 8-bit serial interface

• Standby (STOP/HALT) function

• Low supply voltage data retaining function for data

memory

• Built-in ceramic oscillator for system clock

• Low power dissipation

• Single power supply (2.7 to 6.0 V)

PIN CONFIGURATION (TOP VIEW)

P00/INT0

P01/SCK

P02/SO

P03/SI

P80

P81

P82

CL2

CL1

PD7564A

P113

P112

P111

P110

P103

P102

P101

P100

RESET

★

The quality grade and absolute maximum ratings of the

Except where specifically noted, explanations here concern the

If you are using the

tional differences.

Document No. IC-2401C

(O. D. No. IC-7834C) Date Published December 1994 P Printed in Japan

PD7564A and the µPD7564A(A) differ.

PD7564A as a representative product.

PD7564A(A), use the information presented here after the checking the func-

The information in this document is subject to change without notice.

The mark ★ shows major revised points.

1994

PD7564A, 7564A(A)

ORDERING INFORMATION

Ordering Code Package Quality Grade

PD7564ACS-××× 20-pin plastic shrink DIP (300 mil) Standard

PD7564AG-××× 20-pin plastic SOP (300 mil) Standard

★ ★

PD7564ACS(A)-××× 20-pin plastic shrink DIP (300 mil) Special

PD7564AG(A)-××× 20-pin plastic SOP (300 mil) Special

Caution Be sure to specify a mask option when ordering this device.

Remarks "×××" is a ROM code number.

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

INT0

BLOCK DIAGRAM OF

P01/SCK P03/SI

P02/SO

P00/INT0

PROGRAM COUNTER (10)

PROGRAM MEMORY

1024 × 8 BITS

SYSTEM CLOCK GENERATOR

CLOCK CONTROL

STANDBY CONTROL

TIMER/EVENT COUNTER

INSTRUCTION DECODER

ALU

TEST CONTROL

GENERAL REGISTERS

H (2) L (4)

STACK POINTER (6)

DATA MEMORY

SERIAL INTERFACE

64 × 4 BITS

PD7564A

PORT0

A (4)C

BUFFER

PORT8 LATCH BUFFER

PORT10 LATCH BUFFER

PORT11 LATCH BUFFER

4 P00–P03

3 P80–P82

4 P100–P103

4 P110–P113

PD7564A, 7564A(A)

CL1 CL2

RESETV

PD7564A, 7564A(A)

CONTENTS

1. PIN FUNCTIONS ......................................................................................................................................... 6

1.1 PORT FUNCTIONS ............................................................................................................................................... 6

1.2 OTHER THAN PORTS .......................................................................................................................................... 6

1.3 PIN MASK OPTION .............................................................................................................................................. 7

1.4 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN ................................................................................... 7

1.5 PIN INPUT/OUTPUT CIRCUITS .......................................................................................................................... 8

1.6 RECOMMENDED CONNECTION OF UNUSED

1.7 OPERATION OF INPUT/OUTPUT PORTS ....................................................................................................... 11

PD7564A PINS .................................................................. 11

2. INTERNAL BLOCK FUNCTIONS ............................................................................................................ 13

2.1 PROGRAM COUNTER (PC): 10 BITS ................................................................................................................ 13

2.2 STACK POINTER (SP): 6 BITS .......................................................................................................................... 14

2.3 PROGRAM MEMORY (ROM): 1024 WORDS × 8 BITS ................................................................................... 15

2.4 GENERAL REGISTER ......................................................................................................................................... 15

2.5 DATA MEMORY (RAM): 64 × 4 BITS ............................................................................................................... 16

2.6 ACCUMULATOR (A): 4 BITS ............................................................................................................................. 17

2.7 ARITHMETIC LOGIC UNIT (ALU): 4 BITS ........................................................................................................ 17

2.8 PROGRAM STATUS WORD (PSW): 4 BITS .................................................................................................... 17

2.9 SYSTEM CLOCK GENERATOR ......................................................................................................................... 18

2.10 CLOCK CONTROL CIRCUIT ............................................................................................................................... 19

2.11 TIMER/EVENT COUNTER ................................................................................................................................. 20

2.12 SERIAL INTERFACE ........................................................................................................................................... 21

2.13 TEST CONTROL CIRCUIT .................................................................................................................................. 23

3. STANDBY FUNCTIONS ........................................................................................................................... 25

3.1 STOP MODE ........................................................................................................................................................ 25

3.2 CANCELLING THE HALT MODE ....................................................................................................................... 25

3.3 CANCELLING STOP MODE BY RESET INPUT ................................................................................................ 26

3.4 CANCELLING HALT MODE BY TEST REQUEST FLAG ................................................................................. 26

3.5 CANCELLING HALT MODE BY RESET INPUT ................................................................................................ 26

4. RESET FUNCTIONS ................................................................................................................................. 27

4.1 DETAILS OF INITIALIZATION ........................................................................................................................... 27

5.µPD7564A INSTRUCTION SET............................................................................................................... 28

6. ELECTRICAL SPECIFICATIONS .............................................................................................................. 33

7. CHARACTERISTICS CURVES .................................................................................................................. 40

8.µPD7564A APPLIED CIRCUITS ............................................................................................................... 43

9. PACKAGE INFORMATION ....................................................................................................................... 45

PD7564A, 7564A(A)

10. RECOMMENDED PACKAGING PATTERN OF SOP (REFERENCE) ..................................................... 49

11. RECOMMENDED SOLDERING CONDITIONS....................................................................................... 50

APPENDIX A. COMPARISON BETWEEN SUB-SERIES PRODUCT FUNCTIONS..................................... 51

APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................ 52

APPENDIX C. RELATED DOCUMENTS.......................................................................................................... 54

★

1. PIN FUNCTIONS

1.1 PORT FUNCTIONS

PD7564A, 7564A(A)

Pin Name Input/Output

P00 Input INT0 S

P01

P02 SO W

P03 Input SI S

P80 to P82 Output –– O

P100 to P103 Input/output ––

P110 to P113 Input/output ––

Input/output

Dual-Function

Pin Circuit

SCK

4-bit input port (Port 0)

P00 serves also as a count clock (event pulse)

input.

3-bit output port (Port 8)

High current (15 mA), middle-high voltage (9 V)

output

4-bit I/O port (Port 10)

Middle-high current (10 mA), middle-high voltage

(9 V) input/output

4-bit I/O port (Port 11)

Middle-high current (10 mA), middle-high voltage

(9 V) input/output

Function After RESET

Input

High

impedance

High

impedance

high-level

output

Input/Output

1.2 OTHER THAN PORTS

Pin Name Input/Output

INT0 Input P00 Edge detection testable input pin (Rising edge) S

SCK Input/output P01 Serial clock Input/output pin Input X

SO Output P02 Serial data output pin Input W

SI Input P03 Serial data input pin Input S

CL1

CL2

Dual-Function

Pin Circuit

Connection pin for ceramic oscillation ceramic

resonator

Function After RESET

Input/Output

––

System reset input pin (high-level active)

RESET R

VDD Positive power supply pin

VSS GND potential pin

A pull-down resistor can be incorporated using

the mask option.

PD7564A, 7564A(A)

1.3 PIN MASK OPTION

Each pin is provided with the following mask options which can be selected for each bit according to the purpose:

Pin Name Mask Options

P00 ➀ No internally provided resistor ➁ Pull-down resistor internally provided ➂ Pull-up resistor internally provided P01 ➀ No internally provided resistor ➁ Pull-down resistor internally provided ➂ Pull-up resistor internally provided P02 ➀ No internally provided resistor ➁ Pull-down resistor internally provided ➂ Pull-up resistor internally provided P03 ➀ No internally provided resistor ➁ Pull-down resistor internally provided ➂ Pull-up resistor internally provided P80 ➀ N-ch open-drain output ➁ CMOS (push-pull) output P81 ➀ N-ch open-drain output ➁ CMOS (push-pull) output P82 ➀ N-ch open-drain output ➁ CMOS (push-pull) output P100 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P101 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P102 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P103 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P110 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P111 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P112 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

P113 ➀ N-ch open-drain input/output ➁ Push-pull input/output

➂ N-ch open-drain + pull-up resistor built-in input/output

RESET ➀ Incorporating no pull-down resistor ➁ Incorporating a pull-down resistor

★

There is no mask option for PROM products. For more information, see the µPD75P64 Data Sheet (IC-2838).

1.4 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN

In addition to the functions shown in 1.1, 1.2 and 1.3, the P00/INT0 pin and RESET pin have a function for setting

the test mode in which the internal operation of the

When a potential greater than V

exceeding V

SS is applied during normal operation, the test mode will be entered and normal operation may be

SS is applied to either of these pins, the test mode is set. As a result, if noise

PD7564A is tested (IC test only).

impeded.

If, for example, the routing of the wiring between the P00/INT0 pin and RESET pin is long, the above problem

may occur as the result of inter-wiring noise between these pins.

Therefore, wiring should be carried out so as to suppress inter-wiring noise as far as possible. If it is not possible

to suppress noise, anti-noise measures should be taken using external parts as shown in the figures below.

• Connection of diode with small VF between P00/

INT4/RESET pin and V

Diode with

Small V

P00/INT0, RESET

• Connection of capacitor between P00/INT0/

RESET pin and V

P00/INT0, RESET

1.5 PIN INPUT/OUTPUT CIRCUITS

This section presents the input/output circuit for each pin of the

(1) Type A (for Type W)

PD7564A, 7564A(A)

PD7564A in a partly simplified format:

VDD

P–ch

N–ch

Forming an input buffer conformable to the CMOS specification

(2) Type D (for Types W and X)

data

output disable

P–ch

OUT

N–ch

Forming a push-pull output which becomes high impedance (with both P-ch and N-ch off) in response to

RESET input

(3) Type O

PD7564A, 7564A(A)

(4) Type P

data

output disable

data

P–ch

Mask Option

N–ch

P–ch

OUT

(Middle-High Voltage, High-Current)

Mask Option

(5) Type R

output disable

Middle-High Input Buffer

(Middle-High Voltage,

N–ch

High-Current)

Mask Option

IN/OUT

(6) Type S

(7) Type W

data

output

disable

Type D

Mask Option

PD7564A, 7564A(A)

IN/OUT

(8) Type X

data

output

disable

Type A

Type D

Mask Option

IN/OUT

Mask Option

PD7564A, 7564A(A)

1.6 RECOMMENDED CONNECTION OF UNUSED µPD7564A PINS

Pin Recommended Connection

P00/INT0 Connect to VSS.

P01 to P03 Connect to VSS or VDD.

P80 to P82 Leave open.

P100 to P103

P110 to P113

1.7 OPERATION OF INPUT/OUTPUT PORTS

(1) P00 to P03 (Port 0)

The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input,

P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output.

To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See 2.10 “CLOCK

CONTROL CIRCUIT” for details.)

To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1.

The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2

and SM1) of the shift mode register. See 2.12 “SERIAL INTERFACE” for details.

Even though this port operates using any function other than the port function, execution of the port input

instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time.

Input state : Connect to VSS or VDD.

Output state: Leave open.

(2) P80 to P83 (Port 8)

The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin.

The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs

it to pins P80 to P83.

The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P80 to P82.

For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch open-

drain output.

The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a

different supply voltage because the output buffer has a dielectric strength of 9 V.

PD7564A, 7564A(A)

(3) P100 to P103 (Port 10) and P110 to P113 (Port 11): Quasi-bidirectional input/output

P100 to P103 are 4-bit I/O pins which form the port 10 (4-bit I/O port with an output latch). P110 to P113 are 4-

bit I/O pins which form the port 11 (4-bit I/O port with an output latch).

The port output instruction (OPL) latches the content of the accumulator to the output latch and outputs it to the

4-bit pins.

The data written once in the output latch and the output buffer state are retained until the output instruction to

operate the port 10 or 11 is executed or the RESET signal is input. Even though an input instruction is executed for

the port 10 or 11, the states of both the output latch and output buffer do not change.

The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P100 to P103 and P110 to P113.

The input/output format of each of the ports 10 and 11 can be selected from among the N-ch open-drain input/

output, N-ch open-drain + pull-up resistor built-in input/output, and CMOS (push-pull) input/output by their

respective mask options.

When the CMOS (push-pull) input/output is selected, the port cannot return to the input mode once the output

instruction is executed. However, the states of the pins of the port can be checked by reading via the port input

instruction (IPL).

When one of the other two formats is selected, the port can enter the input mode to load the data on the 4-bit

line to the accumulator (as a quasi-bidirectional port) when the port receives high level output. Select each type of

the input/output format to meet the use of the port:

➀ CMOS input/output

i) Uses all 4 bits of the port as input ports.

ii) Uses pins of the port as output pins not requiring middle withstand voltage output.

➁ N-ch open-drain input/output

i) Uses pins of the port as I/O pins requiring a middle withstand voltage dielectric strength.

ii) Uses input pins of the port which also has output pins.

iii) Uses each pin of the port for both input and output by switching them over.

➂ N-ch open-drain + pull-up resistor built-in input/output

i) Uses input pins of the port which also has output pins, that require a pull-up resistor.

ii) Uses each pin of the port for both input and output by switching them over. This requires a pull-up resistor.

Caution Before using input pins in the case of ➁ or ➂ , write 1 in the output latch to turn the N-ch transistor

off.

PD7564A, 7564A(A)

2. INTERNAL BLOCK FUNCTIONS

2.1 PROGRAM COUNTER (PC): 10 BITS

The program counter is a 10-bit binaryc ounter to retain program memory (ROM) address information.

Fig. 2-1 Program Counter Configuration

PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC

When one instruction is executed, usually the program counter is incremented by the number of bytes of the

instruction.

When the call instruction is executed, the PC is loaded with a nkew call address after the stack memory saves

the current contents (return address) of the PC. When the return instruction is executed, the content (return address)

of the stack memory is loaded onto the PC. When the jump instruction is executed, the immediate data identifying

the destination of the jump is loaded to all or some of bits of the PC.

When a skip occurs, the PC is incremented by 2 or 3 during the machine cycle depending on the number of bytes

in the next instruction.

When the RESET signal is input, all the bits of the PC are cleared to zero.

PD7564A, 7564A(A)

2.2 STACK POINTER (SP): 6 BITS

The stack pointer is a 6-bit register which retains head address information of the stack memory (LIFO type) which

is a part of the data memory.

Fig. 2-2 Stack Pointer Configuration

SP5 SP4 SP3 SP2 SP1 SP0 SP

The stack pointer is decremented when the call instruction is executed. It is incremented when the return

instruction is executed.

To determine the stack area, initialize the SP using the TAMSP instruction. Note that bit SP0 is loaded with 0

unconditionally when the TAMSP instruction is executed. Set the SP to the value of “the highest address of the stack

area + 1” because the stack operation starts with decrementation of the SP.

When the highest address of the stack area is 3FH which is the highest address of the data memory, the initial

value of SP5-0 must be 00H. For emulation using the

when executing the TAMSP instruction.

Fig. 2-3 In Execution of TAMSP Instruction

PD7500H (EVAKIT-7500B), set the data to be used for AM

A3 A2 A1 A0 (HL)3(HL)2(HL)1(HL)

SP5 SP4 SP3 SP2 SP1 SP0

Note that the contents of the SP cannot be read.

Caution Be sure to set the SP at the initial stage of the program execution because the SP becomes undefined

when the RESET signal is input.

Example LHLI 00H

LAI 0

LAI 4

TAMSP ;SP = 40H

PD7564A, 7564A(A)

2.3 PROGRAM MEMORY (ROM): 1024 WORDS × 8 BITS

The program memory is a mask programmable ROM of 1024 word × 8 bits configuration. It is addressed by the

program counter.

The program memory stores programs.

Address 000H is the reset start address.

Fig. 2-4 Program Memory Map

(0) 000H

(1023) 3FFH

2.4 GENERAL REGISTER

General registers H (with two bits) and L (with four bits) operate individually. They also form a pair register HL

(H: high order and L: low order) to serve as a data pointer for addressing the data memory.

Fig. 2-5 General Register Configuration

Reset Start

The L register is also used to specify I/O ports and the mode register when an input/output instruction (IPL or

OPL) is executed. It also used to specify the bits of a port when the SPBL or RPBL instruction is executed.

PD7564A, 7564A(A)

2.5 DATA MEMORY (RAM): 64 × 4 BITS

The data memory is a static RAM of 64 word × 4 bits configuration. It is used as the area to store or stack processed

data. The data memory may be processed in 8-bit units when paired with the accumulator.

Fig. 2-6 Data Memory Map

( 0 ) 00H

64 Words × 4 Bits

(63) 3FH

The data memory is addressed in the following three ways:

• Direct: Direct addressing based on immediate data of an instruction

• Register indirect: Indirect addressing according to the contents of the pair register HL (including automatic

incrementation and decrementation)

• Stack: Indirect addressing according to the contents of the stack pointer (SP)

An arbitrary space of the data memory is available as stack memory. The boundary of the stack area is specified

when the TAMSP instruction initializes the SP. After that, the stack area is accessed automatically by the call or return

instruction.

After the call instruction is executed, the content of the PC and PSW is stored in the order shown in the following

diagram:

Stack Area

SP – 4

SP – 3

SP – 2

SP – 1

0 0 PC9 PC8

PSW*

PC3 – PC0

PC7 – PC4

* Bit 1 is fixed at 0.

When the return instruction is executed, the content of the PSW is not restored while those of the PC are restored.

Data in the data memory is retained at a low supply voltage in the STOP mode.

PD7564A, 7564A(A)

2.6 ACCUMULATOR (A): 4 BITS

The accumulator is a 4-bit register which plays a major role in many types of arithmetic operations. The

accumulator may be processed in 8-bit units when paired with the data memory addressed by the pair register HL.

Fig. 2-7 Accumulator Configuration

A3 A2 A1 A0 A

2.7 ARITHMETIC LOGIC UNIT (ALU): 4 BITS

The arithmetic logic unit is a 4-bit arithmetic circuit to perform arithmetic and bit processing such as binary

addition, logical operation, incrementation, decrementation, and comparison.

2.8 PROGRAM STATUS WORD (PSW): 4 BITS

The program status word consists of skip flags (SK1 and SK0) and a carry flag (C). Bit 1 of the PSW is fixed at 0.

Fig. 2-8 Program Status Word Configuration

3210

SK1 SK0 0 C PSW

(1) Skip flags (SK1 and SK0)

Skip flags store the following skip status:

• Stacking by the LAI instruction

• Stacking by the LHLI instruction

• Skip condition establishment by any instruction other than stack instructions

The skip flags are set and reset automatically when respective instructions are executed.

(2) Carry flag (C)

The carry flag is set to 1 when a carry from bit 3 of the ALU occurs when the add instruction (ACSC) is executed.

The flag is reset to 0 when the carry does not occur. The SC and RC instructions respectively set and reset the carry

flag. The SKC instruction tests the contents of the flag.

The content of the PSW are automatically stored in the stack area when the call instruction is executed. It cannot

be restored by the return inhstruction.

When the RESET signal is input, SK1 and SK0 are both cleared to zero and C becomes undefined.

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