NEC PD178004A, PD178006A, PD178016A, PD178018A Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD178004A, 178006A, 178016A, 178018A

8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD178004A, 178006A, 178016A and 178018A are 8-bit single-chip CMOS microcontrollers that incorporate

hardware for digital tuning systems.

The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for system control.

The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface, power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter.

The µPD178P018A, one-time PROM or EPROM versions which can be operated in the same supply voltage range as for the mask ROM versions, and various development tools, are also available.

For more information on functions, refer to the following User’s Manuals. Be sure to read them when designing.

PD178018A Subseries User’s Manual: to be prepared

78K/0 Series User’s Manual Instruction: U12326E

FEATURES

• Internal high-capacity ROM and RAM

Items Program Memory Data Memory

Product Name ROM Internal High-Speed RAM Buffer RAM Internal Expanded RAM

PD178004A 32 Kbytes 1 024 bytes 32 bytes Not provided

PD178006A 48 Kbytes

PD178016A 2 048 bytes

PD178018A 60 Kbytes

• Instruction Cycle: 0.44 µs (4.5-MHz crystal oscillator used)

• Large array of on-chip peripheral hardware

General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits.

• On-chip hardware for a PLL frequency synthesizer.

Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.

• Vector interrupt sources: 17

• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)

VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower) VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)

The information in this document is subject to change without notice.

Document No. U12641EJ1V0DS00 (1st Edition) Date Published July 1997 N Printed in Japan

1997

PD178004A, 178006A, 178016A, 178018A

APPLICATIONS

Car stereo, home stereo systems.

ORDERING INFORMATION

Part Number Package

PD178004AGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

PD178006AGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

PD178016AGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

PD178018AGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

Remark ××× denotes the ROM code number. Also, the ROM code number becomes E×× when the I2C bus is used.

PD178018A SUBSERIES AND µPD178003 SUBSERIES EXPANSION

PD178018A Subseries

80 pins PROM : 60 KB RAM : 3 KBPD178P018A

80 pins ROM : 60 KB RAM : 3 KBPD178018A

80 pins ROM : 48 KB RAM : 3 KBPD178016A

80 pins ROM : 48 KB RAM : 1 KBPD178006A

80 pins ROM : 32 KB RAM : 1 KBPD178004A

Note

PD178003 Subseries

Note Under development

80 pins ROM : 24 KB RAM : 0.5 KBPD178003

80 pins ROM : 16 KB RAM : 0.5 KBPD178002

Note

PD178004A, 178006A, 178016A, 178018A

OUTLINE OF FUNCTION

Product name

Item Internal ROM (ROM configuration) 32 Kbytes 48 Kbytes 60 Kbytes

memory (mask ROM) (mask ROM) (mask ROM)

High-speed RAM 1 024 bytes Buffer RAM 32 bytes

Expansion RAM Not provided 2 048 bytes General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle With variable instruction execution time function

Instruction set • 16-bit operation

I/O port Total : 62 pins

A/D converter 8-bit resolution × 6 channels Serial interface • 3-wire/SBI/2-wire/I2C bus

Timer • Basic timer (timer carry FF (10 Hz)) : 1 channel

Buzzer (BEEP) output 1.5 kHz, 3 kHz, 6 kHz Vectored Maskable Internal: 8, external: 7

interrupt Source

Test input Internal: 1

Non-maskable Internal: 1

Software Internal: 1

PD178004A

0.44 µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (with 4.5-MHz crystal resonator)

• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

CMOS input : 1 pin CMOS I/O : 54 pins N-ch open-drain I/O : 4 pins N-ch open-drain output : 3 pins

• 3-wire serial I/O mode (with automatic transfer/receive function of up to 32 byte) : 1 channel

• 8-bit timer/event counter : 2 channels

• 8-bit timer (D/A converter: PWM output): 1 channel

• Watchdog timer : 1 channel

PD178006A

Note

PD178016A

mode selectable : 1 channel

PD178018A

(1/2)

Note When using the I2C bus mode (including when this mode is implemented by program without using the

peripheral hardware), consult your local NEC sales representative when you place an order for mask.

PD178004A, 178006A, 178016A, 178018A

(2/2)

Product name

Item PLL frequency Division mode Two types

synthesizer • Direct division mode (VCOL pin)

Reference frequency 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Charge pump Error out output: 2 (EO0 and EO1 pins Phase comparator Unlock detectable by program

Frequency counter • Frequency measurement

D/A converter (PWM output) 8-/9-bit resolution × 3 channels (shared by 8-bit timer) Standby function • HALT mode

Reset • Reset by RESET pin

Power supply voltage • VDD = 4.5 to 5.5 V (with PLL operating)

Package • 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

PD178004A

• Pulse swallow mode (VCOH and VCOL pins)

• AMIFC pin: for 450-kHz count

• FMIFC pin: for 450-kHz/10.7-MHz count

• STOP mode

• Internal reset by watchdog timer

• Reset by power-ON clear circuit (3-value detection)

• Detection of less than 4.5 V

• Detection of less than 3.5 V

• Detection of less than 2.5 V

•VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)

•VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)

PD178006A

Note 2

PD178016A

Note 1

)

Note 2

(CPU clock: fX)

(CPU clock: fX/2 or less and on power application)

Note 2

(in STOP mode)

PD178018A

Notes 1. The EO1 pin can be set to high impedance for the µPD178016A and 178018A.

The following shows an application example.

PD178016A

PD178018A

EO0 EO1

VCOH

VCOL

LPF VCO

To Mixer

LPF : Low path filter VCO : Voltage controlled oscillator

• To lock to a target frequency at high speed Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF voltage control potential.

• Normal state Setting only the EO0 pin to error out output maintains the LPF stable.

2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these values.

PD178004A, 178006A, 178016A, 178018A

TABLE OF CONTENTS

1. PIN CONFIGURATION (TOP VIEW)................................................................................................ 6

2. BLOCK DIAGRAM ........................................................................................................................... 8

3. PIN FUNCTION LIST........................................................................................................................ 9

3.1 PORT PINS................................................................................................................................ 9

3.2 PINS OTHER THAN PORT PINS............................................................................................ 10

3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ..... 11

4. MEMORY SPACE .......................................................................................................................... 14

5. PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 15

5.1 PORTS..................................................................................................................................... 15

5.2 CLOCK GENERATOR ............................................................................................................16

5.3 TIMER...................................................................................................................................... 16

5.4 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................ 18

5.5 A/D CONVERTER ................................................................................................................... 19

5.6 SERIAL INTERFACES............................................................................................................ 19

5.7 PLL FREQUENCY SYNTHESIZER ........................................................................................ 21

5.8 FREQUENCY COUNTER........................................................................................................ 22

6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................... 23

6.1 INTERRUPT FUNCTIONS ...................................................................................................... 23

6.2 TEST FUNCTION .................................................................................................................... 26

7. STANDBY FUNCTION ................................................................................................................... 27

8. RESET FUNCTION ........................................................................................................................ 27

9. INSTRUCTION SET ....................................................................................................................... 28

10. ELECTRICAL SPECIFICATIONS .................................................................................................. 30

11. PACKAGE DRAWINGS ................................................................................................................. 46

12. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 47

APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES ............... 48

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 49

APPENDIX C. RELATED DOCUMENTS ........................................................................................... 51

1. PIN CONFIGURATION (TOP VIEW)

• 80-PIN PLASTIC QFP (14 × 14 mm, 0.65 mm pitch)

PD178004AGC-×××-3B9, 178006AGC-×××-3B9

PD178016AGC-×××-3B9, 178018AGC-×××-3B9

RESET

VDDREGOSCX1X2

GND

PD178004A, 178006A, 178016A, 178018A

REGCPU

P06/INTP6

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1

P00/INTP0

P125

P124

P123

P122

P121

P120

P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

P132/PWM0 P133/PWM1 P134/PWM2

P40 P41 P42

80 7978 77 76 75 7473 72 71 70 6968 67 66 65 6463 62 61

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 2223 24 25 26 2728 29 30 31 3233 34 35 36 3738 39 40

P43

P44

DDPORT

GNDPORT

P45

P46

P47

FMIFC

AMIFC

DDPLL

VCOL

VCOH

EO0

EO1

GNDPLL

P50

P51

P52

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P53

P37 P36/BEEP P35 P34/TI2 P33/TI1 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54

Cautions 1. Connect the Internally Connected (IC) pin to GND directly.

2. Connect VDDPORT and VDDPLL pins to VDD.

3. Connect the GNDPORT and GNDPLL pins to GND.

4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.

PD178004A, 178006A, 178016A, 178018A

AMIFC : AM Intermediate Frequency Counter Input AN10 to AN15 : A/D Converter Input BEEP : Buzzer Output BUSY : Busy Output EO0, EO1 : Error Out Output FMIFC : FM Intermediate Frequency Counter Input GND : Ground GNDPLL : PLL Ground GNDPORT : Port Ground IC : Internally Connected INTP0 to INTP6 P00 to P06 : Port 0 P10 to P15 : Port 1 P20 to P27 : Port 2 P30 to P37 : Port 3 P40 to P47 : Port 4 P50 to P57 : Port 5 P60 to P67 : Port 6 P120 to P125 : Port 12

: Interrupt Inputs

P132 to P134 : Port 13 PWM0 to PWM2 REGCPU : Regulator for CPU Power Supply REGOSC : Regulator for Oscillator Circuit RESET : Reset Input SB0, SB1 : Serial Data Bus Input/Output SCK0, SCK1 : Serial Clock Input/Output SCL : Serial Clock Input/Output SDA0, SDA1 : Serial Data Input/Output SI0, SI1 : Serial Data Input SO0, SO1 : Serial Data Output STB : Strobe Output TI1, TI2 : Timer Clock Input VCOL, VCOH : Local Oscillator Input VDD : Power Supply VDDPLL : PLL Power Supply VDDPORT : Port Power Supply X1, X2 : Crystal Oscillator Connection

: PWM Output

2. BLOCK DIAGRAM

PD178004A, 178006A, 178016A, 178018A

TI1/P33

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

ANI0/P10 to

ANI5/P15

INTP0/P00 to

INTP6/P06

BEEP/P36

8-bit TIMER/ EVENT COUNTER 1

8-bit TIMER/ EVENT COUNTER 2

8-bit TIMER 3

WATCHDOG TIMER

BASIC TIMER

SERIAL INTERFACE 0

SERIAL INTERFACE 1

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

78K/0

CPU

CORE

RAM

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 12

PORT 13

D/A CONVERTER

(PWM)

FREQUENCY COUNTER

P00

P01 to P06

P10 to P15

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P120 to P125

P132 to P134

PWM0/P132 to

PWM2/P134

AMIFC FMIFC

RESET

X1 X2

DDPORT

GNDPORT

REGOSC REGCPU

GND

SYSTEM CONTROL

VOLTAGE REGULATOR

RESET CPU PERIPHERAL

OSC

VCPU

Remark The internal ROM and RAM capacities depend on the version.

PLL

PLL VOLTAGE REGULATOR

EO0 EO1 VCOL VCOH

DDPLL

GNDPLL

3. PIN FUNCTION LIST

3.1 PORT PINS

PD178004A, 178006A, 178016A, 178018A

Pin Name I/O Function After Reset P00 Input Port 0. Input only Input INTP0 P01 to P06 I/O P10 to P15 I/O Port 1. Input ANI0 to ANI5

P20 I/O Port 2. Input SI1 P21 P22 P23 STB P24 BUSY P25 SI0/SB0/SDA0 P26 P27 SCK0/SCL P30 to P32 I/O Port 3. Input — P33 P34 P35 — P36 BEEP

P37 — P40 to P47 I/O Port 4. Input —

P50 to P57 I/O Port 5. Input —

P60 to P63 I/O Port 6. Middle voltage N-ch open drain Input —

P64 to P67 Input/output mode can be LEDs can be driven directly.

P120 to I/O Port 12. Input — P125 6-bit input/output port.

P132 to Output Port 13. — PWM0 to P134 3-bit output port. PWM2

7-bit input/output port.

6-bit input/output port. Input/output mode can be specified bit-wise.

8-bit input/output port. Input/output mode can be specified bit-wise.

8-bit input/output port. Input/output mode can be specified in 8-bit units. Test input flag (KRIF) is set to 1 by falling edge detection.

8-bit input/output port. Input/output mode can be specified bit-wise.

8-bit input/output port. input/output port.

specified bit-wise.

Input/output mode can be specified bit-wise.

N-ch open-drain output port.

Input/output mode can be specified bit-wise.

Input

Alternate Function

INTP1 to INTP6

SO1 SCK1

SO0/SB1/SDA1

TI1 TI2

3.2 PINS OTHER THAN PORT PINS

PD178004A, 178006A, 178016A, 178018A

Pin Name I/O Function After Reset

INTP0 to Input External maskable interrupt inputs with specifiable valid edges (rising Input P00 to P06 INTP6 edge, falling edge, both rising and falling edges).

SI0 Input Serial interface serial data input Input SI1 P20 SO0 Output Serial interface serial data output Input SO1 P21 SB0 I/O Serial interface serial data input/output Input P25/SI0/SDA0 SB1 SDA0 P25/SI0/SB0 SDA1 P26/SO0/SB1 SCK0 I/O Serial interface serial clock input/output Input P27/SCL SCK1 P22 SCL P27/SCK0 STB Output Serial interface automatic transmit/receive strobe output Input P23 BUSY Input Serial interface automatic transmit/receive busy input Input P24 TI1 Input External count clock input to 8-bit timer (TM1) Input P33 TI2 External count clock input to 8-bit timer (TM2) P34 BEEP Output Buzzer output Input P36 ANI0 to ANI5 PWM0 to PWM2 EO0, EO1 Output Error out output from charge pump of the PLL frequency synthesizer — — VCOL Input Inputs PLL local band frequency (In HF, MF mode) — — VCOH Input Inputs PLL local band frequency (In VHF mode) — — AMIFC Input Inputs AM intermediate frequency counter — — FMIFC Input Inputs FM intermediate frequency counter — — RESET Input System reset input — — X1 Input System clock oscillation resonator connection — — X2 — —— REGOSC — Oscillation regulator. Connected to GND via a 0.1-µF capacitor. — — REGCPU — CPU power supply regulator. Connected to GND via a 0.1-µF capacitor. — — VDD — Positive power supply — — GND — Ground —— VDDPORT — Positive power supply for port block — — GNDPORT — Ground for port block — — VDDPLL GNDPLL IC — Internally connected. Connected to GND or GNDPORT. — —

Input A/D converter analog input Input P10 to P15 Output PWM output — P132 to P134

Note

— Positive power supply for PLL — —

Note

— Ground for PLL — —

Alternate Function

P25/SB0/SDA0

P26/SB1/SDA1

P26/SO0/SDA1

Note Connect a capacitor of approximately 1 000 pF between the VDDPLL pin and GNDPLL pin.

PD178004A, 178006A, 178016A, 178018A

3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS

Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type.

Table 3-1. I/O Circuit Type of Each Circuit

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins P00/INTP0 2 Input Connected to GND or GNDPORT P01/INTP1 to P06/INTP6 8 I/O Set in general-purpose input port mode by software and P10/ANI0 to P15/ANI5 11-A P20/SI1 8 P21/SO1 5 P22/SCK1 8 P23/STB 5 P24/BUSY 8 P25/SI0/SB0/SDA0 10

P26/SO0/SB1/SDA1 P27/SCK0/SCL

P30 to P32 5 P33/TI1, P34/TI2 8 P35 5

P36/BEEP P37

P40 to P47 5-G P50 to P57 5 P60 to P63 13-D P64 to P67 5 P120 to P125 P132/PWM0 to P134/PWM2 19 Output Set to low-level output by software and open EO0 DTS-EO1 Open EO1 DTS-EO3 VCOL, VCOH DTS-AMP Input Set to disabled status by software and open AMIFC, FMIFC IC — — Connected to GND or GNDPORT directly

Note

individually connected to VDD, VDDPORT, GND, or GNDPORT via resistor.

Note For the µPD178004A and 178006A, the I/O circuit type is DTS-EO1.

PD178004A, 178006A, 178016A, 178018A

Figure 3-1. Pin Input/Output Circuit of List (1/2)

Type 2

Type 5

data

output disable

Type 8

VDD

Schmitt-Triggered Input with Hysteresis Characteristics

VDD

P-ch

IN/OUT

N-ch

data

output disable

Type 10

data

open-drain

output disable

P-ch

IN/OUT

N-ch

VDD

P-ch

IN/OUT

N-ch

input enable

Type 5-G Type 11-A

VDD

P-ch

IN/OUT

N-ch

data

output disable

VDD

P-ch

N-ch

IN/OUT

data

output

disable

comparator

input enable

P-ch

N-ch

REF (Threshold voltage)

Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,

and should be read as VDDPORT and GNDPORT, respectively.

PD178004A, 178006A, 178016A, 178018A

Figure 3-1. Pin Input/Output Circuit of List (2/2)

Type 13-D Type DTS-EO3

output disable

data

Type 19

N-ch

VDD

Middle-Voltage Input Buffer

N-ch

P-ch

OUT

IN/OUT

Type DTS-AMP

DDPLL

P-ch

N-ch

GNDPLL

DDPLL

OUT

Type DTS-EO1

DDPLL

P-ch

OUT

N-ch

GNDPLL

Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,

and should be read as VDDPORT and GNDPORT, respectively.

PD178004A, 178006A, 178016A, 178018A

4. MEMORY SPACE

Figure 4-1 shows the µPD178004A, 178006A, 178016A, and 178018A memory map.

Figure 4-1. Memory Map

FFFFH

Special Function Registers

(SFR) 256 × 8 bits

FF00H

Data Memory Space

Program Memory Space

FEFFH

FEE0H

FEDFH

FB00H FAFFH

FAE0H

FADFH

FAC0H FABFH

nnnnH + 1

nnnnH

0000H

General-Purpose

Registers

32 × 8 bits

Internal High-Speed

RAM

1 024 × 8 bits

Use Prohibited

Buffer RAM 32 × 8 bits

Use Prohibited

Internal ROM

Note 3

FABFH

F800H

F7FFH

F000H

EFFFH

nnnnH + 1

nnnnH

1000H

0FFFH

0800H 07FFH

0080H 007FH

0040H 003FH

0000H

Use Prohibited

Internal Expanded RAM

2 048 × 8 bits

Use Prohibited

Program Area

CALLF Entry Area

Program Area

CALLT Table Area

Vectored Table Area

Note 2

Note 1

Notes 1. Available only for µPD178016A and 178018A

2. The µPD178018A does not contain this use prohibited area.

3. The internal ROM capacity depends on the version (see the table below).

Corresponding Product Internal ROM Last Address

Name nnnnH

PD178004A 7FFFH

PD178006A, 178016A BFFFH

PD178018A EFFFH

PD178004A, 178006A, 178016A, 178018A

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 PORTS

The following 3 types of I/O ports are available.

• CMOS input (P00) : 1

• CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 12) : 54

• N-channel open-drain input/output (P60 to P63) : 4

• N-ch open drain output (Port 13) : 3 Total : 62

Table 5-1. Port Functions

Name

Port 0 P00

Port 1

Port 3 P30 to P37

Port 4 P40 to P47 Input/output port pins. Input/output specifiable in 8-bit units.

Port 5 P50 to P57

Port 6 P60 to P63

Port 12

Port 13 P132 to P134

Pin Name Function

Dedicated input port pins

P01 to P06 P10 to P15 P20 to P27

P64 to P67

P120 to P125 Input/output port pins. Input/output specifiable bit-wise.

Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise.Port 2 Input/output port pins. Input/output specifiable bit-wise.

Test flag (KRIF) is set to 1 by falling edge detection. Input/output port pins. Input/output specifiable bit-wise. N-channel open-drain input/output port pins. Input/output specifiable bit-wise.

LED direct drive capability. Input/output port pins. Input/output specifiable bit-wise.

N-ch open drain output port.

PD178004A, 178006A, 178016A, 178018A

5.2 CLOCK GENERATOR

The instruction execution time can be changed as follows.

0.44 µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (@ 4.5-MHz crystal oscillator with system clock.)

Figure 5-1. Clock Generator Block Diagram

Prescaler

Clock to the PLL frequency synthesizer, basic timer and buzzer output control circuit.

System

Clock

Oscillator

STOP

Scaler

fX 2

Selector

Prescaler

fXX

Selector

Standby

Control

Circuit

To INTP0 Sampling Clock

5.3 TIMER

The µPD178004A, 178006A, 178016A, and 178018A incorporate 5 channels of the timer.

• Basic timer : 1 channel

• 8-bit timer/event counter : 2 channels

• 8-bit timer (D/A converter)

• Watchdog timer : 1 channel

Note Used is shared with the 8/9-bit resolution × 3-channel D/A converter (PWM output).

Note

: 1 channel

Figure 5-2. Basic Timer Block Diagram

Clock to peripheral hardware other than the above.

Wait Control

Circuit

CPU Clock (f

CPU)

4.5 MHz INTTMC

Divider

xx/2 to fxx/2

fx/2

TI1/P33

fxx/2 to fxx/2

fx/2

TI2/P34

PD178004A, 178006A, 178016A, 178018A

Figure 5-3. 8-Bit Timer/Event Counter Block Diagram

Internal Bus

INTTM1

8-Bit Compare

Match

Selector

8-Bit Timer

Selector

Clear

Selector

8-Bit Compare

Selector

Match

INTTM2

8-Bit Timer

Clear

4.5 MHz

Clock

Generation

Block

PWM

Internal Bus

Figure 5-4. 8-Bit Timer (D/A Converter) Block Diagram

Internal Bus

INTPWM

PWM Data Register 2

(PWMR2)

Comparator Comparator Comparator

Clear Circuit

PWM Duty Setting Block

Note

PWM Data Register 1

(PWMR1)

b8 b0

9-Bit Binary Counter

PWM Data Register 0

(PWMR0)

PWM

1SE

0SE

Output Select

Block

Output Select

Block

Output Select

Block

PWM Mode Select Register

PWM

2SE

P132/PWM0

P133/PWM1

P134/PWM2

PWM

BIT

PWMMDPWMSTPWM

CK0

RES

PWM Control Register

Internal Bus

Note The PWM data register 2 (PWMR2) is multiplexed with the PWM timer register (PWMTMR).

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