NEC PD17062 User Manual
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD17062
4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY
SYNTHESIZER AND IMAGE DISPLAY CONTROLLER
The µPD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device
incorporates an image display controller enabling a range of different displays, together with a PLL frequency
synthesizer.
The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/
reset, powerful interrupt, and a timer.
The device contains a user-programmable image display controller (IDC) for on-screen displays. The
different displays can be controlled with simple programs.
The device also has a serial interface function, many input/output (I/O) ports controlled by powerful I/O
instructions, and 6-bit pulse width modulation (PWM) output for a 4-bit A/D converter and D/A converter.
FEATURES
• 4-bit microcontroller for digital tuning system
• Internal PLL frequency synthesizer: With prescaler
µ
PB595
•5 V ±10%
• Low-power CMOS
• Program memory (ROM): 8K bytes (16 bits × 3968
steps)
• Data memory (RAM): 4 bits × 336 words
• 6 stack levels
• 35 easy-to-understand instruction sets
• Support of decimal operations
µ
• Instruction execution time: 2
crystal)
• Internal D/A converter: 6 bits × 4 (PWM output)
• Internal A/D converter: 4 bits × 6
• Internal horizontal synchronizing signal counter
• Internal commercial power frequency counter
• Internal power-failure detector and power-on reset
circuit
s (with an 8-MHz
• Internal image display controller (IDC) (user-pro-
grammable)
Number of characters in display: Up to 99 on a
single screen
Display configuration: 14 rows × 19 columns
Number of character types: 120
Character format: 10 × 15 dots (rimming possible)
Number of colors: 8
Character size: Four sizes in each of the horizontal
and vertical dimensions
Internal 1H circuit for preventing vertical deflection
• Internal 8-bit serial interface (One system with two
channels: three-wire or two-wire)
• Interrupt input for remote-controller signals (with
noise canceler)
• Many I/O ports
Number of I/O ports : 15
Number of input ports : 4
Number of output ports: 8
Document No. IC-3560
(O.D. No. IC-8937)
Date Published January 1995 P
Printed in Japan
The information in this document is subject to change without notice.
©
1995
µ
ORDERING INFORMATION
Part number Package
µ
PD17062CU-××× 48-pin plastic shrink DIP (600 mil)
µ
PD17062GC-××× 64-pin plastic QFP (14 × 14 mm)
Remark ××× is the ROM code number.
FUNCTION OVERVIEW
Item Function
ROM (program memory) capacity 3968 × 16 bits (masked ROM)
CROM (character ROM) capacity 1920 × 16 bits (included in ROM)
RAM (data memory) capacity 336 × 4 bits (including the area that can be used for VRAM)
VRAM (video RAM) capacity 224 × 4 bits (included in RAM)
Instruction execution time 2 µs (when the 8-MHz crystal is used)
Stack level 6 levels (stack operation possible)
Number of I/O ports Number of input ports: 4
Number of output ports: 8
Number of I/O ports: 15
IDC (Image Display Controller) Number of characters in display: Up to 99 on a single screen
Display format: 10 × 15 dots, 14 rows × 19 columns
Number of character types: 120 (user-programmable)
Number of colors: 8
Character size
Vertical dimension : 1 to 4 times (can be set for each line)
Horizontal dimension : 1 to 4 times (can be set for each character)
Serial interface Serial interface 0 (two-wire or I2C bus compatible)
D/A converter 6 bits × 4 (PWM output, withstand voltage of up to 12.5 V)
A/D converter 4 bits × 6 (successive-approximation converter by software)
Interrupt External interrupt : 2 channels
Timer 1 channel (internal clock/zerocross input)
PLL frequency synthesizer Scaling method : Pulse swallow method (VCO pin: Up to 40 MHz),
Reset Power-on reset
Supply voltage 5 V ±10%
One system
4 channels
Reference frequency : 6.25, 12.5, 25 kHz
Charge pump : Error-out output
Phase comparator : Capable of unlock detection by a program
Reset by the CE pin
With power-failure detection function
Serial interface 1 (two-wire or three-wire)
Internal interrupt : 2 channels
external specialized two-modulus prescaler
(µPB595, for example)
PD17062
2
PIN CONFIGURATION (TOP VIEW)
48-pin plastic shrink DIP (600 mil)
µ
PD17062
P0C3
P0C2
P0C1
P0C0
P0D3/ADC5
P0D2/ADC4
P0D1/ADC3
P0D0/ADC2
PWM3
PWM2
PWM1
PWM0
VDD
VCO
EO
GND
PSC
CE
OUT
X
XIN
P1A3
P1A2
P1A1
P1A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
µ
PD17062CU-×××
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
INTNC
0/SDA
P0A
P0A1/SCL
P0A2/SCK
3/SO
P0A
0/SI
P0B
P0B
1
2/TMIN
P0B
P0B3/HSCNT
0
ADC
P1C1
P1C2
P1C3/ADC1
VSYNC
HSYNC
BLANK
BLUE
GREEN
RED
P1B0
1
P1B
P1B2
3
P1B
GND
0 to ADC5 : A/D converter input P0D0 to P0D3 : Port 0D
ADC
BLANK : Blanking signal output P1A
BLUE : Character signal output P1B
CE : Chip enable P1C
0 to P1A3 : Port 1A
0 to P1B3 : Port 1B
1 to P1C3 : Port 1C
EO : Error out RED : Character signal output
GND : Ground SCK : Shift clock input/output
GREEN : Character signal output SCL : Shift clock input/output
HSCNT : Horizontal synchronizing signal SDA : Serial data input/output
counter input SI : Serial data input
H
SYNC : Horizontal synchronizing signal input SO : Serial data output
NC : Interrupt signal input TMIN : Timer event input
INT
NC : No connection VCO : Local oscillation input
PSC : Pulse swallow control output V
PWM
0 to PWM3 : Pulse width modulation output VSYNC : Vertical synchronizing signal input
0 to P0A3 : Port 0A XIN : Clock oscillation
P0A
P0B
0 to P0B3 : Port 0B XOUT : Clock oscillation
P0C
0 to P0C3 : Port 0C
DD : Main power supply
3
64-pin plastic QFP (14 × 14 mm)
µ
PD17062
P0D
0
/ADC
PWM
PWM
PWM
NC
PWM
NC
NC
V
NC
3
/ADC
1
P0D
4
/ADC
2
P0D
5
/ADC
3
P0D
0
P0C
1
P0C
2
P0C
3
P0C
NC
NC
NC
INT
/SDA
0
P0A
/SCL
1
P0A
/SCK
1
P0A
/SO
3
P0A
/SI
0
P0B
1
P0B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
2
3
2
1
1
2
3
4
5
0
6
7
8
PD17062GC-×××-3BE
µ
DD
9
10
48
47
46
45
44
43
42
41
40
39
POB
2
/TMIN
POB3/HSCNT
ADC
0
P1C
1
NC
P1C
2
NC
NC
NC
NC
VCO
NC
EO
NC
GND
PSC
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0
CE
OUT
X
IN
X
2
P1A3P1A
NC
1
P1A
P1A
NC
GND
3
P1B
2
P1B
1
P1B
0
P1B
RED
38
37
36
35
34
33
GREEN
P1C
3
/ADC
NC
V
SYNC
H
SYNC
BLANK
BLUE
1
4
BLOCK DIAGRAM
VCO
PSC
EO
SYNC
H
V
SYNC
RED
GREEN
BLUE
BLANK
0
/SDA
P0A
1
/SCL
P0A
2
/SCK
P0A
3
/SO
P0A
P0B
0
/SI
PLL
IDC
Serial
I/O
RF
RAM
336 × 4 bits
(Including VRAM)
SYSREG
ALU
PWM
P1A
P1B
µ
PD17062
PWM
PWM
PWM
PWM
P1A
P1A
P1A
P1A
P1B
P1B
P1B
P1B
0
1
2
3
0
1
2
3
0
1
2
3
P0B2/TMIN
3
/HSCNT
P0B
P0D
0
/ADC
P0D1/ADC
P0D2/ADC
P0D3/ADC
P1C3/ADC
P0B
P1C
P1C
ADC
P0A
1
P0B
Hsync Counter
ROM
3968 × 16 bits
(Including CROM)
Timer Controller
P0C
Interrupt
Controller
P0C
P0C
P0C
P0C
INT
0
1
2
3
NC
Instruction
Decoder
2
3
4
5
1
2
1
P0D
P1C
Program Counter
Stack 6 × 12 bits
CPU
Peripheral
OSC
Reset
X
X
V
CE
IN
OUT
DD
GND
A/D
0
5
µ
PD17062
CONTENTS
1. PINS ............................................................................................................................................. 11
1.1 PIN FUNCTIONS ............................................................................................................................. 11
1.2 EQUIVALENT CIRCUITS OF THE PINS ........................................................................................ 14
2. PROGRAM MEMORY (ROM) .................................................................................................... 18
2.1 CONFIGURATION OF PROGRAM MEMORY............................................................................... 18
2.2 FUNCTIONS OF PROGRAM MEMORY ........................................................................................ 19
2.3 PROGRAM FLOW ........................................................................................................................... 19
2.4 BRANCHING A PROGRAM ............................................................................................................ 20
2.6 TABLE REFERENCE ........................................................................................................................ 24
2.7 NOTES ON USING THE BRANCH INSTRUCTION AND
SUBROUTINE CALL INSTRUCTION ............................................................................................. 24
3. PROGRAM COUNTER (PC) ....................................................................................................... 25
4. STACK.......................................................................................................................................... 26
4.1 COMPONENTS................................................................................................................................26
4.2 STACK POINTER (SP) .................................................................................................................... 26
4.3 ADDRESS STACK REGISTERS (ASRs) ........................................................................................ 27
4.4 INTERRUPT STACK REGISTERS .................................................................................................. 27
5. DATA MEMORY (RAM) ............................................................................................................. 29
5.1 STRUCTURE OF DATA MEMORY ................................................................................................ 29
5.2 FUNCTIONS OF DATA MEMORY ................................................................................................. 34
5.3 NOTES ON USING DATA MEMORY ............................................................................................ 38
6. GENERAL-PURPOSE REGISTER (GR) ...................................................................................... 40
6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER ............................................................. 40
6.2 FUNCTION OF THE GENERAL-PURPOSE REGISTER ................................................................ 40
6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND
DATA MEMORY IN INDIVIDUAL INSTRUCTIONS ..................................................................... 42
6.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER......................................................... 46
7. ARITHMETIC LOGIC UNIT (ALU) BLOCK ................................................................................ 48
7.1 OVERVIEW ...................................................................................................................................... 48
7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ............ 49
7.3 ALU OPERATIONS ......................................................................................................................... 49
7.4 NOTES ON USING THE ALU ........................................................................................................ 53
8. SYSTEM REGISTER (SYSREG) ................................................................................................. 54
8.1 ADDRESS REGISTER (AR)............................................................................................................. 55
8.2 WINDOW REGISTER (WR) ............................................................................................................ 55
8.3 BANK REGISTER (BANK) .............................................................................................................. 56
8.4 MEMORY POINTER ENABLE FLAG (MPE) .................................................................................. 56
6
µ
PD17062
8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57
8.6 GENERAL-PURPOSE REGISTER POINTER (RP).......................................................................... 66
8.7 PROGRAM STATUS WORD (PSWORD) ...................................................................................... 66
9. REGISTER FILE (RF) ................................................................................................................... 67
9.1 IDCDMAEN (00H, b1) ...................................................................................................................... 75
9.2 SP (01H) ........................................................................................................................................... 75
9.3 CE (07H, b0) ..................................................................................................................................... 76
9.4 SERIAL INTERFACE MODE REGISTER (08H) .............................................................................. 76
9.5 BTM0MD (09H) ............................................................................................................................... 77
9.6 INTVSYN (0FH, b
9.7 INTNC (0FH, b
9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H).......................... 78
9.9 PLL REFERENCE MODE SELECTION REGISTER (13H).............................................................. 79
9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H) .................................................. 79
9.11 TIMER CARRY (17H) ....................................................................................................................... 80
9.12 SERIAL INTERFACE WAIT CONTROL (18H) ................................................................................ 80
9.13 IEGNC (1FH) .................................................................................................................................... 80
9.14 A/D CONVERTOR CONTROL (21H) .............................................................................................. 81
9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H) ..................................................................... 81
9.16 PORT1C I/O SETTING (27H) .......................................................................................................... 82
9.17 SERIAL I/O0 STATUS REGISTER (28H) ....................................................................................... 82
9.18 INTERRUPT PERMISSION FLAG (2FH) ........................................................................................ 83
9.19 CROM BANK SELECTION (30H) ................................................................................................... 83
9.20 IDCEN (31H) .................................................................................................................................... 84
9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) .................................................. 84
9.22 P1BBIOn (35H) ................................................................................................................................85
9.23 P0BBIOn (36H) ................................................................................................................................85
9.24 P0ABIOn (37H) ................................................................................................................................86
9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN
SERIAL INTERFACE MODE (38H) ................................................................................................. 86
9.26 SHIFT CLOCK FREQUENCY SETTING (39H) ............................................................................... 87
9.27 IRQNC (3FH) .................................................................................................................................... 87
2) ......................................................................................................................... 77
0) .............................................................................................................................. 78
10. DATA BUFFER (DBF) .................................................................................................................. 88
10.1 DATA BUFFER STRUCTURE ......................................................................................................... 88
10.2 FUNCTIONS OF DATA BUFFER .................................................................................................... 90
10.3 DATA BUFFER AND TABLE REFERENCING ................................................................................ 91
10.4 DATA BUFFER AND PERIPHERAL HARDWARE ......................................................................... 93
10.5 DATA BUFFER AND PERIPHERAL REGISTERS .......................................................................... 97
10.6 PRECAUTIONS WHEN USING DATA BUFFERS ......................................................................... 104
11. INTERRUPT ................................................................................................................................. 106
11.1 INTERRUPT BLOCK CONFIGURATION ........................................................................................ 106
11.2 INTERRUPT FUNCTION ................................................................................................................. 108
11.3 INTERRUPT ACCEPTANCE ............................................................................................................ 111
11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE ...................................................................... 116
7
µ
PD17062
11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 116
11.6 INTERRUPT PROCESSING ROUTINE ........................................................................................... 117
11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN) ....................................................................... 121
11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE) .............................................................. 123
11.9 MULTIPLE INTERRUPTS ................................................................................................................ 124
12. TIMER .......................................................................................................................................... 133
12.1 TIMER CONFIGURATION .............................................................................................................. 133
12.2 TIMER FUNCTIONS ........................................................................................................................ 134
12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF) ............................................................................ 136
12.4 CAUTIONS IN USING THE TIMER CARRY FF ............................................................................. 141
12.5 TIMER INTERRUPT ......................................................................................................................... 147
12.6 CAUTIONS IN USING THE TIMER INTERRUPT .......................................................................... 151
13. STANDBY .................................................................................................................................... 153
13.1 STANDBY BLOCK CONFIGURATION ........................................................................................... 153
13.2 STANDBY FUNCTION .................................................................................................................... 154
13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN ........................................................... 155
13.4 HALT FUNCTION ............................................................................................................................ 156
13.5 CLOCK STOP FUNCTION ............................................................................................................... 164
13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP .................................................... 167
14. RESET .......................................................................................................................................... 171
14.1 RESET BLOCK CONFIGURATION ................................................................................................. 171
14.2 RESET FUNCTION .......................................................................................................................... 172
14.3 CE RESET ......................................................................................................................................... 173
14.4 POWER-ON RESET ......................................................................................................................... 177
14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET .............................................. 180
14.6 POWER FAILURE DETECTION ...................................................................................................... 184
15. GENERAL-PURPOSE PORT ....................................................................................................... 189
15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT ............................ 189
15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS ............................................................................ 191
15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C) ............................................................. 194
15.4 GENERAL-PURPOSE INPUT PORT (P0D) .................................................................................... 198
15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A) ..................................................................... 199
16. SERIAL INTERFACE .................................................................................................................... 201
16.1 SERIAL INTERFACE MODE REGISTER ........................................................................................ 201
16.2 CLOCK COUNTER ........................................................................................................................... 206
16.3 STATUS REGISTER ........................................................................................................................ 207
16.4 WAIT REGISTER ............................................................................................................................. 209
16.5 PRESETTABLE SHIFT REGISTER (PSR) ....................................................................................... 214
16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) ........................................... 215
16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)....................................................................... 216
8
µ
PD17062
17. D/A CONVERTER ....................................................................................................................... 217
17.1 PWM PINS ....................................................................................................................................... 217
18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219
18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION ................................................................. 219
18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK .............................................. 220
18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER ................................... 221
18.4 REFERENCE FREQUENCY GENERATOR (RFG) .......................................................................... 223
φ
18.5 PHASE COMPARATOR (
18.6 PLL DISABLE MODE ....................................................................................................................... 231
18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER .................................................... 232
-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK ......... 225
19. A/D CONVERTER ....................................................................................................................... 233
19.1 PRINCIPLE OF OPERATION ........................................................................................................... 233
19.2 D/A CONVERTER CONFIGURATION ........................................................................................... 234
19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR) ................................................................ 235
19.4 COMPARISON REGISTER (ADCCMP) .......................................................................................... 235
19.5 ADC PIN SELECT REGISTER (ADCCHn) ...................................................................................... 236
19.6 EXAMPLE OF A/D CONVERSION PROGRAM ............................................................................ 237
20. IMAGE DISPLAY CONTROLLER ............................................................................................... 240
20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS .................................................................... 240
20.2 DIRECT MEMORY ACCESS ........................................................................................................... 243
20.3 IDC ENABLE FLAG ......................................................................................................................... 245
20.4 VRAM ............................................................................................................................................... 246
20.5 CHARACTER ROM .......................................................................................................................... 255
20.6 BLANK, R, G, AND B PINS ............................................................................................................ 263
20.7 SPECIFYING THE DISPLAY START POSITION ........................................................................... 264
20.8 SAMPLE PROGRAMS .................................................................................................................... 268
21. HORIZONTAL SYNC SIGNAL COUNTER ................................................................................ 274
21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION .................................................... 274
21.2 GATE CONTROL REGISTER (HSCGT) .......................................................................................... 275
21.3 HSYNC COUNTER (HSC) ............................................................................................................... 276
21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL .......................................................... 276
22. INSTRUCTION SETS .................................................................................................................. 277
22.1 OUTLINE OF INSTRUCTION SETS ............................................................................................... 277
22.2 INSTRUCTIONS .............................................................................................................................. 278
22.3 LIST OF INSTRUCTION SETS ....................................................................................................... 279
22.4 BUILT-IN MACRO INSTRUCTIONS .............................................................................................. 281
23. RESERVED SYMBOLS FOR ASSEMBLER ............................................................................... 282
23.1 SYSTEM REGISTER (SYSREG) ..................................................................................................... 282
23.2 DATA BUFFER (DBF) ...................................................................................................................... 282
23.3 PORT REGISTER ............................................................................................................................. 283
23.4 REGISTER FILES ............................................................................................................................. 284
9
µ
PD17062
23.5 PERIPHERAL HARDWARE REGISTER .......................................................................................... 286
23.6 OTHERS ........................................................................................................................................... 286
24. ELECTRICAL CHARACTERISTICS ............................................................................................. 287
25. PACKAGE DRAWINGS ............................................................................................................... 289
26. RECOMMENDED SOLDERING CONDITIONS ....................................................................... 291
APPENDIX DEVELOPMENT TOOLS ............................................................................................... 292
10
1. PINS
1.1 PIN FUNCTIONS
Pin No.
58
|
61
62
|
1
2
|
6
9
11
13
Symbol
P0C3
|
P0C0
P0D3/ADC5
|
P0D0/ADC2
PWM3
|
PWM0
VDD
VDD1
VDD0
VCO
EO
DIP QFP
(GC)
1
|
4
5
|
8
9
|
12
13
14
15
Description Output type At power-on reset
4-bit output port
Input of port 0D and A/D converter
• P0D3 to P0D0
4-bit input port containing a pull-down resis-
tor.
• ADC5 to ADC2
Input of a 4-bit A/D converter, which is a soft-
ware-based successive-approximation type. The
reference voltage is VDD.
Output of a 6-bit D/A converter. The output type
is PWM. Output is done at a frequency of 15.625
kHz. The pin can also be used as a one-bit output
port.
Supplies the power to the device. To enable all
functions, 5 V ±10% is supplied. To operate only
the CPU, 4 V is required. In the clock-stop state,
the voltage can be reduced to 3.5 V.
When the supply voltage increases from 0 V to 4
V, a power-on reset occurs and the program is
started from address 0.
Apply an identical voltage to all pins.
Inputs the signal obtained by dividing the local
oscillation output by the specialized prescaler.
Outputs the PLL error signal. The signal is input
through the external LPF to the local oscillation
circuit.
CMOS push-pull
—
N-ch open drain
—
—
CMOS tristate
µ
PD17062
Undefined
Input
Undefined
—
Input
Hi-z
16
17
18
19
20
15
16
17
18
19
GND
GND2
GND1
GND0
PSC
CE
XOUT
XIN
Grounds the device. Connect all pins to ground.
Outputs the signal to switch the frequency divi-
sion ratio of the specialized prescaler.
Inputs the signal to select the device.
To operate the PLL and IDC, set the input signal
high.
If the input signal is low, the device can be backed
up with a low current drain by executing a stop
instruction.
When the input signal goes high, the device is reset
and the program is started from address 0.
Used to connect a crystal.
An 8-MHz crystal is used.
—
CMOS push-pull
—
—
—
—
Undefined
Input
—
Input
11
Pin No.
DIP QFP
(GC)
21
20
|
|
24
24
26
27
|
|
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
38
|
|
38
45
39
46
40
47
|
|
43
50
44
51
|
|
47
54
µ
PD17062
Symbol Description Output type At power-on reset
P1A3
|
P1A0
P1B3
|
P1B0
RED
GREEN
BLUE
BLANK
HSYNC
VSYNC
P1C3/ADC1
P1C2
P1C1
ADC0
P0B3/HSCNT
P0B2/TMIN
P0B1
P0B0/SI
P0A3/SO
P0A2/SCK
P0A1/SCL
P0A0/SDA
4-bit output port. This N-ch open-drain output
port has an intermediate withstand voltage.
4-bit I/O port. Each bit can be set for input or
output.
Outputs the character data corresponding to R, G,
and B of the IDC display. The output is active-
high.
Outputs the blanking signal for cutting the
video signal of the IDC display. The output is
active-high.
Inputs the horizontal synchronizing signal of the
IDC display. The input must be active-low.
Inputs the vertical synchronizing signal of the IDC
display. The input must be active-low. The input
signal can generate an interrupt.
Input of port 1C and A/D converter
• P1C3 to P1C1
3-bit I/O port
• ADC1
Input of a 4-bit A/D converter
Input of a 4-bit A/D converter
Serial interface and input for port 0B, port 0A,
horizontal synchronizing signal counter, and
timer
• P0A3 to P0A0
4-bit I/O port. Each bit can be set for input or
output.
• P0B3 to P0B0
4-bit I/O port. Each bit can be set for input or
output.
• HSCNT
Inputs the count of the horizontal
synchronizing signal. The input is self-
biased.
• TMIN
Timer input. The pin inputs the commercial
power to be used for the clock.
• SI, SO, SCK
Input/output for the three-wire serial interface
• SI: Serial data input
• SO: Serial data output
• SCK: Shift clock input/output
• SDA, SCL
Input/output for the two-wire serial interface
• SCL: Serial clock input/output
• SDA: Serial data input/output
N-ch open-drain
CMOS push-pull
CMOS push-pull
CMOS push-pull
—
—
CMOS push-pull
—
N-ch open-drain
(P0A1, P0A0)
CMOS push-pull
(Other than P0A1
or P0A0)
Undefined
Input
Low level
Low level
Input
Input
Input
Input
Input
12
Pin No.
DIP QFP
(GC)
48—55
5
6
7
8
10
12
14
22
25
37
39
40
41
42
44
56
57
µ
PD17062
Symbol Description Output type At power-on reset
INTNC
NC
Interrupt input. Contains the noise canceler. An
interrupt can be generated at either the rising or
falling edge of the input signal.
No connection. The pins are not connected to the
internal circuit of the device. They can be used as
desired.
— Input
13
1.2 EQUIVALENT CIRCUITS OF THE PINS
P0A (P0A3/SO, P0A2/SCK)
P0B (P0B
P1B (P1B
P1C (P1C
1, P0B0/SI)
3, P1B2, P1B1, P1B0)
3/ADC1, P1C2, P1C1)
V
DD
µ
PD17062
A/D converter (only for P1C/ADC)
RESET signal (except for P1C)
Read instruction (only for P1C)
V
DD
P0A (P0A1/SCL, P0A0/SDA)
(I/O)
14
P0C (P0C3, P0C2, P0C1, P0C0)
RED, GREEN, BLUE, BLANK, PSC
PWM (PWM3, PWM2, PWM1, PWM0)
P1A (P1A
P0D (P0D3/ADC5, P0D2/ADC4, P0D1/ADC3, P0D0/ADC2)
3, P1A2, P1A1, P1A0)
(Output)
(Output)
µ
PD17062
ADC0
A/D Converter
(Input)
High on-state
resistance
A/D converter selection signal
15
P0B3/HSCNT
Port
µ
PD17062
P0B2/TMIN
P-ch
N-ch
Port
Horizontal synchronizing
signal counter
16
P-ch
Timer/counter
N-ch
HSYNC, VSYNC, INTNC, CE
XOUT, XIN
(Hysteresis input)
µ
PD17062
EO
VCO
X
IN
X
OUT
(Input)
17
µ
PD17062
2. PROGRAM MEMORY (ROM)
Program memory stores the program to be executed by the CPU, as well as predetermined constant data.
2.1 CONFIGURATION OF PROGRAM MEMORY
Fig. 2-1 shows the configuration of program memory.
As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968 × 16 bits).
Locations in program memory are addressed in units of 16 bits. The total address range is from 0000H
to 0F7FH. Memory is divided into pages. The range of page 0 is from 0000H to 07FFH, while that of page
1 is from 0800H to 0F7FH.
The range from 0800H to 0F7FH can be used as the CROM (character ROM) area in which the display patterns
for the IDC are stored. If this area is not used as CROM, it can be used as a program area.
The range from 0000H to 00FFH is a table reference area. The area is used by the JMP @AR, CALL @AR,
MOVT, PUSH, and POP instructions.
Fig. 2-1 Configuration of Program Memory
Address
0000H
07FFH
0800H
0F7FH
Program memory (ROM)
15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b
16 bits
Page 0
Page 1 (area that can be used as CROM)
3968 steps
18
µ
PD17062
2.2 FUNCTIONS OF PROGRAM MEMORY
Program memory has two basic functions:
(1) Program storage
(2) Constant data storage
A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually
controls the microcontroller). The CPU executes processing sequentially according to the instructions coded
in the program. The CPU sequentially reads instructions from the program stored in program memory and
executes processing according to each instruction.
Each instruction is one word, or 16 bits in length. A single instruction can thus be stored at a single address
in program memory.
Constant data is predetermined data such as a display pattern. Constant data is read from program memory
into a data buffer (DBF) in data memory (RAM) upon execution of the specialized MOVT instruction. This
reading of constant data from memory is called table referencing.
Program memory is read-only storage that cannot be rewritten by the execution of an instruction. In this
document, program memory and ROM (read-only memory) are synonymous.
2.3 PROGRAM FLOW
A program stored in program memory is usually executed one address at a time starting from address
0000H. If another program is to be executed upon some condition being satisfied, the program flow must
be branched. To achieve this, the branch instruction (BR) is used.
If a single program is executed a number of times, the efficiency of the program memory is reduced. This
problem can be solved by storing that program at a given location and calling it using the specialized CALL
instruction. Such a program is called a subroutine while the usual program is called a main routine.
If a program is executed upon some condition being satisfied, independently of the current program flow,
the interrupt function is used. If a predetermined condition is satisfied, the interrupt function transfers control
to a specified address (vector address) irrespective of the current program flow.
These program flows are controlled by the program counter (PC), which specifies program memory
addresses.
19
µ
PD17062
2.4 BRANCHING A PROGRAM
A program is branched by execution of the branch instruction (BR).
Fig. 2-2 illustrates the operation of the branch instruction.
Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control
to a program memory address (addr) directly specified in its operand. Indirect branch instructions (BR @AR)
transfer control to a program memory address specified in an address register (AR), described below.
See also Chapter 3.
2.4.1 Direct Branch
A direct branch instruction uses the least significant bit of the operation code and the 11 bits of its operand,
12 bits in total, to specify the destination program memory address. The destination of the direct branch
instruction can be any address in program memory between 0000H and 0F7FH.
2.4.2 Indirect Branch
The indirect branch instruction uses the eight-bit data of an address register to specify the destination
address. The destination of the indirect branch instruction is limited to addresses between 0000H and 00FFH.
See Section 8.1.
20
µ
PD17062
Fig. 2-2 Operation of Branch Instruction and Machine Code
(a) Direct branch (BR addr) (b) Indirect branch (BR @AR)
Address Program memory
0000H
0500H
07FFH
0800H
0900H
0F7FH
Label: Instruction (Machine code)
BR AAA (0C500)
BR BBB (0D100)
AAA:
Page 0
BR AAA (0C500)
BBB:
BR BBB (0D100)
Page 1
Address Program memory
0000H
0010H
0085H
0500H
07FFH
0800H
0F7FH
Label: Instruction (Machine code)
MOV AR0, #5H
MOV AR1, #8H
BR
@AR
Page 0
MOV AR0, #0H
MOV AR1, #1H
@AR
BR
Page 1
Remark The machine code (16 bits) of the 17K series consists of five blocks, of one bit, four bits, three bits,
four bits, and four bits. In this document, machine code is represented in these blocks so that
it can be easily understood.
Example Machine code 0C500 → 0 1100 101 0000 0000
14 3 4 4
2.4.3 Notes on Debugging
Direct branch instructions to page 0 (addresses 0000H to 07FFH) and page 1 (addresses 0800H to 0F7FH)
use different operation codes, as shown in Fig. 2-2.
The operation codes of the direct branch instructions to page 0 and page 1 are 0CH, and 0DH, respectively.
The difference arises because the direct branch instruction uses the addr operand, which is only 11 bits
long, together with the least significant bit of the operation code, to specify the branch destination address.
When assembling a program, the 17K series assembler (AS17K) references a jump destination identified
by a label and automatically converts the that instruction.
If the program is patched during debugging, the programmer must determine whether the branch
destination is on page 0 or page 1 and convert the instruction into operation code 0CH or 0DH.
If address BBB in (a) of Fig. 2-2 is patched from 0900H to 0910H, for example, the machine code of the BR
BBB instruction must be changed to 0D110.
21
µ
PD17062
2.5 SUBROUTINE
If a subroutine is executed, the specialized subroutine call instruction (CALL) and subroutine return
instruction (RET, RETSK) are used.
Fig. 2-3 illustrates the operation of subroutine call.
Subroutine call instructions are divided into two types. The direct subroutine call instruction (CALL addr)
calls the program memory address (addr) specified in its operand. The indirect subroutine call instruction
(CALL @AR) calls the program memory address specified in an address register.
The RET or RETSK instruction is used to return control from a subroutine. The RET or RETSK instruction
returns control to a program memory address next to the address at which the subroutine call instruction
(CALL) was executed. Upon execution of the RETSK instruction, the first instruction after the return is executed
as a no-operation instruction (NOP).
See also Chapter 3.
2.5.1 Direct Subroutine Call
The direct subroutine call instruction uses 11 bits of its operand to specify the program memory address
to be called. If the direct subroutine call instruction is used, the destination, or the first address of the
subroutine to be called, must be page 0 (addresses 0000H to 07FFH). The instruction cannot call a subroutine
whose first address is in page 1 (addresses 0800H to 0F7FH).
The subroutine return instruction (RET, RETSK) can be in page 1. The CALL instruction can be in page 0
or page 1.
Examples 1. When the subroutine return instruction is in page 0
When the first address of the subroutine is in page 0, as shown in Fig. 2-4, the return address
and return instruction can be in page 0 or page 1. When only the first address of the subroutine
is in page 0, the CALL instruction can be used in either page. If the first address of the
subroutine cannot be placed in page 0 because of programming restrictions, the method
shown in example 2 can be used.
2. When the first address of the subroutine is in page 1
The branch instruction (BR) is placed in page 0, as shown in Fig. 2-4, and the desired
subroutine (SUB1) is called via the BR instruction.
2.5.2 Indirect Subroutine Call
The indirect subroutine call instruction (CALL @AR) uses the 8-bit data in an address register (AR) to specify
the address of a subroutine to be called. The instruction can call a subroutine from a program memory address
between 0000H and 00FFH.
See Section 8.1.
22
µ
PD17062
Fig. 2-3 Operation of Subroutine Call Instruction
(a) Direct subroutine call (CALL addr) (b) Indirect subroutine call (CALL @AR)
Address Program memory
0000H
0500H SUB1:
07FFH
0800H
0F7FH
Label: Label:
Instruction
CALL SUB1
RET
Page 0
CALL SUB1
Page 1
Fig. 2-4 Sample Uses of Subroutine Call Instruction
Address Program memory
0000H
0010H
0085H
07FFH
0800H
0F7FH
SUB2:
SUB3:
Instruction
RET
MOV AR0, #0H
MOV AR1, #1H
CALL @AR
Page 0
MOV AR0, #5H
MOV AR1, #8H
CALL @AR
Page 1
(a) If the subroutine return instruction is in page 1 (b) If the first address of the subroutine is in page 1
Address Program memory
0000H
0500H SUB1:
07FFH
0800H
0F7FH
Instruction
CALL SUB1
Page 0
RET
CALL SUB1
Page 1
Address Program memory
0000HLabel: Label:
SUB1:BR SUB2
07FFH
0800H
0890H SUB2:
0F7FH
Instruction
CALL SUB1
Page 0
RET
CALL SUB1
Page 1
23
µ
PD17062
2.6 TABLE REFERENCE
The table reference instruction is used to reference the constant data in program memory. If the MOVT
DBF, @AR instruction is executed, data at the program memory address specified in an address register is
placed in a data buffer (DBF).
Because each data item in program memory consists of 16 bits, the constant data placed in the data buffer
by the MOVT instruction also consists of 16 bits (four words). Because the address register consists of eight
bits, the MOVT instruction can reference a program memory address between 0000H and 00FFH.
When table referencing is executed, a single stack is used.
See Sections 8.1 and 10.3.
2.7 NOTES ON USING THE BRANCH INSTRUCTION AND SUBROUTINE CALL INSTRUCTION
The 17K series assembler (AS17K) detects an error if a program memory address (numeric address) is
directly specified in the operand of the branch instruction (BR) or subroutine call instruction (CALL).
The assembler provides this function to minimize the number of bugs arising from program modification.
Examples 1. Instruction causing an error
;
#
BR 0005H ; The assembler detects the error.
;
$
CALL 00F0H ;
2. Instruction causing no error
;
%
LOOP1: ; The BR or CALL instruction is executed for a label used in the
BR LOOP1 ; program.
;
&
SUB1: ;
CALL SUB1 ;
;
(
LOOP2 LAB 0005H ; As a label type, 0005H is assigned to LOOP2.
BR LOOP2 ;
;
)
BR. LD. 0005H ; The numeric value of the operand is converted to a label type.
; It is recommended that this method not be used to reduce
; the number of bugs.
For details, refer to the AS17K User’s Manual.
24
µ
PD17062
3. PROGRAM COUNTER (PC)
The program counter addresses program memory or a program. It is a 12-bit binary counter.
Fig. 3-1 Program Counter
PC11 PC9PC10 PC8 PC6PC7 PC5 PC3PC4 PC2 PC0PC1
12 bits
Normally, the program counter is incremented by 1 each time an instruction is executed. When a branch
instruction or a subroutine call instruction is executed, however, the address specified in the operand field
is loaded into the program counter. If a skip instruction has been executed, the address of the instruction
following the skip instruction is specified, regardless of the contents of the skip instruction. If the specified
address contains a skip condition, the instruction following the skip instruction is regarded as being a NOP
instruction. That is, the NOP instruction is executed, and the address of the next instruction is specified.
If an interrupt request is accepted, one of addresses 1 to 4 (depending on the cause of the interrupt) is loaded
into the PC.
If a power-on reset or a CE reset is performed, the program counter is reset to address 0.
Table 3-1 Vector Addresses upon Interrupt Occurrence
Priority Interrupt cause Vector address
1 INT
2 Internal timer 3H
3VSYNC pin 2H
4 Serial interface 1H
NC pin 4H
25
µ
PD17062
4. STACK
The stack is a register used to save an address returned by a program or the contents of the system register,
described later, when a subroutine call occurs or an interrupt is accepted.
4.1 COMPONENTS
The stack consists of a stack pointer (SP), which is a 4-bit binary counter, six 13-bit address stack registers
(ASRs), and two 3-bit interrupt stack registers.
4.2 STACK POINTER (SP)
The stack pointer is located at address 01H in the register file, and specifies an address stack register. The
contents of the stack pointer are decremented by 1 whenever a push operation (CALL, MOVT, or PUSH
instruction or interrupt acceptance) is performed, or incremented by 1 whenever a pop operation (RET, RETSK,
RETI, MOVT, or POP instruction) is performed.
The high-order bit of the stack pointer is always set to 0. The stack pointer can indicate any of eight different
values, 0H to 7H. However, 6H and 7H are not assigned to the stack.
Fig. 4-1 Structure of Stack Pointer
MSB LSB
0 (SPb2) (SPb1) (SPb0)
Table 4-1 Behavior of Stack Pointer
Instruction Stack pointer value
CALL addr
CALL @AR
MOVT DBF, @AR SP – 1
PUSH AR
Interrupt acceptance
RET
RETSK
MOVT DBF, @AR SP + 1
POP AR
RETI
26
µ
PD17062
4.3 ADDRESS STACK REGISTERS (ASRs)
There are six address stack registers, each consisting of 13 bits. After a subroutine call instruction has been
executed or an interrupt request accepted, the contents of the address stack register will contain a value that
is equal to the contents of the program counter, plus one, or the return address. The contents of an address
stack register are loaded into the program counter by executing a return instruction, after which control returns
to the original program flow.
The address stack registers are used for both subroutine calls and interrupts. If two levels of the address
stack registers are used for interrupts, the remaining four levels can be used for subroutine calls.
If a MOVT instruction is executed, an address stack register is used temporarily.
Fig. 4-2 Structure of Address Stack Registers
Stack pointer value
0H
1H
2H
3H
4H
5H
ASR0
ASR1
ASR2
ASR3
ASR4
ASR5
4.4 INTERRUPT STACK REGISTERS
There are two interrupt stack registers, each consisting of three bits, as shown in Fig. 4-3.
If an interrupt is accepted, the value of the two bits of the bank register (BANK) and the value of the one
bit of the index-enable flag (IXE) in the system register (SYSREG), described later, are saved to an interrupt
stack register. Once an interrupt return instruction (RETI) has been executed, the contents of the interrupt
stack register are returned to the bank register and the index-enable flag of the system register.
Unlike the address stack registers, the interrupt stack registers contain no addresses specified by the stack
pointer. As shown in Fig. 4-4, data is saved to an interrupt stack pointer each time an interrupt is accepted,
the saved data being returned whenever an interrupt return instruction is executed. If accepted interrupts
consist of more than two levels, the first level of data is pushed out. Thus, it must be saved by the program.
If a power-on reset is performed, the contents of the interrupt stack registers become undefined. Even if
a CE reset is performed or a clock stop instruction is executed, however, the contents of the interrupt stack
registers remain as is.
27
Fig. 4-3 Structure of Interrupt Stack Registers
MSB LSB
µ
PD17062
0H
1H
Fig. 4-4 Behavior of Interrupt Stack Registers
Not defined B A Not definedA
Not defined A Not defined Not definedNot defined
BANKSK0
BANKSK1
IXESK0
IXESK1
RETIRETIInterrupt BInterrupt AVDD is applied.
28
µ
PD17062
5. DATA MEMORY (RAM)
Data memory is used to store data for operations and control. Simply by executing an appropriate
instruction, data can be written to and read from data memory at any time.
5.1 STRUCTURE OF DATA MEMORY
Fig. 5-1 shows the structure of data memory.
As shown in Fig. 5-1, data memory is divided into three units called banks. These three banks are called
BANK0, BANK1, and BANK2.
In each bank, data is assigned an address in units of four bits. The high-order three bits are called the row
address, while the low-order four bits are called the column address. For example, the data memory location
having row address 1H and column address AH is referred to as the data memory location having address
1AH. One address consists of four bits of memory. These four bits are called a nibble.
Data memory is divided into the blocks described in Sections 5.1.1 to 5.1.5, according to function.
29
Fig. 5-1 Data Memory Structure
0123456789ABCDEF
0
1
2
3
BANK0
4
5
6
P0A
P0B
P0C
7
(4 bits)
(4 bits)
(4 bits)
P0D
(4 bits)
System register
0123456789ABCDEF
0
1
2
3
BANK1
4
5
6
P1A
P1B
P1C
7
(4 bits)
(4 bits)
(4 bits)
Fixed
at 0
System register
DBF3 DBF2 DBF1 DBF0
µ
PD17062
0123456789ABCDEF
0
1
2
3
BANK2
4
5
6
P0A
P0B
P0C
7
(4 bits)
(4 bits)
(4 bits)
P0D
(4 bits)
System register
The same register is allocated for each bank.
30
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