UPD16647 |
DATA SHEET |
MOS INTEGRATED CIRCUIT
μ PD16647
402/384-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DESCRIPTION
The μ PD16647 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 5.0 V. The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs γ -corrected by the internal D/A converter and 10 external power supplies. The clock frequency is 50 MHz MIN. μ PD16647 can be used in TFT-LCD panels conforming to the SVGA standards.
FEATURES
∙CMOS level input
∙402/384 outputs
∙6 bits (gray scale data) x 3 dots input
∙64-value output by 10 external power supplies and internal D/A converter
∙Output dynamic range : VSS2 + 0.1 V to VDD2 − 0.1 V
∙ High-speed data transfer: fMAX =50 MHz MIN.(internal data transfer rate at supply voltage VDD1 of logic circuit =3.0 V)
∙ Level of γ -corrected power supply can be inverted
∙ Input data inversion function (INV)
∙ Precharge-less output buffer
∙ Logic supply voltage (VDD1) : 3.3 V ± 0.3 V
∙ Driver supply voltage (VDD2) : 5.0 V ± 0.5 V
∙ Slim TCP
ORDERING INFORMATION
Part Number |
Package |
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μ PD16647N-xxx |
TCP (TAB package) |
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Remark The TCP package |
is a custom-ordered item. Users are requested to consult with an NEC sales |
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representative. |
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13607EJ2V0DS00 (2nd edition) |
The mark • shows major revised points. |
© |
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1998 |
Date Published August 1999 NS CP (K) |
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Printed in Japan
μ PD16647
1. BLOCK DIAGRAM
STHR |
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STHL |
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134-bit bidirectical shift register |
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VDD1 (3.3 V) |
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R,/L |
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VSS1 |
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CLK |
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Osel |
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C1 C2 |
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C133 C134 |
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D00 - D05
D10 - D15
D20 - D25
Data register
INV
STB |
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Latch |
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Bcont |
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D/A converter |
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VDD2 (5.0 V) |
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V0 - V9 |
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VSS2 |
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Output buffer
S1 |
S2 |
S3 |
S402/384 |
Remark /xxx indicates active low signal.
2 |
Data Sheet S13607EJ2V0DS00 |
μ PD16647
2. PIN CONFIGURATION (μ PD16647N-xxx)
Bcont |
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VSS2 |
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VDD2 |
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VDD1 |
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R,/L |
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INV |
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STHL |
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D20 |
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D21 |
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D22 |
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D23 |
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D24 |
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D25 |
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D10 |
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D11 |
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D12 |
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D13 |
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D14 |
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D15 |
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V9 |
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V8 |
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Copper foil |
V7 |
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V6 |
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surface |
V5 |
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V4 |
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V3 |
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V2 |
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V1 |
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V0 |
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CLK |
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STB |
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D00 |
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D01 |
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D02 |
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D03 |
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D04 |
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D05 |
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STHR |
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VSS1 |
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VDD2 |
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VSS2 |
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Osel |
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Remark This figure does not specify the TCP package.
S402/384
S401/383
S400/382
S399/381
S212/194
S211/193
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193
S4
S3
S2
S1
Data Sheet S13607EJ2V0DS00 |
3 |
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μ PD16647 |
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3. PIN DESCRIPTION |
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Pin Symbol |
Pin Name |
Description |
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S1 to S402/384 |
Driver output |
Output 64 gray-scale analog voltages converted from digital signals. |
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Osel = H or open: 402 outputs (S1 to S402/384) |
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Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384) |
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S193 to S210 outputs are invalid in 384 outputs. |
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D00 to D05 |
Display data input |
Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB). |
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D10 to D15 |
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DX0 : LSB, DX5 : MSB |
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D20 to D25 |
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R,/L |
Shift direction select input |
This pin inputs/outputs start pulses in cascade mode. |
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Shift direction of shift register is as follows: |
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R,/L = H : STHR input, S1 → S402, STHL output |
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R,/L = L : STHL input, S402 → S1, STHR output |
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STHR |
Right shift start pulse I/O |
R,/L = H : Inputs start pulse |
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R,/L = L : Outputs start pulse |
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STHL |
Left shift start pulse I/O |
R/L = H : Outputs start pulse |
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R/L = L : Inputs start pulse |
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Bcont |
Bias control |
This pin can be used to finely control the bias current inside the output |
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amplifier. In cases when fine-control is necessary, connect this pin to VDD2 |
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using a resistor of 10 to 100kΩ (per IC). When this fine-control function is |
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not required, short-circuit this pin to VDD2. Refer to 7. Bias Current Control |
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Function/Bcont. |
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CLK |
Shift clock input |
Inputs shift clock to shift register. Display data is loaded to data register at |
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rising edge of this pin. Start pulse output goes high at rising edge of 134th |
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clock after start pulse has been input, and serves as start pulse to driver in |
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next stage. 134th clock of driver in first stage serves as start pulse of driver |
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in next stage. |
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STB |
Latch input |
Contents of data register are latched at rising edge, transferred to D/A |
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converter, and output as analog voltage corresponding to display data. |
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Contents of internal shift register are cleared after STB has been input. One |
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pulse of this signal is input when μ PD16647 is started, and then device |
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operates normally. |
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For STB input timing, refer to 9. Switching Characteristics Waveform. |
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Osel |
Selection of number of outputs |
Selects number of outputs. This pin is internally pulled up to VDD1. |
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Osel = H or open : 402 outputs (S1 to S402/384) |
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Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384) |
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V0 to V9 |
γ-corrected power supply |
Inputs γ-corrected power from external source. |
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VSS2 ≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD2 or |
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VSS2 ≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ VDD2 |
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Maintain gray scale power supply during gray scale voltage output. |
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INV |
Data inversion input |
Input data can be inverted when display data is loaded. |
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INV = H : Inverts and loads input data. |
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INV = L : Does not invert input data. |
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VDD1 |
Logic circuit power supply |
3.3 V ± 0.3 V |
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VDD2 |
Driver circuit power supply |
5.0 V ± 0.5 V |
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VSS1 |
Logic ground |
Ground |
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VSS2 |
Driver ground |
Ground |
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Caution Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V9), and turn off power in the reverse order, to prevent the μ PD16647 from being damaged by latchup. Be sure to observe this power sequence even during a transition period.
4 |
Data Sheet S13607EJ2V0DS00 |
μ PD16647
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 10 major points on the γ -characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V9. If the display data is 00H or 3FH, gray scale voltage V0 or V9 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external power pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1 to Vn into eight segments by means of D/A conversion (however, the ranges from V8 to V7 and from V1 to V0 are divided into seven segments) to output a 64 gray scale voltage.
DX5(MSB) |
DX4 |
DX3 |
DX2 |
DX1 |
DX0 (LSB) |
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High-order 3 bits |
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Low-order 3 bits |
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: γ-corrected power selected |
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: 3-bit D/A (range Vn to Vn+1 is divided to 7 or 8 segments) |
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(Vn, Vn+1) |
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Vn |
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DX5 |
DX4 |
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DX3 |
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Vn+1-Vn |
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1 |
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0 |
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0 |
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0 |
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V1-V2 |
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2 |
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0 |
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0 |
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1 |
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V2-V3 |
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3 |
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0 |
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1 |
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V3-V4 |
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4 |
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0 |
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1 |
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V4-V5 |
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5 |
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1 |
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0 |
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V5-V6 |
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6 |
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1 |
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0 |
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V6-V7 |
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7 |
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1 |
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V7-V8 |
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8 |
Vn+1 |
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V8-V9 |
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000 001 010 011 100 101 110 111 |
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VDD2 V0
V1
V2
V3
V4
V5
V6
V7
Figure4-1. Relationship between Input Data and γ-corrected Voltage
gray scale supply specified by 00H
7 segments
8 segments
8 segments
8 segments
8 segments
8 segments
8 segments
7 segments
V8
VSS2 V9 |
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gray scale supply specified |
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0 |
7 |
F |
17 |
1F |
27 |
2F |
37 |
3F |
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by 3FH |
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Input data (HEX) |
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Data Sheet S13607EJ2V0DS00 |
5 |