MSI MS-6702 Schematics 00E
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Title Page
MS-6702 VER:0E ATX
*AMD PGA 754 K8-Processor (DDR 400)
D D
*VIA K8T400M / VT8237 Chipset
(AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*VT6306 1394a OHCI Link Layer Controller
*PDC20378 Serial ATA Controller
*RTL 8110S Giga/ 8100C100/10 Bit LAN
Support
*USB 2.0 support (integrated into VT8237)
*Vcore Jumpless support
*ALC650/ALC655 6 channel S/W Audio
C C
*DDR DIMM * 3
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 5
B B
Cover Sheet 1
Block Diagram
Clock Synthesizer & MS1 7
System Memory
DDR DIMM 1 & 2 & 3 8,9
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T400M/VER:0.4 (HT)
K8 Vcore
AGP SLOT 8X
VT8237
PCI Connectors * 5
ALC650/ALC655 6 channel S/W Audio
Serial ATA Controller PDC20378
IDE ATA 66/100 Connectors * 2
1394 Controller VT6306
Front USB Port *2
Rear USB Port *2
LPC I/O W83697HF & Floppy
Hardware monitor & FAN
BIOS ROM & VCORE ADJUSTI NG
Keyboard/Mouse Connectors
LPT/COM Port
Giga-Bit LAN RTL8110S/RTL8100C
ACPI Power CONTROLLER (MS-6)
SYSTEM VOLTAGE REGULATOR
Front Panel & POWER OK CIRCUIT
Decoupling Cap.
Power Sequence
History
OPTION PARTS
2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket
10
11
12,13,14
15
16
17,18,19
20,21,22
23
24,25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1. Modify Circuit 6702-0A_0822-91.DSN 08/22/91 - > La y out F in i sh e d ( Ge r be r- O ut Ve r si on ).
1. Modify Circuit 6702-0A_0827A-91.DSN 08/27/91-> Release NEW B O M o f E S -BOM for Stan d a r d
( 6702-A20 ).
2. Modify Circuit 6702-0A_1001-91.DSN 10/01/91-> Af t er Pilot-Run ( Didn't release EC R ) .
1. Modify Circuit 6702-0B_1108-91.DSN 11/08/91=> VER:0A -> OB : Modify H/W issue & K8-CPU
& NB-K8T400M & Change H/W Audio to S/W Audio ( Gerber-Out Version ) .
2. Creat new BOM for MS6702/VER:0B , 6702-0B_1108A-91.dsn 11/08/91 .
3. Modify BOM for MS6702/VER:0B , 6702-0B_1118-91.dsn 11/18/91 .
1. Modify Circuit 6702-0C FROM 67020B.
2.GERBER OUT 1/29/2003.
Layout Gerber-Out 0822-91
Release ES-BOM
Modify MS6702/VER:0B 10/04/2002
Modify MS6702/VER:0C 1/03/2003
A A
Micro Star Restricted Secret
MS6702-0E
5
4
3
2
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
Cover Sheet
MS-6702
Last Revision Date:
Sheet
Rev
0E
Wednesday, June 25, 2003
142
of
5
Block Diagram
4
3
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1
AMD K8 Socket 754
DDR400
D D
HT
A
G
C C
5 PCI Slots
P
S
L
O
T
AGP 8X /Fast Write
PCI-33
VIA
K8T400M
VLINK
Dual ATA
100/133
IDE Slot
==>ATA66,100,133 *2
DDR * 3
B B
1394
Front-Port *3
1394 Host
Controller
VT6306
AC97 => S/W Audio
ALC655 / 6 channel
AC97
SERIAL ATA *2
Serial ATA & IDE
RAID Controller
PDC20378
VT8237
USB
LPC BUS
SUPER I/O
W83697HF
ROM
X BUS
A A
Serial Port *2 ,
IDE Port *1
5
Giga Bit LAN
RTL8110S/8100C
4
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *6 ,
Back-Port *2
3
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Block Diagram
MS-6702
1
Last Revision Date:
Sheet
Rev
0E
Wednesday, June 25, 2003
242
of
5
4
3
2
1
GPIO FUNCTION
VT8237 GPIO Function Define
PIN NAME
D D
GPO0 (VSUS33)
GPO1/SUSA#(VSUS33)
GPO2/SUSB#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/SLP#
GPO8/GPI8/IPBIN0
GPO9/GPI9/IPBIN1
C C
GPO10/GPI10/IPBRDFR
GPO11/GPI11/IPBRDCK
GPO12/GPI12/INTE#
GPO13/GPI13/INTF#
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
B B
GPO20/GPI20
/ACSDIN2/PCS0#/EI
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/IOR#
GPO23/GPI23/DPSLP
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
VIDSEL
GPO29/GPI29/
A A
VRDSLP
GPO30/GPI30/GPIOD
GPO31/GPI31/GPIOE
5
VCORE_ADJ
NA
SUSB#
SUSST#
NA (Exteranl Pull up to 3VDUAL)
NA (Exteranl Pull up to VCC3)
NA (Exteranl Pull up to VCC3)
LDTSTOP#
NA
NA
NA
NA
S_VID0
S_VID1
S_VID2
NA
LDT Freq Strapping Bit0
LDT Freq Strapping Bit1
LDT Width (Low=8 Bit)
Fast Command (Low=Disable)
POWERF1
POWERF2
NA
ROMLOCK
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
NA
NA
NA
PIN NAME Function defineFunction define
GPI0
GPI1
GPI2/EXTSMI#
GPI3/RING#
GPI4/LID#
GPI5/BATLOW#
GPI6/AGPBZ#
GPI7/REQ#5
GPI16/INTRUDER#
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPI19/IORDY
(Exteranl Pull up to VBAT)NA
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
(Exteranl Pull up to 3VDUAL)
NA
POWERF3
(Exteranl Pull up to 3VDUAL)
NA
(Exteranl Pull up to VBAT)
NA
(Exteranl Pull up to 3VDUAL)
NA
THRM#
(Exteranl Pull up to VCC3)NA
S/IO GPIO Function Define
PIN NAME Function define
GPBX/GP13
GPAY/GP15
GPAS1/GP10
GPAS2/GP17
GPAX/GP12
GPBY/GP14
GPBS1/GP11
GPBS2/GP16
4
LED#4
LED#2
LED1
LED4
LED#3
LED#1
LED2
LED3
3
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
Giga-Bit
LAN
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
INT#B
INT#C
INT#D
INT#A
INT#A AD22 GLAN_PCLK
IDSEL
AD16
AD17
AD18
AD19
AD21
MS1 #1
SERIAL ATA INT#B AD24 SATAPCLK
1394 INT#D AD25 1394_PCLK( PREQ#5 )
REQ#/GNT#
PREQ#6
PGNT#6
PREQ#3
PGNT#3
PREQ#4
PGNT#4
PREQ#7
PGNT#7
PREQ#8
PGNT#8
PREQ#1
PGNT#1
PREQ#0
PGNT#0
( PREQ#2 )
( PGNT#2 )
( PGNT#5 )
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
MS1_PCLK
GPIO Spec.
MS-6702
Last Revision Date:
Sheet
1
Rev
0E
Wednesday, June 25, 2003
of
342
5
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MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
-MDQS8
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
C1561
X102P
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
U7B
RSVD_MEMADDA15
RSVD_MEMADDA14
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS5
-MCS4
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
MCKE0 8,9,10
MCKE1 8,9,10
MEMCLK_H[7..0]
MEMCLK_L[7..0]
-MCS5 9,10
-MCS4 9,10
-MCS[3..0]
-MCS[3..0] 8,10
-MSRASA 8,10
-MSCASA 8,10
-MSWEA 8,10
MEMBANKA1 8,10
MEMBANKA0 8,10
MAA[13..0] 8,10
-MSRASB 8,9,10
-MSCASB 8,9,10
-MSWEB 8,9,10
MEMBAKB1 8,9,10
MEMBAKB0 8,9,10
MAB[13..0] 8,9,10
MEMCHECK[7..0] 11
MEMCLK_H[7..0] 8,9,10
MEMCLK_L[7..0] 8,9,10
CLKIP112
CLKIN112
CLKIP012
CLKIN012
CTLIP012
CTLIN012
3
CADIP[0..15]12
VLDT0
R86 49.9RST
R80 49.9RST
VREF routed as 40~50 mils trace wide ,
Space>25 mils
C62
D D
DDR_VREF8,9
VDD_25_SUS
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
R120 10RST
R126 10RST
102P
MD[63..0]11
C C
B B
DM[8..0]11
-MDQS[8..0]11
A A
DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
5
VDD_12_A
VDD_12_A
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
C171
X_0.22u
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP1
CADIP0
CTLIP1
CTLIN1
C160
0.22u
D29
D27
D25
C28
C26
B29
B27
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
R29
T25
T27
T28
T29
C162
0.22u
U7A
N12-7540010-A10
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
2
C230
C169
0.22u
X_0.22u
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_H0
L0_CTLOUT_H1
L0_CTLOUT_H0
HYPER TRANSPORT - LINK0
C237
0.22u
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CLKOUT_L1
L0_CLKOUT_L0
L0_CTLOUT_L1
L0_CTLOUT_L0
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C161
0.22u
VLDT0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
CADOP15
CADON15
CADOP14
CADON14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8
CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3
CADOP2CADIP2
CADON2
CADOP1
CADON1
CADOP0
CADON0
CLKOP1
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
VLDT0 5
C69
4.7u/0805
CADOP[0..15] 12
CADON[0..15] 12CADIN[0..15]12
CLKOP1 12
CLKON1 12
CLKOP0 12
CLKON0 12
CTLOP0 12
CTLON0 12
Micro Star Restricted Secret
K8 DDR & HT
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
442
1
Rev
0E
of
5
D D
4
C1562
X_102P
VDDIO_SENSE
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
VCCA_PLL regulator circuit.
VDDA_25
C C
-LDTSTOP
PS_ON#A38
PS_ON#A
R91
Q18
2N7002S
VCC2_5
1K
VLDT04
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
HDT Test Port Signal .
B B
DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI
NC_AH18
NC_AJ18
NC_AG18
A A
NC_AG17
NC_C19
NC_D18
NC_D20
NC_B19
NC_C21
5
R71 1K
R61 1K
1 2
3 4
5 6
7 8
RN128 8P4R-1K
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R137 1K
VCC2_5
C1541
4.7u/0805
RN130
8P4R-1K
8P4R-1K
RN131
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
traces to exit ball field) and 500 mils long.
FB1 180nH/1210
CPU_GD36
R87 44.2RST
VLDT0
R83 44.2RST
4
CPU_VDDA_25
C46
X_102P
C76
102P
C77
102P
VDD_25_SUS
C74
4.7u/0805
-CPURST38
-LDTSTOP12,19
COREFB_H15
COREFB_L15
Differential , "10:10:5:10:10" .
CPUCLK0_H7
Near CPU in 0.5" .
CPUCLK0_L7
VTT_DDR_SUS
3
C72
0.22u
CPU_GD
L0_REF1
L0_REF0
C75 3900P/X7R
C78 3900P/X7R
R74 820
R64 820
VCC2_5
R133 1K
R124 1K
VDDIO_SENSE
169RST
R85
3 4
5 6
7 8
1 2
C73
3300p
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN129
8P4R-1K
CLKIN_H
CLKIN_L
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AG2
AH1
AE21
AG4
AG6
AE9
AG9
A23
A24
B23
C16
C15
E20
E17
B21
A21
C18
A19
A28
AA2
B18
C20
C1
J3
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
FB1505
THERMDC_CPU
X_120S/0603
U7C
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
2
THRM#
A20
THERMDA_CPU
A26
THERMDC_CPU
A27
VID4
AG13
VID3
AF14
VID2
AG14
VID1
AF15
VID0
AE15
NC_AG18
AG18
NC_AH18
AH18
NC_AG17
AG17
NC_AJ18
AJ18
FBCLKOUT_H
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
R88
80.6RST
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
VID2
VID3
VID1
VID0
VID4
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
THRM# 36
THERMDA_CPU 30,31
THERMDC_CPU 30
VID[4..0] 15,32
LAYOUT: Route
FBCLKOUT_H/L d if fe re n ti al ly
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
VDD_25_SUS
R138
1K
VCC2_5
RN7
1 2
3 4
5 6
7 8
8P4R-4.7K
R31 4.7K
K8 HDT & MISC
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
542
1
of
Rev
0E
5
4
3
2
1
U7E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
D D
C C
B B
A A
AF2
AA8
AB9
AA10
AE16
G20
R20
U20
W20
AA20
AC20
AE20
AG20
AJ20
D21
H21
M21
AD21
AG21
G22
N22
R22
U22
AG29
AA22
AC22
AG22
AH22
AJ22
D23
H23
AB23
AD23
AG23
G24
N24
R24
U24
W24
AA24
AC24
AG24
AJ24
C25
D26
H26
M26
AD26
AF26
AH26
C27
D28
G28
H15
AB17
AD17
G18
AA18
AC18
D19
H19
AB19
AD19
AF19
N20
D2
VSS10
VSS11
W6
VSS12
Y7
VSS13
VSS14
VSS15
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
VSS20
J18
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
F21
VSS32
VSS33
K21
VSS34
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
VSS40
VSS41
B22
VSS42
E22
VSS43
VSS44
J22
VSS45
L22
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
F23
VSS57
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
VSS64
VSS65
VSS66
E24
VSS67
VSS68
J24
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
B25
VSS78
VSS79
B26
VSS80
VSS81
VSS82
VSS83
T26
VSS84
Y26
VSS85
VSS86
VSS87
VSS88
VSS89
B28
VSS90
VSS91
VSS92
F15
VSS187
VSS188
VSS206
VSS207
B16
VSS208
VSS209
VSS210
VSS211
VSS212
F19
VSS213
VSS214
K19
VSS215
Y19
VSS216
VSS217
VSS218
VSS219
J20
VSS220
L20
VSS221
VSS222
GROUND
5
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
W21
AA21
AC21
M22
AB22
AD22
G23
W23
AA23
AC23
M24
AB24
AD24
AH24
AE25
GNDGND
H18
B20
E21
H22
H24
F26
V10
G13
K14
Y14
G15
H16
K16
Y16
G17
F18
K18
Y18
E19
G19
F20
H20
K20
M20
P20
T20
V20
Y20
G21
N21
R21
U21
F22
K22
P22
T22
V22
Y22
E23
N23
R23
U23
B24
D24
F24
K24
P24
T24
V24
Y24
K26
P26
V26
U7D
L7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
J23
VDD7
VDD8
VDD9
N7
VDD10
L9
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
J15
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
J17
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
J19
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
J21
VDD51
L21
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
L23
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of Claw-hammer.
VCORE
X_6.8pF/BACK
C180
{nopop}
C54
C612
X_6.8pF
X_6.8pF
C619
X_6.8pF/BACK
C616
X_6.8pF/BACK
C617
X_6.8pF/BACK
C605
{nopop}
X_6.8pF/BACK
{nopop}
C604
X_6.8pF/BACK
C86
C611
C603
X_6.8pF
X_6.8pF/BACK
Place between DIMN1 & 2
VDD_25_SUS
C2
C88
104P
VDD_25_SUS
C87
{nopop}
X_0.22u
C113
104P
C181
104P
C249
104P
GND
C287
104P
LAYOUT: Place beside processor.
C168
X_4.7u/0805
In CPU.
C119
224P
C120
224P
X_0.22u
{nopop}
C187
3
C125
224P
C136
224P
C232
X_0.22u
C148
X_4.7u/0805
VCORE
X_4.7u/0805
C129
224P
C126
224P
C3
C92
0.22u
C150
C123
X_0.22u
C132
224P
C130
224P
C135
224P
C133
224P
4.7u/0805
4.7u/0805
C139
224P
C137
224P
C159
X_6.8pF/BACK
C600
X_6.8pF/BACK
GND
VDD_25_SUS VTT_DDR_SUS
C172
C199
0.22u
C174
4.7u/0805
X_0.22u
GND
C122
224P
C140
224P
2
C284
X_0.22u
{nopop}
0.22u
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
K8 POWER & GND
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
1
Rev
0E
642
of
5
VCC3 VCC3
MSI PCI-Clock delay about 150pS from
PCI clock-input to PCI clock-output .
FRAME#
FRAME#17,20,21,22,24,27,35
STOP#
STOP#17,20,21,22,24,27,35
PREQ#0
PREQ#017
PGNT#0
PGNT#017
PREQ#6
PREQ#620
PGNT#6
PGNT#620
PREQ#7
PREQ#721
D D
VCC3
C768
C769
X_104P
X_104P
C C
PREQ#117,35
PREQ#217,24
PREQ#317,20
PREQ#417,21
PGNT#7
PGNT#721
PREQ#8
PREQ#822
PGNT#8
PGNT#822
PREQ#1
PREQ#2
PREQ#3
PREQ#4
U33
1
FRAME#
2
STOP#
3
SYSREQ#
4
SYSGNT#
5
PCIREQ1#
6
VSS
7
PCIGNT1#
8
PCIREQ2#
9
VCC
10
PCIGNT2#
11
PCIREQ3#
12
PCIGNT3#
13
VC3A
14 15
VC5A VC5B
MS1
B07-00MS102-E18
RN102
8P4R-2.7K
1 2
3 4
5 6
7 8
VCC
AVCC
PCICLKI
RESET#
AVSS
VSS
PCLCLK0
PCICLK1
VCC
PCICLK2
PCICLK3
PCICLK4
VSS
VC3B
28
27
26
25
24
23
22
21
20
19
18
17
16
PGNT#117,35
PGNT#217,24
PGNT#317,20
PGNT#417,21
PGNT#517,27
PREQ#517,27
4
C465 104P
MS1_PCLK
PCIDEVRST#
MSI_PCLK0
MSI_PCLK1
MSI_PCLK2
MSI_PCLK3
MSI_PCLK4
PGNT#6
PREQ#6
PGNT#0
PREQ#0
PGNT#8
PREQ#8
PGNT#7
PREQ#7
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5
PREQ#5
PCIDEVRST# 13,24,27,30,35,36
MSI_PCLK0
MSI_PCLK1
MSI_PCLK2
MSI_PCLK3
MSI_PCLK4
RN88
8P4R-4.7K
1 2
3 4
5 6
7 8
R470 4.7K
R469 2.7K
RN1541
8P4R-4.7K
1 2
3 4
5 6
7 8
RN108
8P4R-4.7K
1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2
C901 X_10P
VCC3
CN25
X_8P4C-10P
3
Clock Synthesizer
U22
ICS950402
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVDDA
C379 104P
C389 104P
C398 104P
C401 104P
C374 104P
C388 104P
C399 104P
C409 104P
_
46
VDD_46
47
VSS_47
2
VDD_2
5
VSS_5
32
VDDF
33
VSSF
9
VDD_9
10
VSS_10
16
VDD_16
15
VSS_15
19
VDD_19
20
VSS_20
29
VDD_29
30
VSS_30
27
VSS_27
38
VDD_38
39
VSS_39
35
VDD_35
34
VSS_34
43
VDDA
42
VSSA
Only support in ICS950402
PCISTOP_PCI33_6
CLK_RESET#38
ModeAHTT66_0
ModeBHTT66_1
PCI33_9_HT66_3
24_48MHZ/SEL
FS0/REF0
FS1/REF1
FS2/REF2
XOUT
48MHZ
HT66_2
PCI33_10
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_F
PCI33_4
PCI33_5
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
SPREAD
2
R_PCICLK10 GLAN_PCLK
FS0
1
FS1
48
FS2
45
CLKX1
3
XIN
CLKX2
4
31
MODEA
6
MODEB
7
8
R_PCICLK9
11
R_PCICLK10
12
R_PCICLK0
13
R_PCICLK1
14
R_PCICLK2
17
R_PCICLK3
18
R_PCICLKF
23
21
R_PCICLK5 SATAPCLK
22
SEL_24
28
SMBDATA1
26
SMBCLK1
25
TURBO#
41
40
R_CPU_CLK
37
-R_CPU_CLK
36
R_PCICLK6 MS1_PCLK
24
44
R390 22
R459 22
R295 22
R667 22
R313 22
R332 33
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
RN125 8P4R-22
R645 22
R646 22
R341 33
R622 22
R749 10
R750 10
1394_PCLKR_PCICLK9
SB_OSC14
AC_14
APICCLK
C375 10P/X7R
X1 14.318MHZ
C376 10P/X7R
USBCLK_SB48MHZ
RN68
VCLK
8P4R-22
GCLK_NB
GCLK_SLOT
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5R_PCICLK4
SIO48M
R326 15RST
R323 15RST
SBPCLKR_PCICLKF
SIOPCLK
5MILS
1394_PCLK 27
GLAN_PCLK 35
SB_OSC14 18
AC_14 23
APICCLK 19
USBCLK_SB 17
VCLK 19
GCLK_NB 13
GCLK_SLOT 16
PCICLK1 20
PCICLK2 20
PCICLK3 21
PCICLK4 21
PCICLK5 22
SATAPCLK 24
SIO48M 30
SMBDATA1 8,9,18,36
SMBCLK1 8,9,18,36
TURBO# 30
CPUCLK0_H 5
CPUCLK0_L 5
SBPCLK 19
SIOPCLK 30
1
VCLK
GCLK_NB
GCLK_SLOT
USBCLK_SB
SIO48M
SB_OSC14
APICCLK
AC_14
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SATAPCLK
SBPCLK
SIOPCLK
MS1_PCLK
GLAN_PCLK
1394_PCLK
CPUCLK0_H
CPUCLK0_L
VCC3
Decoupling Cap for CPU Clock
CN22
7 8
5 6
3 4
1 2
X_8P4C-10P
C400 X_10P
C406 X_10P
C370 X_10P
C383 X_10P
C700 X_10P
CN23
7 8
5 6
3 4
1 2
X_8P4C-10P
CN29
7 8
5 6
3 4
1 2
X_8P4C-10P
C392 X_10P
C437 X_10P
C435 X_10P
Near CK-Gen in 0.5" .
C395 X_5P/X7R
C393 X_5P/X7R
C698 104P
ICS950402
Strapping CPU
FS0FS2FS3
B B
0000
000
00 0
00
000
00
00
0
***
1
11
11
111
11
11 1
A A
111
1111
ModeA ModeB
***
5
FS1
1
11
1
11
11
111
000
00
00
0
00
0
00
01
10
11
HTTCLK0
ModeA In
PCICLK7 PCICLK8 PCICLK9 PCICLK10
ModeA In
4
100.90
133.90
1
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
0
300.00
Pin6 Pin7
HTT
PCI
MHz
MHz
MHz
67.27 33.63
33.48
66.95
33.60
67.20
33.67
67.33
33.40
66.80
33.38
66.75
33.34
66.68
33.40
66.80
33.00
60.00
33.00
60.00
35.00
70.00
30.00
60.00
33.75
67.50
33.33
66.67
33.33
66.67
37.50
75.00
Pin8 Pin11
HTTCLK1 HTTCLK2 PCICLK10
HTTCLK1 HTTCLK2 HTTCLK3
PCICLK8 PCICLK9 PCICLK10
VCC3
FB6 X_120S/0805
CP28
X_COPPER
ICS950403 didn't support ModeC
*** => Default Setting
ModeC Pin24
01PCICLK6
***
PCI_STOP#
3
C695
4.7u/0805
CLKVDDA
VCC3
C422
104P
For EMI
VCC3 VCC
"FS0~FS3" are all internal
pull-up via 100K ohm ..
FS0
FS2
FS1
48MHZ
"48MHZ" is "FS3" in ICS950402 ,
But not in cy28330 .
ModeA,B=0:0 ( Set Pin 7,8 clock
-> 66 MHz Pin11->33Mhz )
MODEB
MODEA
"24_48MHZ/SEL" Freq.-Out select pin
=> Low->48MHz , Hi->24MHz .
( Internal pull-up via 100K ohm )
SEL_24
FB3 X_120S/0805
C421
104P
C424 X_104P
C505 X_104P
R301 10K
R309 10K
R302 10K
R331 10K
R718 10K
R605 10K
R348 10K
CP19
X_COPPER
CLKVCC3
2
C418
4.7u/0805
CLKVCC3
R1667 X10K
Title
Document Number
CLKVCC3
C414
104P
TURBO#
Micro Star Restricted Secret
Clock Synthesizer
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-6702
1
Last Revision Date:
Wednesday, June 25, 2003
Sheet
742
of
Rev
0D
5
104P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
C51
DR_MD[63..0]9,10,11
D D
C C
B B
VDD_25_SUS
R220 4.7K
-MSWEA4,10
DDR_VREF
VREF routed as 40~50
mils trace wide ,
Space>25 mils
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
Place 104p and 1000p Cap. near the DIMM
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VSS0
VSS1
VSS2
VSS3
VSS4
3111826344250586674818993
VDD8
VSS5
VDDQ0
VDDQ1
VSS6
VSS7
4
SYSTEM MEMORY
104
112
128
136
143
156
164
172
1801582
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
184
PIN
DDR DIMM
SOCKET
NC(RESET#)
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
116
124
132
139
145
152
160
176
184
VDDID
VDDQ15
VDDSPD
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
DDR1
DDRDIMM_184
N13-1840061-K06
3
R213 4.7K
DDR_VREF
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
-MCS0
157
-MCS1
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
-DR_MDQS8
47
103
MAA0
48
MAA1
43
MAA2
41
MAA3
130
MAA4
37
MAA5
32
MAA6
125
MAA7
29
MAA8
122
MAA9
27
MAA10
141
MAA11
118
MAA12 MAB12
115
MAA13
167
59
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
DR_CHECK0
44
DR_CHECK1
45
DR_CHECK2
49
DR_CHECK3
51
DR_CHECK4
134
DR_CHECK5
135
DR_CHECK6
142
DR_CHECK7
144
MEMCLK_H5
16
MEMCLK_L5
17
MEMCLK_H0
137
MEMCLK_L0
138
MEMCLK_H7
76
MEMCLK_L7
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_DM0
97
DR_DM1
107
DR_DM2
119
DR_DM3
129
DR_DM4
149
DR_DM5
159
DR_DM6
169
DR_DM7
177
DR_DM8
140
-MCS0 4,10
-MCS1 4,10
-DR_MDQS0 9,10,11
-DR_MDQS1 9,10,11
-DR_MDQS2 9,10,11
-DR_MDQS3 9,10,11
-DR_MDQS4 9,10,11
-DR_MDQS5 9,10,11
-DR_MDQS6 9,10,11
-DR_MDQS7 9,10,11
-DR_MDQS8 9,10,11
MAA[13..0]
MEMBANKA0 4,10
MEMBANKA1 4,10
SMBCLK1 7,9,18,36
SMBDATA1 7,9,18,36
DR_CHECK[7..0] 9,10,11
MEMCLK_H5 4,10
MEMCLK_L5 4,10
MEMCLK_H0 4,10
MEMCLK_L0 4,10
MEMCLK_H7 4,10
MEMCLK_L7 4,10
MCKE0 4,9,10
MCKE1 4,9,10
-MSCASA 4,10
-MSRASA 4,10
MAA[13..0] 4,10
VDD_25_SUS
-MSWEB4,9,10
2
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
3111826344250586674818993
104
112
128
136
143
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
184
DDR DIMM
SOCKET
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
100
116
124
132
156
164
172
VDDQ11
VDDQ12
VDDQ13
PIN
VSS17
VSS18
VSS19
139
145
152
1801582
VDDQ14
VDDQ15
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
160
176
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK2(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
A0
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
DDR2
DDRDIMM_184
N13-1840061-K06
-MCS2
-MCS3
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
-DR_MDQS8
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB13
MEMBAKB0
MEMBAKB1
SMBCLK1
SMBDATA1
DR_CHECK0
DR_CHECK1
DR_CHECK2
DR_CHECK3
DR_CHECK4
DR_CHECK5
DR_CHECK6
DR_CHECK7
DIMM2_CK3
DIMM2_CK#3
DIMM2_CK4
DIMM2_CK#4
DIMM2_CK5
DIMM2_CK#5
MCKE0
MCKE1
-MSCASB
-MSRASB
1
-MCS2 4,10
-MCS3 4,10
MAB[13..0] 4,9,10
MEMBAKB0 4,9,10
MEMBAKB1 4,9,10
VDD_25_SUS
DIMM2_CK3 9
DIMM2_CK#3 9
DIMM2_CK4 9
DIMM2_CK#4 9
DIMM2_CK5 9
DIMM2_CK#5 9
-MSCASB 4,9,10
-MSRASB 4,9,10
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
DR_DM8
Place near the DIMM
VDD_25_SUS
R72
1KST
A A
R66
1KST
C32
X104P
DDR_VREF
C44
105P/0805
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF 4,9
5
DIMM1 SLAVE ADDRESS
= (1010000X)B = A0
4
DR_DM[8..0]
DR_DM[8..0] 9,10,11
3
DIMM2 SLAVE ADDRESS
= (1010001X)B = A2
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Micro Star Restricted Secret
System Memory : DDR DIMM 1
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
842
1
of
Rev
0E
5
4
3
2
1
SYSTEM MEMORY
VDD_25_SUS
738467085
108
120
148
D D
VDD0
VDD1
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
R223 4.7K
C33
104P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP3
DR_MD[63..0]8,10,11
C C
B B
VDD_25_SUS
-MSWEB4,8,10
DDR_VREF4,8
VREF routed as 40~50
mils trace wide ,
Space>25 mils
-MSWEB
DDR_VREF
Place 104p and 1000p Cap. near the DIMM
168223054627796
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
3111826344250586674818993
104
112
128
136
143
156
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
184
DDR DIMM
SOCKET
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
100
116
124
132
139
164
172
1801582
VDDQ11
VDDQ12
VDDQ13
PIN
VSS17
VSS18
VSS19
145
152
160
VDDID
VDDQ14
VDDQ15
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
184
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VDDSPD
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
A0
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
DDR3
DDRDIMM_184
N13-1840061-K06
-MCS4
-MCS5
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
-DR_MDQS8
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MEMBAKB0
MEMBAKB1
SMBCLK1
SMBDATA1
VDD_25_SUS
DR_CHECK0
DR_CHECK1
DR_CHECK2
DR_CHECK3
DR_CHECK4
DR_CHECK5
DR_CHECK6
DR_CHECK7
DIMM3_CK0
DIMM3_CK#0
DIMM3_CK1
DIMM3_CK#1
DIMM3_CK2
DIMM3_CK#2
MCKE0
MCKE1
-MSCASB
-MSRASB
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
DR_DM8
-MCS4 4,10
-MCS5 4,10
-DR_MDQS0 8,10,11
-DR_MDQS1 8,10,11
-DR_MDQS2 8,10,11
-DR_MDQS3 8,10,11
-DR_MDQS4 8,10,11
-DR_MDQS5 8,10,11
-DR_MDQS6 8,10,11
-DR_MDQS7 8,10,11
-DR_MDQS8 8,10,11
MAB[13..0] 4,8,10
MEMBAKB0 4,8,10
MEMBAKB1 4,8,10
SMBCLK1 7,8,18,36
SMBDATA1 7,8,18,36
DR_CHECK[7..0] 8,10,11
MCKE0 4,8,10
MCKE1 4,8,10
-MSCASB 4,8,10
-MSRASB 4,8,10
DR_DM[8..0] 8,10,11
Clock Buffer (DDR)
VDD_25_SUS
C184
X_104P
VDD_25_SUS
DIMM2_CK38 DIMM2_CK#3 8
CBVDD
AVDD25
SMBCLK1
SMBDATA1
MEMCLK_H14
MEMCLK_H1
R1669
R1668
X1K
X1K
INTERNAL PUU-DOWN ADDRESS=D4H
C1
104P
R1670
X1K
DIMM2_CK3
DIMM3_CK0
DIMM2_CK4
DIMM3_CK1
DIMM3_CK2
DIMM2_CK5
3
12
23
10
7
22
8
21
18
9
CP5 X_COPPER
L14
X_0/0805
C183
104P
CP6 X_COPPER
L15
X_0/0805
Near U8
R624 X120RST
R625 X120RST
R626 X120RST
R627 X120RST
R628 X120RST
R629 X120RST
U8
ICS93737BF-SSOP28
_
VDD
VDD
VDD
AVDD
SCLK
SDATA
CLK_INT
CS_PROG1
CS_PROG0
AD_SEL
GND
GND
111528
6
GND
GND
C176
104P
C185
X_105P/0805
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
RSTEP
RFIX
DIMM2_CK#3
DIMM3_CK#0
DIMM2_CK#4
DIMM3_CK#1
DIMM3_CK#2
DIMM2_CK#5
2
4
13
17
24
26
1
5
14
16
25
27
19
20
C152
104P
R127
R1665
C153
104P
DIMM2_CK#4 8DIMM2_CK48
DIMM2_CK#5 8DIMM2_CK58
DIMM2_CK3
DIMM3_CK0
DIMM2_CK4
DIMM3_CK1
DIMM3_CK2
DIMM2_CK5
DIMM2_CK#3
DIMM3_CK#0
DIMM2_CK#4
DIMM3_CK#1
DIMM3_CK#2
DIMM2_CK#5
1K
1K
C177
104P
CBVDD
AVDD25
A A
DIMM3 SLAVE ADDRESS
= (1010010X)B = A4
5
4
3
MEMCLK_L14
MEMCLK_L1
C1563
10P/X7R
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
System Memory : DDR DIMM 2
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
1
Rev
0E
942
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
DR_MD40
DR_MD39
DR_MD35
D D
DR_MD59
DR_MD63
DR_MD58
DR_MD62
-DR_MDQS7
DR_DM7
DR_MD57
DR_MD61
DR_MD56
DR_MD60
DR_MD51
DR_MD55
C C
B B
-MSCASA4,8
-MSRASB4,8,9
-MSRASA4,8
MEMBANKA04,8
MEMBAKB04,8,9
A A
DR_MD50
DR_MD54
-DR_MDQS6
DR_DM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD49
DR_MD48
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_DM5
-DR_MDQS5
-MCS1
-MCS14,8
-MCS0
-MCS04,8
-MSCASA
DR_MD41
-MSWEB
-MSWEB4,8,9
DR_MD45
-MSRASB
DR_MD44
-MSRASA
RN67 8P4R-47
7 8
5 6
3 4
1 2
RN65 8P4R-47
7 8
5 6
3 4
1 2
RN63 8P4R-47
7 8
5 6
3 4
1 2
RN61 8P4R-47
7 8
5 6
3 4
1 2
RN59 8P4R-47
7 8
5 6
3 4
1 2
RN57 8P4R-47
7 8
5 6
3 4
1 2
RN55 8P4R-47
7 8
5 6
3 4
1 2
RN53 8P4R-47
7 8
5 6
3 4
1 2
RN52 8P4R-47
7 8
5 6
3 4
1 2
RN50 8P4R-47
7 8
5 6
3 4
1 2
MEMBAKB14,8,9
DR_MD38
DR_MD34
DR_DM4
-DR_MDQS4
DR_MD37
DR_MD33
DR_MD36
DR_MD32
DR_CHECK7
DR_CHECK3
DR_CHECK6
DR_CHECK2
DR_DM8
-DR_MDQS8
DR_CHECK1
DR_CHECK0
DR_CHECK5
DR_CHECK4
DR_MD31
DR_MD27
MAA1
MAB1
MAA2
MAB2
MAA3
MAA4
MAB4
MAA6
DR_MD30
MAB3
DR_MD26
DR_DM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
MAB6
MAB5
MAA5
MAA8
RN48 8P4R-47
7 8
5 6
3 4
1 2
RN46 8P4R-47
7 8
5 6
3 4
1 2
RN45 8P4R-47
7 8
5 6
3 4
1 2
RN44 8P4R-47
7 8
5 6
3 4
1 2
RN41 8P4R-47
7 8
5 6
3 4
1 2
RN37 8P4R-47
7 8
5 6
3 4
1 2
RN33 8P4R-47
7 8
5 6
3 4
1 2
RN30 8P4R-47
7 8
5 6
3 4
1 2
RN29 8P4R-47
7 8
5 6
3 4
1 2
RN28 8P4R-47
7 8
5 6
3 4
1 2
RN26 8P4R-47
7 8
5 6
3 4
1 2
DR_MD24
DR_MD19
DR_MD23
MAA7
DR_DM2
MAA9
MAA11
MAA12
MAB8
DR_MD22
MAB7
DR_MD18
MAB9
MAB11
DR_MD21
-DR_MDQS2
DR_MD17
MAB12
DR_MD16
DR_MD20
DR_MD11
DR_MD10
DR_MD15
DR_MD14
DR_DM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD7
DR_MD6
DR_MD2
DR_DM0
-DR_MDQS0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
For DIMM1 Clock
MEMCLK_H5
MEMCLK_H0
R99 X120RST
R122 X120RST
R107 X120RST
5
MEMCLK_L5
MEMCLK_L7MEMCLK_H7
MEMCLK_L0
4
MAB10
MAB0
MAA10
MAA0
RN24 8P4R-47
7 8
5 6
3 4
1 2
RN22 8P4R-47
7 8
5 6
3 4
1 2
RN21 8P4R-47
7 8
5 6
3 4
1 2
RN19 8P4R-47
7 8
5 6
3 4
1 2
RN17 8P4R-47
7 8
5 6
3 4
1 2
RN15 8P4R-47
7 8
5 6
3 4
1 2
RN12 8P4R-47
7 8
5 6
3 4
1 2
RN10 8P4R-47
7 8
5 6
3 4
1 2
RN9 8P4R-47
7 8
5 6
3 4
1 2
RN8 8P4R-47
7 8
5 6
3 4
1 2
RN126 8P4R-47
7 8
5 6
3 4
1 2
3
VTT_DDR_SUS
MCKE04,8,9
MCKE14,8,9
-MCS3
-MCS34,8
-MCS2
-MCS24,8
-MSCASB4,8,9
-MSCASB
-MSWEA
-MSWEA4,8
-MCS4
-MCS44,9
-MCS5
-MCS54,9
R648 47
R649 47
RN127 8P4R-47
7 8
5 6
3 4
1 2
R1606 47
R1607 47
-MSCASB4,8,9
-MSCASA4,8
-MSRASB4,8,9
-MSRASA4,8
-MSWEA4,8
-MSWEB4,8,9
MEMBAKB14,8,9
MEMBANKA14,8
MEMBAKB04,8,9
MEMBANKA04,8
DR_DM[8..0]8,9,11MEMBANKA14,8
MEMCLK_L[7..0]4,8,9
MEMCLK_H[7..0]4,8,9
-DR_MDQS[8..0]8,9,11
DR_MD[63..0]8,9,11
MAB[13..0]4,8,9
MAA[13..0]4,8
DR_CHECK[7..0]8,9,11
DR_DM[8..0]
MEMCLK_L[7..0]
MEMCLK_H[7..0]
-DR_MDQS[8..0]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_CHECK[7..0]
2
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
-MCS2
-MCS24,8
-MCS3
-MCS34,8
MAB13
MAA13
MAB12
MAA12
MAB11
MAA11
MAB1
MAA1
MAB3
MAA3
MAB2
MAA2
MAB6
MAA6
MAB4
MAA4
MAB8
MAA8
MAA5
MAB5
MAA0
MAA10
MAB0
MAB10
-MSCASB
-MCS0
-MCS04,8
-MSCASA
-MCS1
-MCS14,8
MAA9
MAB9
MAB7
MAA7
-MSRASB
-MSRASA
-MSWEA
-MSWEB
MCKE14,8,9
MCKE04,8,9
-MCS4
-MCS5
Micro Star Restricted Secret
DDR Terminations Bank 0
VTT_DDR_SUS
CN21
8P4C-22P
CN6
8P4C-22P
CN11
8P4C-22P
CN10
8P4C-22P
CN8
8P4C-22P
CN9
8P4C-22P
CN15
8P4C-22P
CN19
8P4C-22P
CN7
8P4C-22P
CN18
8P4C-22P
CN17
8P4C-22P
CN3
8P4C-22P
C1532 22P
C1533 22P
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
1
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
10 42
of
Rev
0E
5
4
3
2
1
LAYOUT: Place on backside,
R661 0
MD38
RN42 8P4R-0
MEMCHECK7 DR_CHECK7
DDR Terminations
R657 0
D D
C C
B B
-MDQS0 -DR_MDQS0
RN11 8P4R-0
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN13 8P4R-0
DM0
1 2
3 4
MD6 DR_MD6
5 6
MD7 DR_MD7
7 8
RN16 8P4R-0
1 2
MD8 DR_MD8
3 4
MD9 DR_MD9
5 6
7 8
R658 0
MD15
RN18 8P4R-0
-MDQS1
1 2
MD13 DR_MD13
3 4
DM1
5 6
MD14 DR_MD14
7 8
RN23 8P4R-0
1 2
MD17
3 4
MD21 DR_MD21
5 6
DM2
7 8
R659 0
MD18
RN20 8P4R-0
MD10
1 2
3 4
MD20 DR_MD20
5 6
MD16 DR_MD16
7 8
RN25 8P4R-0
1 2
MD23 DR_MD23
3 4
5 6
MD24
7 8
RN27 8P4R-0
1 2
MD29
3 4
5 6
-MDQS3
7 8
RN32 8P4R-0
MD26
1 2
3 4
MD27
5 6
MD31 DR_MD31
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
DR_DM0
DR_MD2MD2
DR_MD3MD3
DR_MD12MD12
DR_MD15
-DR_MDQS1
DR_DM1
-DR_MDQS2-MDQS2
DR_MD17
DR_DM2
DR_MD18
DR_MD10
DR_MD11MD11
DR_MD22MD22
DR_MD19MD19
DR_MD24
DR_MD28MD28
DR_MD29
DR_MD25MD25
-DR_MDQS3
DR_MD26
DR_MD30MD30
DR_MD27
-MDQS7
MD63
MEMCHECK5
MEMCHECK0
MEMCHECK1
-MDQS8
1 2
3 4
5 6
7 8
RN47 8P4R-0
1 2
-MDQS4 -DR_MDQS4
3 4
DM4
5 6
MD34 DR_MD34
7 8
R662 0
MD42
RN49 8P4R-0
MD35 DR_MD35
1 2
MD39 DR_MD39
3 4
5 6
MD44 DR_MD44
7 8
RN51 8P4R-0
1 2
MD41 DR_MD41
3 4
-MDQS5 -DR_MDQS5
5 6
DM5 DR_DM5
7 8
RN54 8P4R-0
MD43
1 2
MD46 DR_MD46
3 4
MD47 DR_MD47
5 6
7 8
RN58 8P4R-0
1 2
3 4
MD53 DR_MD53
5 6
7 8
R663 0
MD51
RN60 8P4R-0
1 2
3 4
MD50
5 6
MD55
7 8
RN62 8P4R-0
1 2
MD56
3 4
MD61 DR_MD61
5 6
MD57 DR_MD57
7 8
RN64 8P4R-0
DM7
1 2
3 4
MD62 DR_MD62
5 6
MD58
7 8
R707 0
R664 0
RN34
1 2
3 4
5 6
7 8
8P4R-0
DM8
MEMCHECK2 DR_CHECK2
-MDQS[8..0]4
-DR_MDQS[8..0]8,9,10
DR_MD[63..0]8,9,10
MD[63..0]4
A A
MEMCHECK[7..0]4
DR_CHECK[7..0]8,9,10
DR_DM[8..0]8,9,10
DM[8..0]4
-MDQS[8..0]
-DR_MDQS[8..0]
DR_MD[63..0]
MD[63..0]
MEMCHECK[7..0]
DR_CHECK[7..0]
DR_DM[8..0]
DM[8..0]
5
MEMCHECK6
MEMCHECK3
MEMCHECK4
DM3
RN38
1 2
3 4
5 6
7 8
8P4R-0
R665 0
R660 0
4
DR_MD38
DR_MD32MD32
DR_MD36MD36
DR_MD33MD33
DR_MD37MD37
DR_DM4
DR_MD42
DR_MD40MD40
DR_MD45MD45
DR_MD43
DR_MD48MD48
DR_MD49MD49
DR_MD52MD52
DR_DM6DM6
DR_MD51
-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55
DR_MD60MD60
DR_MD56
DR_DM7
-DR_MDQS7
DR_MD58
DR_MD59MD59
DR_MD63
DR_CHECK5
DR_CHECK0
DR_CHECK1
-DR_MDQS8
DR_DM8
DR_CHECK6
DR_CHECK3
DR_DM3
DR_CHECK4
evenly spaced around VTT fill.
C104
C118
C138
C145
C149
C93
104P
104P
C209
X_4.7u/0805
C217
4.7u/0805
VTT_DDR_SUS
C28
X_0.22u
{nopop}
C285
X_0.22u
{nopop}
C11
X_0.22u
{nopop}
X_0.22u
{nopop}
104P
104P
X_100PC12
X_0.22uC14
GND
102PC190
C100
C213
C288
0.22uC165
104P
104P
C107
C220
C164
4.7u/0805
GND
C154
104P
C156
104P
C163
104P
C170
104P
C178
104P
C186
104P
C192
104P
104P
C121
104P
104P
C131
104P
C233
104P
C242
LAYOUT: Locate close to
Clawhammer socket.
104P
C114
C226
2
104P
104P
C141
C252
104P
104P
104P
104P
104P
104P
104P
C200
C208
C212
C215
C223
C231
C238
104P
104P
C146
C263
C155
104P
104P
C151
104P
104P
C266
C270
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
VDD_25_SUS
VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C37
104P
104P
C111
104P
104P
C128
104P
104P
104P
104P
C90
C83
104P
104P
C53
C68
104P
C81
104P
C85
104P
C91
104P
C97
104P
VTT_DDR_SUS
C49
104P
104P
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.
C71
C59
104P
VTT_DDR_SUS
C173
104P
C182
C189
C197
104P
C206
104P
104P
VTT_DDR_SUS
0.22uC79
X_0.22uC61
C67
4.7u/0805
C66
4.7u/0805
C16
VTT_DDR_SUS
X_100PC295
X_102PC289
C292
X_4.7u/0805
3
C239
X_4.7u/0805
X_0.22uC229
LAYOUT: Locate close
to Clawhammer socket.
VTT_DDR_SUS
+
EC61
1000U/6.3V
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS
C248
104P
C259
104P
C265
104P
C268
104P
C272
104P
C281
104P
104P
104P
C167
GND
C282
GND
104P
104P
104P
104P
C157
C274
DDR Terminations Bank 1
MS-6702
Last Revision Date:
Wednesday, June 25, 2003
Sheet
1
+
EC62
1000U/6.3V
GND
11 42
of
Rev
0E
A
B
C
K8T400M HT Interface
D
E
Reserved
VAVDD2
C203
X_103P
VDD_12_A
VAGND2
VAVDD2
4 4
A10
A24
A25
A26
B10
B24
B26
C10
C24
C25
A9
B9
B23
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
J10
G24
G23
H22
K22
N22
M22
N24
N23
R22
P22
R24
R23
H26
G26
H24
H25
K26
K24
K25
M24
M25
P26
N26
P24
P25
R26
M26
K12
K13
K14
K15
K16
K17
VLDT
RCADP15
RCADN15
J22
RCADP14
RCADN14
J24
RCADP13
J23
RCADN13
L22
RCADP12
RCADN12
RCADP11
RCADN11
RCADP10
RCADN10
RCADP9
RCADN9
RCADP8
RCADN8
RCADP7
RCADN7
RCADP6
RCADN6
RCADP5
J26
RCADN5
RCADP4
RCADN4
RCADP3
RCADN3
RCADP2
RCADN2
RCADP1
RCADN1
T26
RCADP0
RCADN0
L24
RCLKP1
L23
RCLKN1
RCLKP0
L26
RCLKN0
F24
RCTLP
F25
RCTLN
J18
VSS
F13
VSS
F18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
From Claw Hammer
CADON[15:0]4
CADOP[15:0]4
3 3
2 2
CADOP15
CADOP14
CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2
CADOP1
CADOP0
CLKOP14
CLKON14
CLKOP04
CLKON04
CTLOP04
CTLON04
CADON15
CADON14
CADON13
CADON12
CADON11
CADON10
CADON9
CADON8
CADON7
CADON6
CADON5
CADON4
CADON3
CADON2
CADON1
CADON0
CLKOP1
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
VLDT
C11D9D10
C9
B25
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
C23
D22
D23
D24
D11E9E10
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
E22
E23
E24
F10
E11
E21
VLDT
VLDT
VLDT
VLDT
VLDT
F15
F11
F16
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
G22
F21
F23
G21
F19
F22
H21
F20
VLDT
VLDT
J11
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
H14
H17
NC_H13
NC_H14
H18
NC_H18
NC_H17
TCADP15
TCADN15
TCADP14
TCADN14
TCADP13
TCADN13
TCADP12
TCADN12
TCADP11
TCADN11
TCADP10
TCADN10
TCADP9
TCADN9
TCADP8
TCADN8
TCADP7
TCADN7
TCADP6
TCADN6
TCADP5
TCADN5
TCADP4
TCADN4
TCADP3
TCADN3
TCADP2
TCADN2
TCADP1
TCADN1
TCADP0
TCADN0
TCLKP1
TCLKN1
TCLKP0
TCLKN0
TCTLP
TCTLN
RNCOMP
RTCOMP
RPCOMP
LDTRST
LDTSTOP
C22C21
U10A
K8T400M_#A
B01-0838505-V01
AVDD2AVSS2
E20
D21
D19
C19
E18
E19
D17
C17
D15
C15
E14
E15
D13
C13
E12
E13
B20
C20
A19
A20
B18
C18
A17
A18
A15
A16
B14
C14
A13
A14
B12
C12
E16
E17
B16
C16
A21
A22
D26
C26
D25
B11
A12
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
CLKIP1
CLKIN1
CLKIP0
CLKIN0
CTLIP0
CTLIN0
PNCOMP
RTCOMP
RPCOMP
-LDTRST
-LDTSTOP
To Claw Hammer
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP2
CADIP1
CADIP0
CLKIP1 4
CLKIN1 4
CLKIP0 4
CLKIN0 4
CTLIP0 4
CTLIN0 4
-LDTRST 38
-LDTSTOP 5,19
CADIN[15:0] 4
CADIP[15:0] 4
PNCOMP
RTCOMP
RPCOMP
C204 104P
Around NB
C641
X_104P/BACK
Decoupling capacitors
at NB BGA Area (On
Solder Layer)
R152 49.9RST
R140 100RST
R151 49.9RST
VDD_12_A
VDD_12_A
VDD_12_A
H13
J12
J13
J14
J15
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
U26
VLDT
VLDT
V21
V22
V23
V24
V25
V26
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
M18
N18
J17
K18
J16
N21
K21
L21
L18
VLDT
P18
P21
R18
T18
T21
T23
T24
T25
T22
U18
U21
U22
U23
U24
VLDT
U25
VSS
VSS
VSS
VSS
K10
VSS
VSS
VSS
VSS
M10
N10
P10
R10
L10
T10
K11
U10
VSS
NC_N19
NC_P3
NC_P2
NC_K8
NC_L8
NC_J19
NC_P4
NC_P19
P19
N19
P3
P2
K8
L8
J19
P4
VDD_12_A
VAGND2
1 1
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet
MS-6702
NORTH BRIDGE K8T400M/VER:0.4 (H T)
MS-6702
12 42Wednesday, June 25, 2003
E
0E
of
A
K8T400M AGP 8X ,V-Link, Misc. Control
VCC2_5
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
W14
W13
W12
AF18
AD18
AE18
AF17
AD17
AD16
AE16
AF16
AF14
AD14
AD13
AE13
AF13
AD12
AF12
AE12
AD10
AE10
AF10
AD9
AF9
AF8
AE9
AD8
AF6
AD7
AE6
AD5
AF5
AF4
AE4
AD4
AC2
AC3
AD1
AD2
AF2
AD3
AE3
AF3
AD15
AF11
AD11
AC7
AE15
AF15
AE7
AF7
AF1
AE1
AC5
AC4
AC9
AC10
AC14
AC11
AC12
AC16
AD6
AC1
AA3
AC15
AA2
AA1
AB1
A11
AC13
AC6
W1
4 4
GAD[31:0]16
3 3
SBA016
SBA116
SBA216
SBA316
SBA416
SBA516
SBA616
SBA716
GC/BE#016
GC/BE#116
GC/BE#216
GC/BE#316
AD_STBF016
AD_STBS016
AD_STBF116
AD_STBS116
SB_STBF16
2 2
SB_STBS16
GFRAME16
GIRDY16
GTRDY16
GDEVSEL16
GSTOP16
GPAR16
GREQ16
GGNT16
GSERR16
AGP8XDET#16
GCLK_NB7
AGPVREF_GC16
1 1
DBIH16
DBIL16
RBF16
WBF16
ST016
ST116
ST216
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1
SB_STBF
SB_STBS
DBIH
DBIL
AGPPCOMP
AGPNCOMP AGPPCOMP
AGPVREF_GC
A
U1T2T3T4T5T8T9U2U3U4U5U8U9V2V3
M8
N8
VDD
Y1
Y2
V1
VDD
VDD
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GD16
GD17
GD18
GD19
GD20
GD21
GD22
GD23
GD24
GD25
GD26
GD27
GD28
GD29
GD30
GD31
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
C/BE0
C/BE1
C/BE2
C/BE3
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1
SB_STBF
SB_STBS
DBIH
DBIL
GFRAME
GIRDY
GTRDY
GDEVSEL
GSTOP
GPAR
RBF
WBF
GREQ
GGNT
GSERR
AGP8XDET
ST0
ST1
ST2
GCLK
AGPPCOMP
AGPNCOMP
AGPVREF0
AGPVREF1
VCCQQ
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VSSQQ
T1
VCC1
VCC1
VCC1
VSS
VSS
P5R1R2R3R4
A8
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
B
VDDQ
V4V5V8
V10
V11
V12
V13W2W3
W4W5W9
W25
VCC1
VSS
W26
VCC1
VSS
AB2
VCC1
VSS
AB3
VCC1
VSS
AB4
VCC1
VSS
VCC1
VSS
AB5
Y3Y4Y5
VCC1
VCC1
VSS
VSS
AB6
AB9
AA4
AA5
VCC1
VCC1
VSS
VSS
AB10
AB15
AB16
V9
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VSS
VSS
VSS
VSS
VSS
R5
R21
VSS
VSS
VSS
W21
W22
W23
W24
B
VCC1
VSS
AB7
AC8
VCC1
VSS
AB8
AC24
VCC1
VSS
AB11
AE2
VCC1
VSS
AB12
AE5
VCC1
VSS
AB13
AE8
VCC1
VSS
AB14
VCC1
VSS
VSS
AE11
AE14
AE17
VSS
C
VAVDD1
VSUS2_5
VSUS2_5
C1544
104P
E25
AC25
AVDD1
VSUS25
AE26
PWRGD
AD25
RESET
TESTIN
SUSST
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VBE
VPAR
LVREF
LCOMPP
UPCMD
DNCMD
DNSTB
DNSTB
UPSTB
UPSTB
DEBUG
PIPE#
RSVD3
RSVD0
RSVD2
RSVD6
RSVD5
NC_M5
NC_N1
NC_N2
NC_N3
NC_N4
NC_N5
NC_P1
NC_L5
NC_W8
NC_Y8
NC_Y9
NC_Y10
AVSS1
VSS
VSS
VSS
E26
AE20
AE22
AE25
AC26
AD26
V14
V15
V16
V17
W15
W16
W17
W18
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
AE21
AF19
LVREF_NB
AF21
LCOMPP
AD19
AF26
AD23
AF22
AD22
AE23
AF23
AC17
M1
L3
L4
M2
M3
M4
M5
N1
N2
N3
N4
N5
P1
L5
W8
Y8
Y9
Y10
U10B
K8T400M_#B
B01-0838505-V01
TESTIN
PWROK_NB# 18
PCIDEVRST# 7,24,27,30,35,36
SUSST# 18
VCC2_5
VLAD0 19
VLAD1 19
VLAD2 19
VLAD3 19
VLAD4 19
VLAD5 19
VLAD6 19
VLAD7 19
VBE0# 19
VPAR 19
UPCMD 19
DNCMD 19
DNSTB 19
DNSTB# 19
UPSTB 19
UPSTB# 19
DEBUG
R180 10K
VAGND1
C
D
The voltage level of
LVREF_NB is
0.625V
D
E
Reserved
VAVDD1
VAGND1
V-Link ->
LVREF=0.625 Volt
VCC2_5
R176
3KST
C246
104P
LVREF_NB
R181
1KST
C250
104P
LAYOUT: Place caps on the bottom of NB
VDDQ
C648 X_104P/BACK
C650 X_104P/BACK
C656 X_104P/BACK
C647 X_104P/BACK
C658 X_104P/BACK
C671 X_104P/BACK
C640 X_104P/BACK
C663 X_104P/BACK
AGPVREF_GC
C307 105P/0805
C297 105P/0805
LAYOUT: Place caps as close NB as possible
TESTIN
VPAR
AGPNCOMP
LCOMPP
Title
Size Document Number Rev
C
MS-6702
NORTH BRIDGE K8T400M/VER:0.4 (AGP & VLINK)
Date: Sheet
R192 4.7K
R205 X_8.2K
R193 60.4RST
R187 60.4RST
R185 360RST
MS-6702
13 42Wednesday, June 25, 2003
E
C194
X_103P
VCC2_5
VDDQ
0E
of
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